Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_buf
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_seed_anchor.u_secure_anchor_buf.gen_generic.u_impl_generic 0.00 0.00
tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[0].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[1].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[2].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[3].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[4].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[5].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[6].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.gen_sw_assigns[7].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_seed_anchor.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[0].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[1].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[2].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[3].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[4].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[5].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[6].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_sw_assigns[7].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_buf
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_seed_anchor.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN15100.00
CONT_ASSIGN16100.00

14 logic [Width-1:0] inv; 15 0/1 ==> assign inv = ~in_i; 16 0/1 ==> assign out_o = ~inv;
Line Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_prim_buf_share0_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_prim_buf_share1_d.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_prim_buf_share0_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_prim_buf_share1_de.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%