Module Definition
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Module : prim_intr_hw
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_intr_op_done 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_intr_op_done

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_intr_hw
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Module : prim_intr_hw
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT48,T60,T49

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T60,T49
11CoveredT48,T60,T49

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T14,T15
10CoveredT2,T3,T4
11CoveredT1,T14,T16

Branch Coverage for Module : prim_intr_hw
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_intr_hw
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 875 875 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%