Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.32 99.32

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec 97.26 97.26
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec 97.95 97.95



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.26 97.26


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.26 97.26


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.95 97.95


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.95 97.95


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 292 290 99.32
Total Bits 0->1 146 145 99.32
Total Bits 1->0 146 145 99.32

Ports 4 3 75.00
Port Bits 292 290 99.32
Port Bits 0->1 146 145 99.32
Port Bits 1->0 146 145 99.32

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Yes Yes T121,T122,T123 Yes T121,T122,T123 OUTPUT
err_o[0] Yes Yes *T121,*T122,*T124 Yes T121,T122,T124 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] No No No OUTPUT
syndrome_o[1] Yes Yes *T124 Yes T124 OUTPUT
syndrome_o[4:2] No No No OUTPUT
syndrome_o[6:5] Yes Yes T124 Yes T124 OUTPUT
syndrome_o[7] No No No OUTPUT
err_o[0] Yes Yes *T124 Yes T124 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T14,T15 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T14,T15 Yes T1,T2,T3 OUTPUT
syndrome_o[0] No No No OUTPUT
syndrome_o[1] Yes Yes *T124 Yes T124 OUTPUT
syndrome_o[3:2] No No No OUTPUT
syndrome_o[5:4] Yes Yes T124 Yes T124 OUTPUT
syndrome_o[7:6] No No No OUTPUT
err_o[0] Yes Yes *T124 Yes T124 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T121 Yes T121 OUTPUT
syndrome_o[3:1] No No No OUTPUT
syndrome_o[4] Yes Yes *T121 Yes T121 OUTPUT
syndrome_o[5] No No No OUTPUT
syndrome_o[6] Yes Yes *T121 Yes T121 OUTPUT
syndrome_o[7] No No No OUTPUT
err_o[0] Yes Yes *T121 Yes T121 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[1:0] No No No OUTPUT
syndrome_o[2] Yes Yes *T122 Yes T122 OUTPUT
syndrome_o[3] No No No OUTPUT
syndrome_o[4] Yes Yes *T122 Yes T122 OUTPUT
syndrome_o[6:5] No No No OUTPUT
syndrome_o[7] Yes Yes T122 Yes T122 OUTPUT
err_o[0] Yes Yes *T122 Yes T122 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T125 Yes T125 OUTPUT
syndrome_o[3:1] No No No OUTPUT
syndrome_o[5:4] Yes Yes T125 Yes T125 OUTPUT
syndrome_o[7:6] No No No OUTPUT
err_o[0] Yes Yes *T125 Yes T125 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T122 Yes T122 OUTPUT
syndrome_o[1] No No No OUTPUT
syndrome_o[2] Yes Yes *T122 Yes T122 OUTPUT
syndrome_o[3] No No No OUTPUT
syndrome_o[4] Yes Yes *T122 Yes T122 OUTPUT
syndrome_o[7:5] No No No OUTPUT
err_o[0] Yes Yes *T122 Yes T122 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 284 97.26
Total Bits 0->1 146 142 97.26
Total Bits 1->0 146 142 97.26

Ports 4 2 50.00
Port Bits 292 284 97.26
Port Bits 0->1 146 142 97.26
Port Bits 1->0 146 142 97.26

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T123 Yes T123 OUTPUT
syndrome_o[2:1] No No No OUTPUT
syndrome_o[4:3] Yes Yes T123,*T121 Yes T123,T121 OUTPUT
syndrome_o[5] No No No OUTPUT
syndrome_o[7:6] Yes Yes T121 Yes T121 OUTPUT
err_o[0] Yes Yes *T121,*T123 Yes T121,T123 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 286 97.95
Total Bits 0->1 146 143 97.95
Total Bits 1->0 146 143 97.95

Ports 4 2 50.00
Port Bits 292 286 97.95
Port Bits 0->1 146 143 97.95
Port Bits 1->0 146 143 97.95

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[1:0] No No No OUTPUT
syndrome_o[7:2] Yes Yes T125,T123 Yes T125,T123 OUTPUT
err_o[0] Yes Yes *T123,*T125 Yes T123,T125 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%