Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_working_state.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_cmd.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_kmac_fsm.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_kmac_done.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_kmac_op.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_kmac_out.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_regfile_intg.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_shadow.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_intg.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_chk.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_reseed_cnt.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_side_ctrl_fsm.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_side_ctrl_sel.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fault_status_key_ecc.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_invalid_shadow_update.wr_en_data_arb 95.00 100.00 90.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_start.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sideload_clear.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_reseed_interval_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_version.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_0.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_1.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_2.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_3.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_4.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_5.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_6.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_7.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_0.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_1.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_2.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_7.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_op_status.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_err_code_invalid_op.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_err_code_invalid_kmac_input.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=2,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_op_status.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_op.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_kmac_input.wr_en_data_arb

SCORELINE
95.00 100.00
tb.dut.u_reg.u_err_code_invalid_shadow_update.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_start.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sideload_clear.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_version.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T1 T2 T3  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_reseed_interval_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T4 T14 T15  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Line Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=6,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_7.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16800

139 // WARN: we signal is actually read signal not write enable. 140 1/1 assign wr_en = we | de; Tests: T1 T2 T3  141 if (Mubi) begin : gen_mubi 142 if (DW == 4) begin : gen_mubi4 143 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 144 (we ? prim_mubi_pkg::MuBi4False : 145 prim_mubi_pkg::MuBi4True)); 146 end else if (DW == 8) begin : gen_mubi8 147 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 148 (we ? prim_mubi_pkg::MuBi8False : 149 prim_mubi_pkg::MuBi8True)); 150 end else if (DW == 12) begin : gen_mubi12 151 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 152 (we ? prim_mubi_pkg::MuBi12False : 153 prim_mubi_pkg::MuBi12True)); 154 end else if (DW == 16) begin : gen_mubi16 155 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 156 (we ? prim_mubi_pkg::mubi16_t'(wd) : 157 prim_mubi_pkg::MuBi16True)); 158 end else begin : gen_invalid_mubi 159 $error("%m: Invalid width for MuBi"); 160 end 161 end else begin : gen_non_mubi 162 1/1 assign wr_data = (de ? d : q) & (we ? '0 : '1); Tests: T1 T2 T3  163 end 164 // Unused wd - Prevent lint errors. 165 logic [DW-1:0] unused_wd; 166 //VCS coverage off 167 // pragma coverage off 168 unreachable assign unused_wd = wd;

Line Coverage for Module : prim_subreg_arb ( parameter DW=3,SwAccess=1,Mubi=0 + DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_working_state.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_cmd.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_kmac_fsm.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_kmac_done.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_kmac_op.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_kmac_out.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_regfile_intg.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_shadow.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_intg.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_chk.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_reseed_cnt.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_side_ctrl_fsm.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_side_ctrl_sel.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_fault_status_key_ecc.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=6,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_op_status.wr_en_data_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       140
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sideload_clear.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_op.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_kmac_input.wr_en_data_arb

SCORECOND
95.00 90.00
tb.dut.u_reg.u_err_code_invalid_shadow_update.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_start.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg.wr_en_data_arb

TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_reseed_interval_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT19,T5,T26
10CoveredT4,T14,T15

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT4,T14,T15
10CoveredT4,T14,T15
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T5,T26

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T15

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_version.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T14,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T15

Cond Coverage for Module : prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%