Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23397362	14831	0	0
attest_sw_binding_0_rd_A	23397362	3550	0	0
attest_sw_binding_1_rd_A	23397362	3520	0	0
attest_sw_binding_2_rd_A	23397362	3621	0	0
attest_sw_binding_3_rd_A	23397362	3347	0	0
attest_sw_binding_4_rd_A	23397362	3552	0	0
attest_sw_binding_5_rd_A	23397362	3595	0	0
attest_sw_binding_6_rd_A	23397362	3381	0	0
attest_sw_binding_7_rd_A	23397362	3469	0	0
intr_enable_rd_A	23397362	4053	0	0
key_version_rd_A	23397362	3537	0	0
max_creator_key_ver_regwen_rd_A	23397362	3488	0	0
max_owner_int_key_ver_regwen_rd_A	23397362	3656	0	0
max_owner_key_ver_regwen_rd_A	23397362	3646	0	0
reseed_interval_regwen_rd_A	23397362	3484	0	0
salt_0_rd_A	23397362	3481	0	0
salt_1_rd_A	23397362	3240	0	0
salt_2_rd_A	23397362	3412	0	0
salt_3_rd_A	23397362	3534	0	0
salt_4_rd_A	23397362	3333	0	0
salt_5_rd_A	23397362	3428	0	0
salt_6_rd_A	23397362	3373	0	0
salt_7_rd_A	23397362	3465	0	0
sealing_sw_binding_0_rd_A	23397362	3524	0	0
sealing_sw_binding_1_rd_A	23397362	3349	0	0
sealing_sw_binding_2_rd_A	23397362	3352	0	0
sealing_sw_binding_3_rd_A	23397362	3609	0	0
sealing_sw_binding_4_rd_A	23397362	3454	0	0
sealing_sw_binding_5_rd_A	23397362	3255	0	0
sealing_sw_binding_6_rd_A	23397362	3499	0	0
sealing_sw_binding_7_rd_A	23397362	3711	0	0
sideload_clear_rd_A	23397362	3599	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	14831	0	0
T48	33898	84	0	0
T49	0	200	0	0
T50	0	496	0	0
T51	0	868	0	0
T52	0	413	0	0
T53	0	1035	0	0
T54	0	165	0	0
T55	0	106	0	0
T56	0	481	0	0
T57	0	115	0	0
T58	25782	0	0	0
T59	2216	0	0	0
T60	54432	0	0	0
T61	4788	0	0	0
T62	9243	0	0	0
T63	6111	0	0	0
T64	3784	0	0	0
T65	7104	0	0	0
T66	5065	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3550	0	0
T54	37018	14	0	0
T55	0	75	0	0
T57	0	47	0	0
T83	0	36	0	0
T159	0	22	0	0
T181	0	59	0	0
T182	0	35	0	0
T183	0	25	0	0
T184	0	8	0	0
T185	0	77	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3520	0	0
T54	37018	26	0	0
T55	0	59	0	0
T57	0	33	0	0
T83	0	15	0	0
T120	0	62	0	0
T159	0	13	0	0
T181	0	44	0	0
T182	0	17	0	0
T183	0	35	0	0
T185	0	66	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3621	0	0
T54	37018	29	0	0
T55	0	71	0	0
T57	0	27	0	0
T83	0	6	0	0
T120	0	47	0	0
T159	0	19	0	0
T181	0	79	0	0
T182	0	21	0	0
T183	0	28	0	0
T185	0	65	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3347	0	0
T54	37018	34	0	0
T55	0	47	0	0
T57	0	34	0	0
T120	0	59	0	0
T159	0	10	0	0
T181	0	37	0	0
T182	0	45	0	0
T183	0	27	0	0
T185	0	83	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0
T195	0	27	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3552	0	0
T54	37018	26	0	0
T55	0	58	0	0
T57	0	37	0	0
T120	0	64	0	0
T159	0	14	0	0
T181	0	61	0	0
T182	0	30	0	0
T183	0	23	0	0
T185	0	54	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0
T195	0	40	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3595	0	0
T54	37018	30	0	0
T55	0	51	0	0
T57	0	27	0	0
T83	0	34	0	0
T120	0	53	0	0
T159	0	17	0	0
T181	0	66	0	0
T182	0	40	0	0
T183	0	38	0	0
T185	0	117	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3381	0	0
T54	37018	32	0	0
T55	0	59	0	0
T57	0	32	0	0
T83	0	17	0	0
T120	0	45	0	0
T159	0	7	0	0
T181	0	54	0	0
T182	0	38	0	0
T183	0	27	0	0
T185	0	76	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3469	0	0
T54	37018	28	0	0
T55	0	69	0	0
T57	0	35	0	0
T83	0	24	0	0
T120	0	51	0	0
T159	0	16	0	0
T181	0	43	0	0
T182	0	37	0	0
T183	0	16	0	0
T185	0	66	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	4053	0	0
T7	6325	0	0	0
T21	47981	0	0	0
T42	11194	0	0	0
T54	0	36	0	0
T55	0	88	0	0
T57	0	43	0	0
T67	7230	0	0	0
T128	156619	29	0	0
T131	0	10	0	0
T181	0	111	0	0
T182	0	56	0	0
T196	0	91	0	0
T197	0	19	0	0
T198	0	11	0	0
T199	4835	0	0	0
T200	6531	0	0	0
T201	7661	0	0	0
T202	5736	0	0	0
T203	8642	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3537	0	0
T54	37018	51	0	0
T55	0	57	0	0
T57	0	27	0	0
T120	0	57	0	0
T159	0	16	0	0
T181	0	48	0	0
T182	0	35	0	0
T183	0	24	0	0
T185	0	92	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0
T195	0	31	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3488	0	0
T54	37018	31	0	0
T55	0	57	0	0
T57	0	24	0	0
T120	0	35	0	0
T159	0	17	0	0
T181	0	49	0	0
T182	0	23	0	0
T183	0	46	0	0
T185	0	59	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0
T195	0	21	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3656	0	0
T54	37018	17	0	0
T55	0	73	0	0
T57	0	45	0	0
T83	0	40	0	0
T120	0	62	0	0
T159	0	25	0	0
T181	0	100	0	0
T182	0	18	0	0
T183	0	25	0	0
T185	0	47	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3646	0	0
T54	37018	23	0	0
T55	0	50	0	0
T57	0	19	0	0
T83	0	57	0	0
T120	0	50	0	0
T159	0	10	0	0
T181	0	76	0	0
T182	0	58	0	0
T183	0	46	0	0
T185	0	67	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3484	0	0
T54	37018	28	0	0
T55	0	70	0	0
T57	0	53	0	0
T83	0	9	0	0
T120	0	53	0	0
T159	0	18	0	0
T181	0	52	0	0
T182	0	66	0	0
T183	0	28	0	0
T185	0	67	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3481	0	0
T54	37018	30	0	0
T55	0	48	0	0
T57	0	28	0	0
T83	0	31	0	0
T120	0	35	0	0
T159	0	9	0	0
T181	0	62	0	0
T182	0	29	0	0
T183	0	27	0	0
T185	0	33	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3240	0	0
T54	37018	26	0	0
T55	0	36	0	0
T57	0	30	0	0
T83	0	17	0	0
T159	0	19	0	0
T181	0	42	0	0
T182	0	17	0	0
T183	0	9	0	0
T185	0	58	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0
T204	0	1	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3412	0	0
T54	37018	35	0	0
T55	0	39	0	0
T57	0	31	0	0
T83	0	17	0	0
T120	0	51	0	0
T159	0	18	0	0
T181	0	65	0	0
T182	0	30	0	0
T183	0	26	0	0
T185	0	80	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3534	0	0
T54	37018	36	0	0
T55	0	41	0	0
T57	0	21	0	0
T83	0	23	0	0
T120	0	36	0	0
T159	0	24	0	0
T181	0	58	0	0
T182	0	50	0	0
T183	0	32	0	0
T185	0	51	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3333	0	0
T54	37018	22	0	0
T55	0	76	0	0
T57	0	35	0	0
T83	0	7	0	0
T120	0	61	0	0
T159	0	12	0	0
T181	0	67	0	0
T182	0	40	0	0
T183	0	6	0	0
T185	0	53	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3428	0	0
T54	37018	5	0	0
T55	0	68	0	0
T57	0	23	0	0
T83	0	29	0	0
T120	0	30	0	0
T159	0	20	0	0
T181	0	57	0	0
T182	0	33	0	0
T183	0	8	0	0
T185	0	61	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3373	0	0
T54	37018	31	0	0
T55	0	74	0	0
T57	0	47	0	0
T83	0	18	0	0
T120	0	41	0	0
T159	0	12	0	0
T181	0	63	0	0
T182	0	28	0	0
T183	0	26	0	0
T185	0	73	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3465	0	0
T54	37018	24	0	0
T55	0	36	0	0
T57	0	19	0	0
T83	0	30	0	0
T120	0	58	0	0
T159	0	6	0	0
T181	0	63	0	0
T182	0	33	0	0
T183	0	19	0	0
T185	0	83	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3524	0	0
T54	37018	42	0	0
T55	0	78	0	0
T57	0	27	0	0
T83	0	14	0	0
T120	0	62	0	0
T159	0	8	0	0
T181	0	58	0	0
T182	0	20	0	0
T183	0	31	0	0
T185	0	36	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3349	0	0
T54	37018	27	0	0
T55	0	74	0	0
T57	0	24	0	0
T83	0	21	0	0
T120	0	37	0	0
T159	0	12	0	0
T181	0	74	0	0
T182	0	24	0	0
T183	0	16	0	0
T185	0	44	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3352	0	0
T54	37018	41	0	0
T55	0	59	0	0
T57	0	21	0	0
T83	0	14	0	0
T120	0	66	0	0
T159	0	13	0	0
T181	0	56	0	0
T182	0	26	0	0
T183	0	39	0	0
T185	0	78	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3609	0	0
T54	37018	26	0	0
T55	0	69	0	0
T57	0	26	0	0
T83	0	26	0	0
T120	0	29	0	0
T159	0	26	0	0
T181	0	61	0	0
T182	0	11	0	0
T183	0	26	0	0
T185	0	76	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3454	0	0
T54	37018	15	0	0
T55	0	50	0	0
T57	0	21	0	0
T83	0	26	0	0
T120	0	41	0	0
T159	0	7	0	0
T181	0	61	0	0
T182	0	24	0	0
T183	0	15	0	0
T185	0	56	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3255	0	0
T54	37018	33	0	0
T55	0	62	0	0
T57	0	53	0	0
T83	0	29	0	0
T120	0	55	0	0
T159	0	6	0	0
T181	0	80	0	0
T182	0	74	0	0
T183	0	30	0	0
T185	0	46	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3499	0	0
T54	37018	50	0	0
T55	0	49	0	0
T57	0	31	0	0
T83	0	11	0	0
T120	0	50	0	0
T159	0	9	0	0
T181	0	65	0	0
T182	0	40	0	0
T183	0	17	0	0
T185	0	56	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3711	0	0
T54	37018	35	0	0
T55	0	57	0	0
T57	0	39	0	0
T83	0	4	0	0
T120	0	54	0	0
T159	0	21	0	0
T181	0	63	0	0
T182	0	43	0	0
T183	0	28	0	0
T185	0	61	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23397362	3599	0	0
T54	37018	29	0	0
T55	0	66	0	0
T57	0	44	0	0
T83	0	25	0	0
T120	0	52	0	0
T159	0	22	0	0
T181	0	57	0	0
T182	0	38	0	0
T183	0	21	0	0
T185	0	90	0	0
T186	13896	0	0	0
T187	9156	0	0	0
T188	20236	0	0	0
T189	2972	0	0	0
T190	877	0	0	0
T191	67387	0	0	0
T192	5144	0	0	0
T193	4995	0	0	0
T194	13401	0	0	0