Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25344720	17458	0	0
attest_sw_binding_0_rd_A	25344720	1891	0	0
attest_sw_binding_1_rd_A	25344720	2140	0	0
attest_sw_binding_2_rd_A	25344720	1946	0	0
attest_sw_binding_3_rd_A	25344720	1907	0	0
attest_sw_binding_4_rd_A	25344720	2128	0	0
attest_sw_binding_5_rd_A	25344720	2025	0	0
attest_sw_binding_6_rd_A	25344720	1880	0	0
attest_sw_binding_7_rd_A	25344720	2084	0	0
intr_enable_rd_A	25344720	2415	0	0
key_version_rd_A	25344720	1972	0	0
max_creator_key_ver_regwen_rd_A	25344720	1872	0	0
max_owner_int_key_ver_regwen_rd_A	25344720	2026	0	0
max_owner_key_ver_regwen_rd_A	25344720	2061	0	0
reseed_interval_regwen_rd_A	25344720	2060	0	0
salt_0_rd_A	25344720	2024	0	0
salt_1_rd_A	25344720	2024	0	0
salt_2_rd_A	25344720	1958	0	0
salt_3_rd_A	25344720	1919	0	0
salt_4_rd_A	25344720	2080	0	0
salt_5_rd_A	25344720	1893	0	0
salt_6_rd_A	25344720	2006	0	0
salt_7_rd_A	25344720	2029	0	0
sealing_sw_binding_0_rd_A	25344720	2162	0	0
sealing_sw_binding_1_rd_A	25344720	2071	0	0
sealing_sw_binding_2_rd_A	25344720	1962	0	0
sealing_sw_binding_3_rd_A	25344720	2030	0	0
sealing_sw_binding_4_rd_A	25344720	2034	0	0
sealing_sw_binding_5_rd_A	25344720	1922	0	0
sealing_sw_binding_6_rd_A	25344720	2151	0	0
sealing_sw_binding_7_rd_A	25344720	1975	0	0
sideload_clear_rd_A	25344720	1954	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	17458	0	0
T7	0	44	0	0
T26	52666	325	0	0
T27	71815	0	0	0
T31	1998	0	0	0
T50	2440	0	0	0
T57	7360	0	0	0
T79	0	206	0	0
T110	5347	0	0	0
T111	5725	0	0	0
T112	12031	0	0	0
T113	9875	0	0	0
T114	0	465	0	0
T119	3819	0	0	0
T126	0	58	0	0
T127	0	436	0	0
T128	0	248	0	0
T129	0	32	0	0
T131	0	131	0	0
T133	0	399	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1891	0	0
T7	30534	43	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	30	0	0
T129	0	23	0	0
T147	0	6	0	0
T172	0	30	0	0
T189	0	49	0	0
T190	0	30	0	0
T191	0	3	0	0
T192	0	221	0	0
T193	0	1	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2140	0	0
T7	30534	35	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	32	0	0
T129	0	24	0	0
T147	0	12	0	0
T172	0	52	0	0
T189	0	72	0	0
T190	0	46	0	0
T191	0	15	0	0
T192	0	209	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	6	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1946	0	0
T7	30534	33	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	33	0	0
T129	0	49	0	0
T147	0	3	0	0
T172	0	25	0	0
T189	0	71	0	0
T190	0	22	0	0
T191	0	4	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	11	0	0
T201	0	2	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1907	0	0
T7	30534	22	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	23	0	0
T129	0	30	0	0
T147	0	2	0	0
T172	0	62	0	0
T189	0	60	0	0
T190	0	32	0	0
T191	0	5	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	7	0	0
T201	0	1	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2128	0	0
T7	30534	15	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	33	0	0
T129	0	50	0	0
T147	0	10	0	0
T172	0	36	0	0
T189	0	94	0	0
T190	0	38	0	0
T191	0	5	0	0
T192	0	237	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	13	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2025	0	0
T7	30534	31	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	34	0	0
T129	0	11	0	0
T147	0	11	0	0
T172	0	49	0	0
T189	0	73	0	0
T190	0	21	0	0
T191	0	10	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	12	0	0
T201	0	7	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1880	0	0
T7	30534	18	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	31	0	0
T129	0	24	0	0
T147	0	12	0	0
T172	0	42	0	0
T189	0	59	0	0
T190	0	21	0	0
T192	0	237	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	9	0	0
T201	0	6	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2084	0	0
T7	30534	20	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	40	0	0
T129	0	29	0	0
T147	0	5	0	0
T172	0	42	0	0
T189	0	77	0	0
T190	0	37	0	0
T191	0	2	0	0
T192	0	254	0	0
T193	0	17	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2415	0	0
T6	113731	0	0	0
T7	0	39	0	0
T9	3627	0	0	0
T53	126867	27	0	0
T63	0	13	0	0
T84	2152	0	0	0
T85	3606	0	0	0
T86	122101	0	0	0
T87	5185	0	0	0
T88	1565	0	0	0
T89	19271	0	0	0
T90	7565	0	0	0
T129	0	33	0	0
T189	0	91	0	0
T190	0	68	0	0
T202	0	46	0	0
T203	0	30	0	0
T204	0	25	0	0
T205	0	29	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1972	0	0
T7	30534	15	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T67	0	2	0	0
T124	0	32	0	0
T129	0	43	0	0
T147	0	11	0	0
T172	0	52	0	0
T189	0	69	0	0
T190	0	23	0	0
T191	0	10	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T206	0	4	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1872	0	0
T7	30534	16	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	17	0	0
T129	0	43	0	0
T147	0	8	0	0
T172	0	51	0	0
T189	0	81	0	0
T190	0	15	0	0
T191	0	4	0	0
T192	0	224	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T201	0	6	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2026	0	0
T7	30534	19	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	25	0	0
T129	0	25	0	0
T147	0	18	0	0
T172	0	43	0	0
T189	0	69	0	0
T190	0	53	0	0
T192	0	205	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	23	0	0
T201	0	9	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2061	0	0
T7	30534	20	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	24	0	0
T129	0	36	0	0
T147	0	2	0	0
T172	0	38	0	0
T189	0	55	0	0
T190	0	12	0	0
T192	0	175	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	1	0	0
T201	0	2	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2060	0	0
T7	0	23	0	0
T13	24638	0	0	0
T40	13021	1	0	0
T70	99464	0	0	0
T92	19956	0	0	0
T124	0	28	0	0
T129	0	28	0	0
T147	0	6	0	0
T172	0	48	0	0
T189	0	76	0	0
T190	0	31	0	0
T191	0	6	0	0
T201	0	3	0	0
T207	11571	0	0	0
T208	2437	0	0	0
T209	3794	0	0	0
T210	10188	0	0	0
T211	14559	0	0	0
T212	10239	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2024	0	0
T7	30534	28	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	31	0	0
T129	0	25	0	0
T147	0	8	0	0
T172	0	27	0	0
T189	0	97	0	0
T190	0	22	0	0
T191	0	4	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	5	0	0
T201	0	8	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2024	0	0
T7	30534	31	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	31	0	0
T129	0	25	0	0
T147	0	5	0	0
T172	0	34	0	0
T189	0	64	0	0
T190	0	28	0	0
T192	0	234	0	0
T193	0	9	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T213	0	17	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1958	0	0
T7	0	22	0	0
T58	6061	0	0	0
T65	4712	0	0	0
T124	0	29	0	0
T129	0	24	0	0
T137	27099	0	0	0
T138	8994	0	0	0
T147	0	8	0	0
T172	0	46	0	0
T189	0	59	0	0
T190	0	27	0	0
T191	0	6	0	0
T200	0	5	0	0
T214	6661	9	0	0
T215	8034	0	0	0
T216	5248	0	0	0
T217	98104	0	0	0
T218	21410	0	0	0
T219	18458	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1919	0	0
T7	30534	37	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	32	0	0
T129	0	22	0	0
T147	0	14	0	0
T172	0	36	0	0
T189	0	54	0	0
T190	0	44	0	0
T192	0	241	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	5	0	0
T201	0	7	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2080	0	0
T7	30534	29	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	37	0	0
T129	0	51	0	0
T147	0	13	0	0
T172	0	51	0	0
T189	0	56	0	0
T190	0	33	0	0
T191	0	1	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T201	0	1	0	0
T220	0	4	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1893	0	0
T7	30534	30	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	38	0	0
T129	0	24	0	0
T147	0	4	0	0
T172	0	46	0	0
T189	0	44	0	0
T190	0	27	0	0
T192	0	194	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	2	0	0
T221	0	1	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2006	0	0
T7	30534	28	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	27	0	0
T129	0	15	0	0
T147	0	2	0	0
T172	0	46	0	0
T189	0	61	0	0
T190	0	23	0	0
T191	0	5	0	0
T192	0	208	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T201	0	10	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2029	0	0
T7	30534	17	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	51	0	0
T129	0	20	0	0
T147	0	9	0	0
T172	0	47	0	0
T189	0	46	0	0
T190	0	19	0	0
T191	0	7	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	3	0	0
T201	0	9	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2162	0	0
T7	30534	32	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	33	0	0
T129	0	44	0	0
T147	0	13	0	0
T172	0	37	0	0
T189	0	58	0	0
T190	0	34	0	0
T191	0	5	0	0
T192	0	265	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T201	0	1	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2071	0	0
T7	30534	19	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	28	0	0
T129	0	48	0	0
T147	0	18	0	0
T172	0	49	0	0
T189	0	46	0	0
T190	0	29	0	0
T192	0	209	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	3	0	0
T201	0	5	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1962	0	0
T7	30534	46	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	30	0	0
T129	0	15	0	0
T147	0	10	0	0
T172	0	30	0	0
T189	0	95	0	0
T190	0	24	0	0
T191	0	7	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	2	0	0
T201	0	9	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2030	0	0
T7	30534	15	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	24	0	0
T129	0	29	0	0
T147	0	15	0	0
T172	0	45	0	0
T189	0	71	0	0
T190	0	22	0	0
T191	0	2	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	2	0	0
T201	0	8	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2034	0	0
T7	30534	23	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	41	0	0
T129	0	32	0	0
T147	0	8	0	0
T172	0	23	0	0
T189	0	68	0	0
T190	0	19	0	0
T191	0	1	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	6	0	0
T201	0	1	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1922	0	0
T7	30534	41	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	27	0	0
T129	0	22	0	0
T147	0	13	0	0
T172	0	34	0	0
T189	0	53	0	0
T190	0	24	0	0
T191	0	5	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	8	0	0
T201	0	5	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	2151	0	0
T7	30534	43	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	43	0	0
T129	0	39	0	0
T147	0	14	0	0
T172	0	34	0	0
T189	0	72	0	0
T190	0	20	0	0
T191	0	7	0	0
T192	0	255	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T201	0	5	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1975	0	0
T7	30534	19	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	25	0	0
T129	0	32	0	0
T147	0	6	0	0
T172	0	36	0	0
T189	0	59	0	0
T190	0	17	0	0
T191	0	5	0	0
T192	0	208	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T201	0	5	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25344720	1954	0	0
T7	30534	31	0	0
T20	15263	0	0	0
T42	14209	0	0	0
T66	10720	0	0	0
T124	0	51	0	0
T129	0	30	0	0
T147	0	3	0	0
T172	0	60	0	0
T189	0	59	0	0
T190	0	25	0	0
T191	0	4	0	0
T192	0	214	0	0
T194	1825	0	0	0
T195	11473	0	0	0
T196	17151	0	0	0
T197	6093	0	0	0
T198	7812	0	0	0
T199	9019	0	0	0
T200	0	4	0	0