Module Definition
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Module Instance : tb.dut.u_reg.u_intr_test

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.90 100.00 99.61 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_alert_test_recov_operation_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.90 100.00 99.61 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_alert_test_fatal_fault_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.90 100.00 99.61 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_cfg_regwen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.90 100.00 99.61 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_sw_binding_regwen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.90 100.00 99.61 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_subreg_ext
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T13 T4 T14  30 1/1 assign qre = re; Tests: T91 T70 T73 
Line Coverage for Instance : tb.dut.u_reg.u_intr_test
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T48 T60 T49  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg.u_alert_test_recov_operation_err
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T13 T111 T72  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg.u_alert_test_fatal_fault_err
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T13 T111 T72  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg.u_cfg_regwen
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T91 T70 T73 
Line Coverage for Instance : tb.dut.u_reg.u_sw_binding_regwen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T4 T14 T15  30 1/1 assign qre = re; Tests: T48 T49 T50 
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