Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_packer_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.78 100.00 93.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.78 100.00 93.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 100.00 92.31 100.00 100.00 u_edn_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
TOTAL1717100.00
ALWAYS8277100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11711100.00

81 always_ff @(posedge clk_i or negedge rst_ni) begin 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 depth_q <= '0; Tests: T1 T2 T3  84 1/1 data_q <= '0; Tests: T1 T2 T3  85 1/1 clr_q <= 1'b1; Tests: T1 T2 T3  86 end else begin 87 1/1 depth_q <= depth_d; Tests: T1 T2 T3  88 1/1 data_q <= data_d; Tests: T1 T2 T3  89 1/1 clr_q <= clr_d; Tests: T1 T2 T3  90 end 91 end 92 93 // flop for handling reset case for clr 94 unreachable assign clr_d = clr_i; 95 96 1/1 assign depth_o = depth_q; Tests: T1 T2 T3  97 98 if (InW < OutW) begin : gen_pack_mode 99 logic [MaxW-1:0] wdata_shifted; 100 101 1/1 assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW); Tests: T1 T2 T3  102 1/1 assign clear_status = (rready_i && rvalid_o) || clr_q; Tests: T1 T2 T3  103 1/1 assign clear_data = (ClearOnRead && clear_status) || clr_q; Tests: T1 T2 T3  104 1/1 assign load_data = wvalid_i && wready_o; Tests: T1 T2 T3  105 106 1/1 assign depth_d = clear_status ? '0 : Tests: T1 T2 T3  107 load_data ? (depth_q + DepthOne): 108 depth_q; 109 110 1/1 assign data_d = clear_data ? '0 : Tests: T1 T2 T3  111 load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) : 112 data_q; 113 114 // set outputs 115 1/1 assign wready_o = !(depth_q == FullDepth) && !clr_q; Tests: T1 T2 T3  116 1/1 assign rdata_o = data_q; Tests: T1 T2 T3  117 1/1 assign rvalid_o = (depth_q == FullDepth) && !clr_q; Tests: T1 T2 T3 

Cond Coverage for Module : prim_packer_fifo
TotalCoveredPercent
Conditions302893.33
Logical302893.33
Non-Logical00
Event00

 LINE       102
 EXPRESSION ((rready_i && rvalid_o) || clr_q)
             -----------1----------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       102
 SUB-EXPRESSION (rready_i && rvalid_o)
                 ----1---    ----2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       103
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       104
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       106
 EXPRESSION (clear_status ? '0 : (load_data ? ((depth_q + DepthOne)) : depth_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       106
 SUB-EXPRESSION (load_data ? ((depth_q + DepthOne)) : depth_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION (clear_data ? '0 : (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 SUB-EXPRESSION (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       115
 EXPRESSION (( ! (depth_q == FullDepth) ) && ((!clr_q)))
             --------------1-------------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       115
 SUB-EXPRESSION ( ! (depth_q == FullDepth) )
                    -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       115
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       117
 EXPRESSION ((depth_q == FullDepth) && ((!clr_q)))
             -----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 106 3 3 100.00
TERNARY 110 3 3 100.00
IF 82 2 2 100.00


106 assign depth_d = clear_status ? '0 : -1- ==> 107 load_data ? (depth_q + DepthOne): -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


110 assign data_d = clear_data ? '0 : 111 load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) : 112 data_q; ID LINE -1- 110 clear_data -2- 110 load_data

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


82 if (!rst_ni) begin -1- 83 depth_q <= '0; ==> 84 data_q <= '0; 85 clr_q <= 1'b1; 86 end else begin 87 depth_q <= depth_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_packer_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 21705443 0 0 875
ValidOPairedWithReadyI_A 21705443 0 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21705443 0 0 875

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21705443 0 0 0

Line Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_packer_fifo
Line No.TotalCoveredPercent
TOTAL1717100.00
ALWAYS8277100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11711100.00

81 always_ff @(posedge clk_i or negedge rst_ni) begin 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 depth_q <= '0; Tests: T1 T2 T3  84 1/1 data_q <= '0; Tests: T1 T2 T3  85 1/1 clr_q <= 1'b1; Tests: T1 T2 T3  86 end else begin 87 1/1 depth_q <= depth_d; Tests: T1 T2 T3  88 1/1 data_q <= data_d; Tests: T1 T2 T3  89 1/1 clr_q <= clr_d; Tests: T1 T2 T3  90 end 91 end 92 93 // flop for handling reset case for clr 94 unreachable assign clr_d = clr_i; 95 96 1/1 assign depth_o = depth_q; Tests: T1 T2 T3  97 98 if (InW < OutW) begin : gen_pack_mode 99 logic [MaxW-1:0] wdata_shifted; 100 101 1/1 assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW); Tests: T1 T2 T3  102 1/1 assign clear_status = (rready_i && rvalid_o) || clr_q; Tests: T1 T2 T3  103 1/1 assign clear_data = (ClearOnRead && clear_status) || clr_q; Tests: T1 T2 T3  104 1/1 assign load_data = wvalid_i && wready_o; Tests: T1 T2 T3  105 106 1/1 assign depth_d = clear_status ? '0 : Tests: T1 T2 T3  107 load_data ? (depth_q + DepthOne): 108 depth_q; 109 110 1/1 assign data_d = clear_data ? '0 : Tests: T1 T2 T3  111 load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) : 112 data_q; 113 114 // set outputs 115 1/1 assign wready_o = !(depth_q == FullDepth) && !clr_q; Tests: T1 T2 T3  116 1/1 assign rdata_o = data_q; Tests: T1 T2 T3  117 1/1 assign rvalid_o = (depth_q == FullDepth) && !clr_q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_packer_fifo
TotalCoveredPercent
Conditions302893.33
Logical302893.33
Non-Logical00
Event00

 LINE       102
 EXPRESSION ((rready_i && rvalid_o) || clr_q)
             -----------1----------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       102
 SUB-EXPRESSION (rready_i && rvalid_o)
                 ----1---    ----2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       103
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       104
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       106
 EXPRESSION (clear_status ? '0 : (load_data ? ((depth_q + DepthOne)) : depth_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       106
 SUB-EXPRESSION (load_data ? ((depth_q + DepthOne)) : depth_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION (clear_data ? '0 : (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 SUB-EXPRESSION (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       115
 EXPRESSION (( ! (depth_q == FullDepth) ) && ((!clr_q)))
             --------------1-------------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       115
 SUB-EXPRESSION ( ! (depth_q == FullDepth) )
                    -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       115
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       117
 EXPRESSION ((depth_q == FullDepth) && ((!clr_q)))
             -----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_packer_fifo
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 106 3 3 100.00
TERNARY 110 3 3 100.00
IF 82 2 2 100.00


106 assign depth_d = clear_status ? '0 : -1- ==> 107 load_data ? (depth_q + DepthOne): -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


110 assign data_d = clear_data ? '0 : 111 load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) : 112 data_q; ID LINE -1- 110 clear_data -2- 110 load_data

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


82 if (!rst_ni) begin -1- 83 depth_q <= '0; ==> 84 data_q <= '0; 85 clr_q <= 1'b1; 86 end else begin 87 depth_q <= depth_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_packer_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 0 0 0
Cover properties 0 0 0
Cover sequences 0 0 0
Total 0 0 0




Assertion Details

NameAttemptsReal SuccessesFailuresIncompleteExclusionExclude Annotation
DataOStableWhenPending_A Excluded [UNR] rready_i is tied to 1 from prim_edn_req module.
ValidOPairedWithReadyI_A Excluded [UNR] rready_i is tied to 1 from prim_edn_req module.

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%