Module Definition
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Module : prim_lfsr
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lfsr 100.00 100.00



Module Instance : tb.dut.u_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_lfsr
TotalCoveredPercent
Totals 6 6 100.00
Total Bits 264 264 100.00
Total Bits 0->1 132 132 100.00
Total Bits 1->0 132 132 100.00

Ports 6 6 100.00
Port Bits 264 264 100.00
Port Bits 0->1 132 132 100.00
Port Bits 1->0 132 132 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T15,T37 Yes T1,T2,T3 INPUT
seed_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_i[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[7:0] Unreachable Unreachable Unreachable INPUT
state_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

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