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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.04 98.07 98.77 100.00 99.02 98.41 91.14


Total test records in report: 1082
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1005 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.577169998 Feb 08 02:48:02 PM UTC 25 Feb 08 02:48:05 PM UTC 25 106592849 ps
T1006 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2728071400 Feb 08 02:47:49 PM UTC 25 Feb 08 02:48:05 PM UTC 25 344996058 ps
T1007 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3283414589 Feb 08 02:48:02 PM UTC 25 Feb 08 02:48:06 PM UTC 25 712279469 ps
T1008 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.3939819529 Feb 08 02:48:05 PM UTC 25 Feb 08 02:48:07 PM UTC 25 19032777 ps
T1009 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.606578100 Feb 08 02:48:06 PM UTC 25 Feb 08 02:48:09 PM UTC 25 52726712 ps
T1010 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3241621919 Feb 08 02:48:03 PM UTC 25 Feb 08 02:48:09 PM UTC 25 184259436 ps
T1011 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1879747403 Feb 08 02:48:05 PM UTC 25 Feb 08 02:48:10 PM UTC 25 106534860 ps
T1012 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1819732514 Feb 08 02:48:03 PM UTC 25 Feb 08 02:48:10 PM UTC 25 94867562 ps
T1013 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3795680330 Feb 08 02:47:57 PM UTC 25 Feb 08 02:48:10 PM UTC 25 1140876712 ps
T1014 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3181387491 Feb 08 02:48:07 PM UTC 25 Feb 08 02:48:11 PM UTC 25 46326732 ps
T1015 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1812413338 Feb 08 02:48:06 PM UTC 25 Feb 08 02:48:12 PM UTC 25 108814744 ps
T1016 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.2268748854 Feb 08 02:48:10 PM UTC 25 Feb 08 02:48:12 PM UTC 25 32409444 ps
T1017 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.748852396 Feb 08 02:48:11 PM UTC 25 Feb 08 02:48:14 PM UTC 25 23553136 ps
T1018 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.1870802897 Feb 08 02:48:09 PM UTC 25 Feb 08 02:48:14 PM UTC 25 140576878 ps
T1019 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.681568744 Feb 08 02:48:12 PM UTC 25 Feb 08 02:48:15 PM UTC 25 26089205 ps
T1020 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3189124510 Feb 08 02:48:07 PM UTC 25 Feb 08 02:48:15 PM UTC 25 257518358 ps
T1021 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2634968714 Feb 08 02:48:12 PM UTC 25 Feb 08 02:48:16 PM UTC 25 153028285 ps
T1022 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.628450942 Feb 08 02:48:11 PM UTC 25 Feb 08 02:48:16 PM UTC 25 105810202 ps
T1023 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.7085374 Feb 08 02:48:13 PM UTC 25 Feb 08 02:48:17 PM UTC 25 441183905 ps
T1024 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3394367845 Feb 08 02:48:16 PM UTC 25 Feb 08 02:48:18 PM UTC 25 27164488 ps
T1025 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.990075632 Feb 08 02:48:16 PM UTC 25 Feb 08 02:48:18 PM UTC 25 11401931 ps
T159 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.3896032920 Feb 08 02:48:05 PM UTC 25 Feb 08 02:48:19 PM UTC 25 561152662 ps
T163 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.3409755322 Feb 08 02:48:09 PM UTC 25 Feb 08 02:48:19 PM UTC 25 279265502 ps
T1026 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2342438401 Feb 08 02:48:17 PM UTC 25 Feb 08 02:48:20 PM UTC 25 269311203 ps
T1027 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.708188269 Feb 08 02:48:08 PM UTC 25 Feb 08 02:48:20 PM UTC 25 4650953228 ps
T1028 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2410567142 Feb 08 02:48:17 PM UTC 25 Feb 08 02:48:21 PM UTC 25 56940146 ps
T1029 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3134434966 Feb 08 02:48:17 PM UTC 25 Feb 08 02:48:21 PM UTC 25 42500051 ps
T1030 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2089719376 Feb 08 02:48:13 PM UTC 25 Feb 08 02:48:21 PM UTC 25 868328465 ps
T1031 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.777727667 Feb 08 02:48:20 PM UTC 25 Feb 08 02:48:22 PM UTC 25 27436351 ps
T1032 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.2208783035 Feb 08 02:48:21 PM UTC 25 Feb 08 02:48:24 PM UTC 25 26114055 ps
T1033 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2890949565 Feb 08 02:48:21 PM UTC 25 Feb 08 02:48:24 PM UTC 25 37192916 ps
T1034 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1194869393 Feb 08 02:48:21 PM UTC 25 Feb 08 02:48:25 PM UTC 25 265014054 ps
T1035 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.53272824 Feb 08 02:48:21 PM UTC 25 Feb 08 02:48:25 PM UTC 25 753006533 ps
T1036 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.3472456405 Feb 08 02:48:20 PM UTC 25 Feb 08 02:48:26 PM UTC 25 402210153 ps
T1037 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3837408196 Feb 08 02:48:23 PM UTC 25 Feb 08 02:48:26 PM UTC 25 68085933 ps
T1038 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.3067271356 Feb 08 02:48:18 PM UTC 25 Feb 08 02:48:26 PM UTC 25 621238625 ps
T1039 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.3279621598 Feb 08 02:48:25 PM UTC 25 Feb 08 02:48:27 PM UTC 25 18571590 ps
T1040 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3141353865 Feb 08 02:48:18 PM UTC 25 Feb 08 02:48:27 PM UTC 25 219849336 ps
T1041 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.1967354402 Feb 08 02:48:25 PM UTC 25 Feb 08 02:48:28 PM UTC 25 16885324 ps
T151 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.47810724 Feb 08 02:48:15 PM UTC 25 Feb 08 02:48:28 PM UTC 25 284870132 ps
T153 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.2502520956 Feb 08 02:48:23 PM UTC 25 Feb 08 02:48:29 PM UTC 25 713161241 ps
T1042 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.672392378 Feb 08 02:48:26 PM UTC 25 Feb 08 02:48:30 PM UTC 25 46120719 ps
T1043 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3605209815 Feb 08 02:48:26 PM UTC 25 Feb 08 02:48:30 PM UTC 25 838712605 ps
T1044 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.1323038908 Feb 08 02:48:29 PM UTC 25 Feb 08 02:48:31 PM UTC 25 17090642 ps
T1045 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.697141733 Feb 08 02:48:23 PM UTC 25 Feb 08 02:48:32 PM UTC 25 346195439 ps
T1046 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.1422182092 Feb 08 02:48:28 PM UTC 25 Feb 08 02:48:32 PM UTC 25 39921761 ps
T1047 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.1284263933 Feb 08 02:48:29 PM UTC 25 Feb 08 02:48:32 PM UTC 25 99770803 ps
T1048 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.1932865006 Feb 08 02:48:31 PM UTC 25 Feb 08 02:48:33 PM UTC 25 14559667 ps
T1049 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.2506709058 Feb 08 02:48:31 PM UTC 25 Feb 08 02:48:33 PM UTC 25 9290907 ps
T1050 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3505831775 Feb 08 02:48:29 PM UTC 25 Feb 08 02:48:33 PM UTC 25 202846639 ps
T1051 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.770535508 Feb 08 02:48:28 PM UTC 25 Feb 08 02:48:34 PM UTC 25 1810786849 ps
T1052 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2406832779 Feb 08 02:48:31 PM UTC 25 Feb 08 02:48:34 PM UTC 25 22470973 ps
T1053 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.3243043814 Feb 08 02:48:29 PM UTC 25 Feb 08 02:48:34 PM UTC 25 79686610 ps
T1054 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.1237390610 Feb 08 02:48:32 PM UTC 25 Feb 08 02:48:34 PM UTC 25 27478930 ps
T1055 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.1641429664 Feb 08 02:48:34 PM UTC 25 Feb 08 02:48:36 PM UTC 25 28809145 ps
T1056 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1844638407 Feb 08 02:48:34 PM UTC 25 Feb 08 02:48:36 PM UTC 25 13029346 ps
T1057 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.1652952234 Feb 08 02:48:34 PM UTC 25 Feb 08 02:48:36 PM UTC 25 22252542 ps
T1058 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.564609344 Feb 08 02:48:34 PM UTC 25 Feb 08 02:48:36 PM UTC 25 17530386 ps
T1059 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.2508055854 Feb 08 02:48:34 PM UTC 25 Feb 08 02:48:36 PM UTC 25 43078719 ps
T1060 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.556344271 Feb 08 02:48:28 PM UTC 25 Feb 08 02:48:37 PM UTC 25 620382228 ps
T1061 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.1704905694 Feb 08 02:48:35 PM UTC 25 Feb 08 02:48:38 PM UTC 25 11567227 ps
T1062 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.108360910 Feb 08 02:48:36 PM UTC 25 Feb 08 02:48:38 PM UTC 25 36020822 ps
T1063 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3501301519 Feb 08 02:48:35 PM UTC 25 Feb 08 02:48:38 PM UTC 25 28146686 ps
T1064 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.1292100654 Feb 08 02:48:35 PM UTC 25 Feb 08 02:48:38 PM UTC 25 46770106 ps
T1065 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2621342852 Feb 08 02:48:35 PM UTC 25 Feb 08 02:48:38 PM UTC 25 22547821 ps
T1066 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.1710479296 Feb 08 02:48:37 PM UTC 25 Feb 08 02:48:39 PM UTC 25 26017095 ps
T1067 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1651023384 Feb 08 02:48:37 PM UTC 25 Feb 08 02:48:39 PM UTC 25 41876434 ps
T1068 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.2233256871 Feb 08 02:48:37 PM UTC 25 Feb 08 02:48:40 PM UTC 25 33495588 ps
T1069 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.1794529101 Feb 08 02:48:37 PM UTC 25 Feb 08 02:48:40 PM UTC 25 38489969 ps
T1070 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.836582290 Feb 08 02:48:37 PM UTC 25 Feb 08 02:48:40 PM UTC 25 32963358 ps
T1071 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.3027294754 Feb 08 02:48:39 PM UTC 25 Feb 08 02:48:42 PM UTC 25 52083554 ps
T1072 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.3936725277 Feb 08 02:48:39 PM UTC 25 Feb 08 02:48:42 PM UTC 25 136628744 ps
T1073 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.1276845759 Feb 08 02:48:40 PM UTC 25 Feb 08 02:48:42 PM UTC 25 115375199 ps
T1074 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.3691094729 Feb 08 02:48:39 PM UTC 25 Feb 08 02:48:42 PM UTC 25 17392069 ps
T1075 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.4089088190 Feb 08 02:48:40 PM UTC 25 Feb 08 02:48:42 PM UTC 25 38236981 ps
T1076 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.1126776369 Feb 08 02:48:39 PM UTC 25 Feb 08 02:48:42 PM UTC 25 221095742 ps
T1077 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.2708231305 Feb 08 02:48:42 PM UTC 25 Feb 08 02:48:45 PM UTC 25 12892605 ps
T1078 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.898154165 Feb 08 02:48:42 PM UTC 25 Feb 08 02:48:45 PM UTC 25 13869002 ps
T1079 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.2756540095 Feb 08 02:48:42 PM UTC 25 Feb 08 02:48:45 PM UTC 25 15083334 ps
T1080 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.3907232735 Feb 08 02:48:42 PM UTC 25 Feb 08 02:48:45 PM UTC 25 12746592 ps
T1081 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.4091128527 Feb 08 02:48:42 PM UTC 25 Feb 08 02:48:45 PM UTC 25 28381787 ps
T1082 /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.4283489845 Feb 08 02:48:44 PM UTC 25 Feb 08 02:48:46 PM UTC 25 17945915 ps

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_random.31935074
Short name T5
Test name
Test status
Simulation time 1446044530 ps
CPU time 5.37 seconds
Started Feb 08 12:46:36 PM UTC 25
Finished Feb 08 12:46:43 PM UTC 25
Peak memory 228488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31935074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_rand
om_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.keymgr_random.31935074
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.3948716864
Short name T26
Test name
Test status
Simulation time 548652247 ps
CPU time 24.73 seconds
Started Feb 08 12:47:12 PM UTC 25
Finished Feb 08 12:47:39 PM UTC 25
Peak memory 232348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3948716864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_
reset.3948716864
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.769592842
Short name T53
Test name
Test status
Simulation time 1281500608 ps
CPU time 59.81 seconds
Started Feb 08 12:48:16 PM UTC 25
Finished Feb 08 12:49:18 PM UTC 25
Peak memory 232928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769592842 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.769592842
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.1479763617
Short name T11
Test name
Test status
Simulation time 2294011307 ps
CPU time 16.16 seconds
Started Feb 08 12:47:15 PM UTC 25
Finished Feb 08 12:47:33 PM UTC 25
Peak memory 260492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479763617 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1479763617
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.2977677311
Short name T54
Test name
Test status
Simulation time 3180150513 ps
CPU time 40.25 seconds
Started Feb 08 12:49:19 PM UTC 25
Finished Feb 08 12:50:01 PM UTC 25
Peak memory 232688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977677311 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2977677311
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all_with_rand_reset.1046377437
Short name T7
Test name
Test status
Simulation time 3817007659 ps
CPU time 16 seconds
Started Feb 08 12:49:33 PM UTC 25
Finished Feb 08 12:49:51 PM UTC 25
Peak memory 232868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1046377437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_
reset.1046377437
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.703417307
Short name T70
Test name
Test status
Simulation time 994667670 ps
CPU time 30.29 seconds
Started Feb 08 12:47:56 PM UTC 25
Finished Feb 08 12:48:28 PM UTC 25
Peak memory 228488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703417307 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.703417307
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.455873622
Short name T10
Test name
Test status
Simulation time 120377849 ps
CPU time 2.67 seconds
Started Feb 08 12:49:30 PM UTC 25
Finished Feb 08 12:49:34 PM UTC 25
Peak memory 233092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455873622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cus
tom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.keymgr_custom_cm.455873622
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.3909355660
Short name T46
Test name
Test status
Simulation time 932728245 ps
CPU time 53.18 seconds
Started Feb 08 12:46:42 PM UTC 25
Finished Feb 08 12:47:37 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909355660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3909355660
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1302543367
Short name T116
Test name
Test status
Simulation time 371903863 ps
CPU time 11.59 seconds
Started Feb 08 02:46:19 PM UTC 25
Finished Feb 08 02:46:34 PM UTC 25
Peak memory 226284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302543367 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.1302543367
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.1008279125
Short name T48
Test name
Test status
Simulation time 116729820 ps
CPU time 4.57 seconds
Started Feb 08 12:47:51 PM UTC 25
Finished Feb 08 12:47:56 PM UTC 25
Peak memory 224600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008279125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1008279125
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.636094325
Short name T420
Test name
Test status
Simulation time 299528621 ps
CPU time 13.17 seconds
Started Feb 08 12:49:09 PM UTC 25
Finished Feb 08 12:49:24 PM UTC 25
Peak memory 224460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636094325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.636094325
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all_with_rand_reset.2718906257
Short name T114
Test name
Test status
Simulation time 230282544 ps
CPU time 17.46 seconds
Started Feb 08 12:49:48 PM UTC 25
Finished Feb 08 12:50:07 PM UTC 25
Peak memory 232948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2718906257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_
reset.2718906257
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.2319382158
Short name T22
Test name
Test status
Simulation time 50766256 ps
CPU time 3.95 seconds
Started Feb 08 12:50:52 PM UTC 25
Finished Feb 08 12:50:57 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319382158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2319382158
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.461381388
Short name T444
Test name
Test status
Simulation time 1535538054 ps
CPU time 37.58 seconds
Started Feb 08 12:51:44 PM UTC 25
Finished Feb 08 12:52:23 PM UTC 25
Peak memory 226740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461381388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.461381388
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.3902374485
Short name T6
Test name
Test status
Simulation time 2369380190 ps
CPU time 45.17 seconds
Started Feb 08 12:48:32 PM UTC 25
Finished Feb 08 12:49:19 PM UTC 25
Peak memory 226576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902374485 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3902374485
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.3407653486
Short name T387
Test name
Test status
Simulation time 1179655145 ps
CPU time 15.29 seconds
Started Feb 08 12:53:18 PM UTC 25
Finished Feb 08 12:53:35 PM UTC 25
Peak memory 226440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407653486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3407653486
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.3989334564
Short name T16
Test name
Test status
Simulation time 86116326 ps
CPU time 5.09 seconds
Started Feb 08 12:46:54 PM UTC 25
Finished Feb 08 12:47:00 PM UTC 25
Peak memory 218508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989334564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3989334564
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.624051246
Short name T135
Test name
Test status
Simulation time 120376411 ps
CPU time 8.47 seconds
Started Feb 08 12:48:07 PM UTC 25
Finished Feb 08 12:48:17 PM UTC 25
Peak memory 224352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624051246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.624051246
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.1060584642
Short name T312
Test name
Test status
Simulation time 427701749 ps
CPU time 21.41 seconds
Started Feb 08 12:50:53 PM UTC 25
Finished Feb 08 12:51:16 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060584642 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1060584642
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.1276603860
Short name T44
Test name
Test status
Simulation time 205175219 ps
CPU time 4.39 seconds
Started Feb 08 12:48:32 PM UTC 25
Finished Feb 08 12:48:38 PM UTC 25
Peak memory 218308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276603860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1276603860
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.156586072
Short name T441
Test name
Test status
Simulation time 1624473081 ps
CPU time 39.37 seconds
Started Feb 08 12:52:24 PM UTC 25
Finished Feb 08 12:53:06 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156586072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.156586072
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.1779942097
Short name T41
Test name
Test status
Simulation time 164420675 ps
CPU time 3.41 seconds
Started Feb 08 12:48:12 PM UTC 25
Finished Feb 08 12:48:17 PM UTC 25
Peak memory 226720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779942097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 2.keymgr_custom_cm.1779942097
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.1161834992
Short name T24
Test name
Test status
Simulation time 201349136 ps
CPU time 3.27 seconds
Started Feb 08 12:51:27 PM UTC 25
Finished Feb 08 12:51:32 PM UTC 25
Peak memory 216476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161834992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 17.keymgr_custom_cm.1161834992
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.1946238244
Short name T178
Test name
Test status
Simulation time 1075597119 ps
CPU time 11.69 seconds
Started Feb 08 12:51:58 PM UTC 25
Finished Feb 08 12:52:12 PM UTC 25
Peak memory 228840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946238244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 20.keymgr_custom_cm.1946238244
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.756888646
Short name T297
Test name
Test status
Simulation time 5892003046 ps
CPU time 82.1 seconds
Started Feb 08 12:48:44 PM UTC 25
Finished Feb 08 12:50:08 PM UTC 25
Peak memory 230960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756888646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.756888646
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.4060552528
Short name T8
Test name
Test status
Simulation time 2127716820 ps
CPU time 55.68 seconds
Started Feb 08 12:49:32 PM UTC 25
Finished Feb 08 12:50:30 PM UTC 25
Peak memory 228564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060552528 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.4060552528
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.1033167574
Short name T33
Test name
Test status
Simulation time 540524774 ps
CPU time 5.5 seconds
Started Feb 08 12:51:16 PM UTC 25
Finished Feb 08 12:51:23 PM UTC 25
Peak memory 226552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033167574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 16.keymgr_custom_cm.1033167574
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.3973364714
Short name T59
Test name
Test status
Simulation time 489172109 ps
CPU time 27.17 seconds
Started Feb 08 12:48:56 PM UTC 25
Finished Feb 08 12:49:25 PM UTC 25
Peak memory 232812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973364714 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3973364714
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.1075524359
Short name T294
Test name
Test status
Simulation time 10500411360 ps
CPU time 111.69 seconds
Started Feb 08 12:51:34 PM UTC 25
Finished Feb 08 12:53:28 PM UTC 25
Peak memory 230696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075524359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1075524359
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.693699254
Short name T951
Test name
Test status
Simulation time 356229172 ps
CPU time 7.87 seconds
Started Feb 08 02:47:14 PM UTC 25
Finished Feb 08 02:47:24 PM UTC 25
Peak memory 226556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693699254 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.693699254
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.726338233
Short name T150
Test name
Test status
Simulation time 775463931 ps
CPU time 9.55 seconds
Started Feb 08 02:47:15 PM UTC 25
Finished Feb 08 02:47:26 PM UTC 25
Peak memory 216080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726338233 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.726338233
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.441269076
Short name T426
Test name
Test status
Simulation time 4547121065 ps
CPU time 16.08 seconds
Started Feb 08 12:54:53 PM UTC 25
Finished Feb 08 12:55:11 PM UTC 25
Peak memory 226544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441269076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.441269076
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.3154893920
Short name T104
Test name
Test status
Simulation time 35842661 ps
CPU time 1.16 seconds
Started Feb 08 12:47:31 PM UTC 25
Finished Feb 08 12:47:33 PM UTC 25
Peak memory 214760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154893920 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3154893920
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.751249668
Short name T72
Test name
Test status
Simulation time 3235454975 ps
CPU time 30.14 seconds
Started Feb 08 12:50:32 PM UTC 25
Finished Feb 08 12:51:04 PM UTC 25
Peak memory 232576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751249668 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.751249668
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.1965983632
Short name T92
Test name
Test status
Simulation time 399163377 ps
CPU time 10.25 seconds
Started Feb 08 12:48:10 PM UTC 25
Finished Feb 08 12:48:22 PM UTC 25
Peak memory 226536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965983632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1965983632
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all_with_rand_reset.2602005173
Short name T128
Test name
Test status
Simulation time 111736062 ps
CPU time 8.2 seconds
Started Feb 08 12:50:53 PM UTC 25
Finished Feb 08 12:51:03 PM UTC 25
Peak memory 232716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2602005173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand
_reset.2602005173
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.33391870
Short name T27
Test name
Test status
Simulation time 2992413649 ps
CPU time 31.41 seconds
Started Feb 08 12:47:11 PM UTC 25
Finished Feb 08 12:47:44 PM UTC 25
Peak memory 230616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33391870 -assert nopostproc +UVM_TESTNAME=keymgr_base_t
est +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.33391870
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.982175771
Short name T454
Test name
Test status
Simulation time 213134804 ps
CPU time 4.42 seconds
Started Feb 08 12:55:27 PM UTC 25
Finished Feb 08 12:55:33 PM UTC 25
Peak memory 232536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982175771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.982175771
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.2359033439
Short name T272
Test name
Test status
Simulation time 151052241 ps
CPU time 3.77 seconds
Started Feb 08 12:50:10 PM UTC 25
Finished Feb 08 12:50:15 PM UTC 25
Peak memory 226492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359033439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2359033439
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.47810724
Short name T151
Test name
Test status
Simulation time 284870132 ps
CPU time 11.8 seconds
Started Feb 08 02:48:15 PM UTC 25
Finished Feb 08 02:48:28 PM UTC 25
Peak memory 225884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47810724 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.47810724
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.2752285601
Short name T353
Test name
Test status
Simulation time 58445651 ps
CPU time 3.95 seconds
Started Feb 08 12:52:56 PM UTC 25
Finished Feb 08 12:53:02 PM UTC 25
Peak memory 224436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752285601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2752285601
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.525982634
Short name T234
Test name
Test status
Simulation time 770437127 ps
CPU time 5.86 seconds
Started Feb 08 12:48:02 PM UTC 25
Finished Feb 08 12:48:09 PM UTC 25
Peak memory 218504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525982634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.525982634
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.813176940
Short name T442
Test name
Test status
Simulation time 266111884 ps
CPU time 8.89 seconds
Started Feb 08 12:51:57 PM UTC 25
Finished Feb 08 12:52:07 PM UTC 25
Peak memory 224576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813176940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.813176940
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.77150553
Short name T205
Test name
Test status
Simulation time 8700096076 ps
CPU time 202.47 seconds
Started Feb 08 12:52:01 PM UTC 25
Finished Feb 08 12:55:27 PM UTC 25
Peak memory 232772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77150553 -assert nopostproc +UVM_TESTNAME=keymgr_base_t
est +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.77150553
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.1369020866
Short name T99
Test name
Test status
Simulation time 194342693 ps
CPU time 4.2 seconds
Started Feb 08 12:50:58 PM UTC 25
Finished Feb 08 12:51:04 PM UTC 25
Peak memory 231552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369020866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1369020866
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.2132053342
Short name T74
Test name
Test status
Simulation time 129863029 ps
CPU time 3.78 seconds
Started Feb 08 12:50:00 PM UTC 25
Finished Feb 08 12:50:05 PM UTC 25
Peak memory 232852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132053342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 8.keymgr_custom_cm.2132053342
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.1136535996
Short name T187
Test name
Test status
Simulation time 254078565 ps
CPU time 3.49 seconds
Started Feb 08 12:54:41 PM UTC 25
Finished Feb 08 12:54:46 PM UTC 25
Peak memory 228940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136535996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 40.keymgr_custom_cm.1136535996
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.4289607379
Short name T184
Test name
Test status
Simulation time 264249919 ps
CPU time 3.46 seconds
Started Feb 08 12:55:08 PM UTC 25
Finished Feb 08 12:55:13 PM UTC 25
Peak memory 232892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289607379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 44.keymgr_custom_cm.4289607379
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.1728850585
Short name T181
Test name
Test status
Simulation time 350864907 ps
CPU time 3.87 seconds
Started Feb 08 12:53:45 PM UTC 25
Finished Feb 08 12:53:50 PM UTC 25
Peak memory 229036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728850585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 32.keymgr_custom_cm.1728850585
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.37955547
Short name T348
Test name
Test status
Simulation time 413310822 ps
CPU time 21.59 seconds
Started Feb 08 12:52:14 PM UTC 25
Finished Feb 08 12:52:38 PM UTC 25
Peak memory 226440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37955547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.37955547
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.198103531
Short name T82
Test name
Test status
Simulation time 573447579 ps
CPU time 36.23 seconds
Started Feb 08 12:52:57 PM UTC 25
Finished Feb 08 12:53:36 PM UTC 25
Peak memory 226168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198103531 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.198103531
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.1882394914
Short name T77
Test name
Test status
Simulation time 1161371745 ps
CPU time 51.74 seconds
Started Feb 08 12:49:48 PM UTC 25
Finished Feb 08 12:50:41 PM UTC 25
Peak memory 232552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882394914 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1882394914
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.238436051
Short name T160
Test name
Test status
Simulation time 269405333 ps
CPU time 8.67 seconds
Started Feb 08 02:47:22 PM UTC 25
Finished Feb 08 02:47:32 PM UTC 25
Peak memory 227992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238436051 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.238436051
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.2755877232
Short name T66
Test name
Test status
Simulation time 446727702 ps
CPU time 6.69 seconds
Started Feb 08 12:49:44 PM UTC 25
Finished Feb 08 12:49:52 PM UTC 25
Peak memory 226308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755877232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2755877232
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.3896032920
Short name T159
Test name
Test status
Simulation time 561152662 ps
CPU time 13.17 seconds
Started Feb 08 02:48:05 PM UTC 25
Finished Feb 08 02:48:19 PM UTC 25
Peak memory 225948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896032920 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.3896032920
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.829968257
Short name T532
Test name
Test status
Simulation time 91187839 ps
CPU time 1.77 seconds
Started Feb 08 12:51:49 PM UTC 25
Finished Feb 08 12:51:52 PM UTC 25
Peak memory 217872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829968257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_syn
c_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.829968257
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.1341870016
Short name T371
Test name
Test status
Simulation time 89267536 ps
CPU time 5.34 seconds
Started Feb 08 12:53:36 PM UTC 25
Finished Feb 08 12:53:43 PM UTC 25
Peak memory 224656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341870016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1341870016
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.2961936394
Short name T398
Test name
Test status
Simulation time 151435078 ps
CPU time 10.46 seconds
Started Feb 08 12:54:25 PM UTC 25
Finished Feb 08 12:54:37 PM UTC 25
Peak memory 226336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961936394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2961936394
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.3269980603
Short name T179
Test name
Test status
Simulation time 531507590 ps
CPU time 7.44 seconds
Started Feb 08 12:52:46 PM UTC 25
Finished Feb 08 12:52:55 PM UTC 25
Peak memory 232832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269980603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 25.keymgr_custom_cm.3269980603
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.3409755322
Short name T163
Test name
Test status
Simulation time 279265502 ps
CPU time 8.51 seconds
Started Feb 08 02:48:09 PM UTC 25
Finished Feb 08 02:48:19 PM UTC 25
Peak memory 225948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409755322 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.3409755322
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.3351372133
Short name T61
Test name
Test status
Simulation time 64520310 ps
CPU time 3.06 seconds
Started Feb 08 12:50:49 PM UTC 25
Finished Feb 08 12:50:53 PM UTC 25
Peak memory 226448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351372133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 13.keymgr_lc_disable.3351372133
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.484394249
Short name T176
Test name
Test status
Simulation time 85981681 ps
CPU time 2.46 seconds
Started Feb 08 12:50:53 PM UTC 25
Finished Feb 08 12:50:57 PM UTC 25
Peak memory 226740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484394249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cus
tom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.keymgr_custom_cm.484394249
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.648574860
Short name T235
Test name
Test status
Simulation time 3021333365 ps
CPU time 29.07 seconds
Started Feb 08 12:47:38 PM UTC 25
Finished Feb 08 12:48:09 PM UTC 25
Peak memory 216328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648574860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.648574860
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.585638342
Short name T401
Test name
Test status
Simulation time 50993336 ps
CPU time 2.57 seconds
Started Feb 08 12:51:33 PM UTC 25
Finished Feb 08 12:51:37 PM UTC 25
Peak memory 218592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585638342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.585638342
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.4026728187
Short name T257
Test name
Test status
Simulation time 13314079267 ps
CPU time 101.79 seconds
Started Feb 08 12:52:39 PM UTC 25
Finished Feb 08 12:54:23 PM UTC 25
Peak memory 228552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026728187 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4026728187
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.750932900
Short name T83
Test name
Test status
Simulation time 4965116005 ps
CPU time 37.74 seconds
Started Feb 08 12:53:08 PM UTC 25
Finished Feb 08 12:53:47 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750932900 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.750932900
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.4072343180
Short name T320
Test name
Test status
Simulation time 146176837 ps
CPU time 6.57 seconds
Started Feb 08 12:53:14 PM UTC 25
Finished Feb 08 12:53:22 PM UTC 25
Peak memory 224428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072343180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4072343180
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.3373143417
Short name T189
Test name
Test status
Simulation time 801270352 ps
CPU time 19.21 seconds
Started Feb 08 12:53:25 PM UTC 25
Finished Feb 08 12:53:46 PM UTC 25
Peak memory 232756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3373143417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand
_reset.3373143417
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.1936545346
Short name T263
Test name
Test status
Simulation time 2245456077 ps
CPU time 55.22 seconds
Started Feb 08 12:55:36 PM UTC 25
Finished Feb 08 12:56:34 PM UTC 25
Peak memory 224528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936545346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1936545346
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.2833425970
Short name T167
Test name
Test status
Simulation time 159966968 ps
CPU time 8.6 seconds
Started Feb 08 02:46:47 PM UTC 25
Finished Feb 08 02:46:57 PM UTC 25
Peak memory 226196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833425970 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.2833425970
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.396144826
Short name T174
Test name
Test status
Simulation time 82293491 ps
CPU time 2.62 seconds
Started Feb 08 12:54:55 PM UTC 25
Finished Feb 08 12:54:59 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396144826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_syn
c_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.396144826
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.4145121987
Short name T180
Test name
Test status
Simulation time 284657720 ps
CPU time 4.41 seconds
Started Feb 08 12:53:32 PM UTC 25
Finished Feb 08 12:53:38 PM UTC 25
Peak memory 232832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145121987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 30.keymgr_custom_cm.4145121987
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.1273462772
Short name T182
Test name
Test status
Simulation time 48531948 ps
CPU time 3.36 seconds
Started Feb 08 12:54:04 PM UTC 25
Finished Feb 08 12:54:09 PM UTC 25
Peak memory 226720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273462772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 35.keymgr_custom_cm.1273462772
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.1345914041
Short name T490
Test name
Test status
Simulation time 1451373711 ps
CPU time 6.15 seconds
Started Feb 08 12:50:47 PM UTC 25
Finished Feb 08 12:50:54 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345914041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1345914041
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.3117925244
Short name T413
Test name
Test status
Simulation time 1036311935 ps
CPU time 11.55 seconds
Started Feb 08 12:50:58 PM UTC 25
Finished Feb 08 12:51:12 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117925244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3117925244
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.3262210785
Short name T291
Test name
Test status
Simulation time 33505009 ps
CPU time 3.09 seconds
Started Feb 08 12:51:08 PM UTC 25
Finished Feb 08 12:51:12 PM UTC 25
Peak memory 232568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262210785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3262210785
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.2729737322
Short name T395
Test name
Test status
Simulation time 58507200 ps
CPU time 3.82 seconds
Started Feb 08 12:52:30 PM UTC 25
Finished Feb 08 12:52:35 PM UTC 25
Peak memory 226456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729737322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2729737322
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.3084395481
Short name T376
Test name
Test status
Simulation time 222874928 ps
CPU time 3.59 seconds
Started Feb 08 12:53:37 PM UTC 25
Finished Feb 08 12:53:42 PM UTC 25
Peak memory 224100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084395481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3084395481
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.3896727279
Short name T458
Test name
Test status
Simulation time 2370084089 ps
CPU time 103.79 seconds
Started Feb 08 12:54:18 PM UTC 25
Finished Feb 08 12:56:04 PM UTC 25
Peak memory 226452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896727279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3896727279
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.3007323950
Short name T249
Test name
Test status
Simulation time 6727120187 ps
CPU time 79.9 seconds
Started Feb 08 12:54:33 PM UTC 25
Finished Feb 08 12:55:55 PM UTC 25
Peak memory 226768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007323950 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3007323950
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.816263303
Short name T154
Test name
Test status
Simulation time 608299190 ps
CPU time 6.32 seconds
Started Feb 08 02:47:44 PM UTC 25
Finished Feb 08 02:47:52 PM UTC 25
Peak memory 226008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816263303 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.816263303
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.3466025852
Short name T165
Test name
Test status
Simulation time 242145471 ps
CPU time 4.06 seconds
Started Feb 08 02:47:59 PM UTC 25
Finished Feb 08 02:48:04 PM UTC 25
Peak memory 226324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466025852 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.3466025852
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.2502520956
Short name T153
Test name
Test status
Simulation time 713161241 ps
CPU time 4.92 seconds
Started Feb 08 02:48:23 PM UTC 25
Finished Feb 08 02:48:29 PM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502520956 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.2502520956
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.2687915399
Short name T12
Test name
Test status
Simulation time 590404169 ps
CPU time 6.51 seconds
Started Feb 08 12:47:58 PM UTC 25
Finished Feb 08 12:48:06 PM UTC 25
Peak memory 254536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687915399 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2687915399
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.1798723493
Short name T34
Test name
Test status
Simulation time 287476318 ps
CPU time 4.73 seconds
Started Feb 08 12:51:09 PM UTC 25
Finished Feb 08 12:51:15 PM UTC 25
Peak memory 224668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798723493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 15.keymgr_custom_cm.1798723493
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.198834895
Short name T186
Test name
Test status
Simulation time 107689497 ps
CPU time 3.92 seconds
Started Feb 08 12:52:19 PM UTC 25
Finished Feb 08 12:52:24 PM UTC 25
Peak memory 226688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198834895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cus
tom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.keymgr_custom_cm.198834895
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.2532323279
Short name T185
Test name
Test status
Simulation time 154891572 ps
CPU time 3.23 seconds
Started Feb 08 12:53:22 PM UTC 25
Finished Feb 08 12:53:27 PM UTC 25
Peak memory 232856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532323279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 29.keymgr_custom_cm.2532323279
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.480914176
Short name T17
Test name
Test status
Simulation time 167359118 ps
CPU time 3.29 seconds
Started Feb 08 12:46:58 PM UTC 25
Finished Feb 08 12:47:03 PM UTC 25
Peak memory 224400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480914176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hws
w_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.480914176
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.2791484843
Short name T3
Test name
Test status
Simulation time 1625505477 ps
CPU time 10.06 seconds
Started Feb 08 12:46:18 PM UTC 25
Finished Feb 08 12:46:30 PM UTC 25
Peak memory 218504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791484843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2791484843
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.611443144
Short name T50
Test name
Test status
Simulation time 47887776 ps
CPU time 2.51 seconds
Started Feb 08 12:47:45 PM UTC 25
Finished Feb 08 12:47:49 PM UTC 25
Peak memory 230640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611443144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.611443144
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.1864912098
Short name T314
Test name
Test status
Simulation time 129641563 ps
CPU time 4.22 seconds
Started Feb 08 12:50:20 PM UTC 25
Finished Feb 08 12:50:25 PM UTC 25
Peak memory 226384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864912098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1864912098
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all_with_rand_reset.826870316
Short name T127
Test name
Test status
Simulation time 156517013 ps
CPU time 12.02 seconds
Started Feb 08 12:50:32 PM UTC 25
Finished Feb 08 12:50:46 PM UTC 25
Peak memory 232484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=826870316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_
reset.826870316
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.804790097
Short name T358
Test name
Test status
Simulation time 109288936 ps
CPU time 4.7 seconds
Started Feb 08 12:50:40 PM UTC 25
Finished Feb 08 12:50:46 PM UTC 25
Peak memory 224340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804790097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.804790097
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.3194573306
Short name T56
Test name
Test status
Simulation time 115510756 ps
CPU time 2.4 seconds
Started Feb 08 12:51:07 PM UTC 25
Finished Feb 08 12:51:11 PM UTC 25
Peak memory 226704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194573306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3194573306
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.412594289
Short name T238
Test name
Test status
Simulation time 700750025 ps
CPU time 4.98 seconds
Started Feb 08 12:51:45 PM UTC 25
Finished Feb 08 12:51:51 PM UTC 25
Peak memory 218288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412594289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 19.keymgr_lc_disable.412594289
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_random.2990266531
Short name T223
Test name
Test status
Simulation time 1918701478 ps
CPU time 49.67 seconds
Started Feb 08 12:48:06 PM UTC 25
Finished Feb 08 12:48:58 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990266531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.keymgr_random.2990266531
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.2860740381
Short name T407
Test name
Test status
Simulation time 386016541 ps
CPU time 6.03 seconds
Started Feb 08 12:51:58 PM UTC 25
Finished Feb 08 12:52:06 PM UTC 25
Peak memory 220304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860740381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 20.keymgr_lc_disable.2860740381
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.1225622003
Short name T340
Test name
Test status
Simulation time 10837550540 ps
CPU time 132.97 seconds
Started Feb 08 12:52:32 PM UTC 25
Finished Feb 08 12:54:48 PM UTC 25
Peak memory 228552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225622003 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1225622003
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.3464190894
Short name T239
Test name
Test status
Simulation time 252695808 ps
CPU time 3.58 seconds
Started Feb 08 12:53:20 PM UTC 25
Finished Feb 08 12:53:24 PM UTC 25
Peak memory 224828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464190894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 29.keymgr_lc_disable.3464190894
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.1411094631
Short name T354
Test name
Test status
Simulation time 197990040 ps
CPU time 4.15 seconds
Started Feb 08 12:53:44 PM UTC 25
Finished Feb 08 12:53:50 PM UTC 25
Peak memory 226476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411094631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1411094631
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.1045060963
Short name T446
Test name
Test status
Simulation time 1013593274 ps
CPU time 13.89 seconds
Started Feb 08 12:54:30 PM UTC 25
Finished Feb 08 12:54:45 PM UTC 25
Peak memory 224392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045060963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1045060963
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.866137347
Short name T252
Test name
Test status
Simulation time 3988578891 ps
CPU time 64.98 seconds
Started Feb 08 12:54:56 PM UTC 25
Finished Feb 08 12:56:03 PM UTC 25
Peak memory 232684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866137347 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.866137347
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.1779691859
Short name T254
Test name
Test status
Simulation time 64229481 ps
CPU time 3.81 seconds
Started Feb 08 12:55:14 PM UTC 25
Finished Feb 08 12:55:19 PM UTC 25
Peak memory 218252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779691859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 45.keymgr_lc_disable.1779691859
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.1787752648
Short name T177
Test name
Test status
Simulation time 517198994 ps
CPU time 5.79 seconds
Started Feb 08 12:51:37 PM UTC 25
Finished Feb 08 12:51:45 PM UTC 25
Peak memory 229072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787752648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 18.keymgr_custom_cm.1787752648
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.390470132
Short name T183
Test name
Test status
Simulation time 167624681 ps
CPU time 3.15 seconds
Started Feb 08 12:54:32 PM UTC 25
Finished Feb 08 12:54:36 PM UTC 25
Peak memory 232228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390470132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cus
tom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.keymgr_custom_cm.390470132
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.3582912561
Short name T423
Test name
Test status
Simulation time 1228697558 ps
CPU time 6.49 seconds
Started Feb 08 02:46:34 PM UTC 25
Finished Feb 08 02:46:42 PM UTC 25
Peak memory 215956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582912561 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3582912561
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1827278179
Short name T927
Test name
Test status
Simulation time 1791087838 ps
CPU time 18.96 seconds
Started Feb 08 02:46:32 PM UTC 25
Finished Feb 08 02:46:52 PM UTC 25
Peak memory 215756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827278179 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1827278179
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3066344215
Short name T147
Test name
Test status
Simulation time 28959513 ps
CPU time 1.53 seconds
Started Feb 08 02:46:28 PM UTC 25
Finished Feb 08 02:46:33 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066344215 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3066344215
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1622625366
Short name T191
Test name
Test status
Simulation time 98340713 ps
CPU time 1.4 seconds
Started Feb 08 02:46:35 PM UTC 25
Finished Feb 08 02:46:38 PM UTC 25
Peak memory 214868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622625
366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1622625366
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.1016573769
Short name T139
Test name
Test status
Simulation time 23629129 ps
CPU time 1.45 seconds
Started Feb 08 02:46:31 PM UTC 25
Finished Feb 08 02:46:33 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016573769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1016573769
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.434084895
Short name T921
Test name
Test status
Simulation time 34674108 ps
CPU time 0.99 seconds
Started Feb 08 02:46:26 PM UTC 25
Finished Feb 08 02:46:31 PM UTC 25
Peak memory 213160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434084895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.434084895
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3036649631
Short name T140
Test name
Test status
Simulation time 31851631 ps
CPU time 2.49 seconds
Started Feb 08 02:46:34 PM UTC 25
Finished Feb 08 02:46:38 PM UTC 25
Peak memory 215792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036649631 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.3036649631
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.4164532723
Short name T115
Test name
Test status
Simulation time 274171560 ps
CPU time 3.56 seconds
Started Feb 08 02:46:18 PM UTC 25
Finished Feb 08 02:46:25 PM UTC 25
Peak memory 226344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164532723 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.4164532723
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.1764584328
Short name T920
Test name
Test status
Simulation time 472075615 ps
CPU time 4.81 seconds
Started Feb 08 02:46:22 PM UTC 25
Finished Feb 08 02:46:29 PM UTC 25
Peak memory 228000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764584328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1764584328
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.3038805559
Short name T148
Test name
Test status
Simulation time 218188706 ps
CPU time 3.27 seconds
Started Feb 08 02:46:26 PM UTC 25
Finished Feb 08 02:46:33 PM UTC 25
Peak memory 215624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038805559 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.3038805559
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.845481888
Short name T143
Test name
Test status
Simulation time 268744004 ps
CPU time 5.37 seconds
Started Feb 08 02:46:43 PM UTC 25
Finished Feb 08 02:46:50 PM UTC 25
Peak memory 216016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845481888 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.845481888
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2423629015
Short name T937
Test name
Test status
Simulation time 861337371 ps
CPU time 27.99 seconds
Started Feb 08 02:46:42 PM UTC 25
Finished Feb 08 02:47:12 PM UTC 25
Peak memory 216052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423629015 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2423629015
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2782531354
Short name T923
Test name
Test status
Simulation time 125048862 ps
CPU time 1.43 seconds
Started Feb 08 02:46:40 PM UTC 25
Finished Feb 08 02:46:43 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782531354 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2782531354
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3965329445
Short name T925
Test name
Test status
Simulation time 18407230 ps
CPU time 1.32 seconds
Started Feb 08 02:46:43 PM UTC 25
Finished Feb 08 02:46:46 PM UTC 25
Peak memory 226136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965329
445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3965329445
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.1555536571
Short name T141
Test name
Test status
Simulation time 24504849 ps
CPU time 1.39 seconds
Started Feb 08 02:46:42 PM UTC 25
Finished Feb 08 02:46:45 PM UTC 25
Peak memory 215964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555536571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1555536571
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.4140302929
Short name T922
Test name
Test status
Simulation time 21290854 ps
CPU time 0.92 seconds
Started Feb 08 02:46:40 PM UTC 25
Finished Feb 08 02:46:43 PM UTC 25
Peak memory 213108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140302929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4140302929
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3904816720
Short name T142
Test name
Test status
Simulation time 197653308 ps
CPU time 3.2 seconds
Started Feb 08 02:46:43 PM UTC 25
Finished Feb 08 02:46:48 PM UTC 25
Peak memory 215824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904816720 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.3904816720
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3537464752
Short name T117
Test name
Test status
Simulation time 825257388 ps
CPU time 2.32 seconds
Started Feb 08 02:46:35 PM UTC 25
Finished Feb 08 02:46:39 PM UTC 25
Peak memory 226688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537464752 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.3537464752
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2039360256
Short name T120
Test name
Test status
Simulation time 172248396 ps
CPU time 4.88 seconds
Started Feb 08 02:46:35 PM UTC 25
Finished Feb 08 02:46:42 PM UTC 25
Peak memory 231912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039360256 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.2039360256
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.3733048098
Short name T924
Test name
Test status
Simulation time 766139624 ps
CPU time 2.61 seconds
Started Feb 08 02:46:39 PM UTC 25
Finished Feb 08 02:46:43 PM UTC 25
Peak memory 226132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733048098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3733048098
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.4148686374
Short name T172
Test name
Test status
Simulation time 284197844 ps
CPU time 4.83 seconds
Started Feb 08 02:46:39 PM UTC 25
Finished Feb 08 02:46:45 PM UTC 25
Peak memory 226196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148686374 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.4148686374
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1814911650
Short name T985
Test name
Test status
Simulation time 116140874 ps
CPU time 1.46 seconds
Started Feb 08 02:47:46 PM UTC 25
Finished Feb 08 02:47:51 PM UTC 25
Peak memory 215992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814911
650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1814911650
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.3467532925
Short name T983
Test name
Test status
Simulation time 35549929 ps
CPU time 1.24 seconds
Started Feb 08 02:47:45 PM UTC 25
Finished Feb 08 02:47:48 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467532925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3467532925
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.2851599284
Short name T982
Test name
Test status
Simulation time 10146738 ps
CPU time 1.13 seconds
Started Feb 08 02:47:45 PM UTC 25
Finished Feb 08 02:47:48 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851599284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2851599284
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4011743198
Short name T989
Test name
Test status
Simulation time 89858876 ps
CPU time 3.95 seconds
Started Feb 08 02:47:46 PM UTC 25
Finished Feb 08 02:47:53 PM UTC 25
Peak memory 215760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011743198 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.4011743198
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3613402453
Short name T980
Test name
Test status
Simulation time 293643578 ps
CPU time 1.67 seconds
Started Feb 08 02:47:43 PM UTC 25
Finished Feb 08 02:47:46 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613402453 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.3613402453
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1284307667
Short name T986
Test name
Test status
Simulation time 243024578 ps
CPU time 6.59 seconds
Started Feb 08 02:47:43 PM UTC 25
Finished Feb 08 02:47:51 PM UTC 25
Peak memory 232352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284307667 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.1284307667
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.4098154737
Short name T981
Test name
Test status
Simulation time 207115750 ps
CPU time 3.56 seconds
Started Feb 08 02:47:43 PM UTC 25
Finished Feb 08 02:47:48 PM UTC 25
Peak memory 227996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098154737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.4098154737
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.561095333
Short name T992
Test name
Test status
Simulation time 113050646 ps
CPU time 2.27 seconds
Started Feb 08 02:47:52 PM UTC 25
Finished Feb 08 02:47:56 PM UTC 25
Peak memory 226048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5610953
33 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.561095333
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.3243779300
Short name T990
Test name
Test status
Simulation time 164366830 ps
CPU time 1.52 seconds
Started Feb 08 02:47:50 PM UTC 25
Finished Feb 08 02:47:53 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243779300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3243779300
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.2868415449
Short name T987
Test name
Test status
Simulation time 55277912 ps
CPU time 0.95 seconds
Started Feb 08 02:47:50 PM UTC 25
Finished Feb 08 02:47:52 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868415449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2868415449
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.4292160974
Short name T991
Test name
Test status
Simulation time 86261607 ps
CPU time 1.69 seconds
Started Feb 08 02:47:51 PM UTC 25
Finished Feb 08 02:47:54 PM UTC 25
Peak memory 215952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292160974 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.4292160974
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.188333026
Short name T988
Test name
Test status
Simulation time 224241011 ps
CPU time 3.46 seconds
Started Feb 08 02:47:46 PM UTC 25
Finished Feb 08 02:47:53 PM UTC 25
Peak memory 226276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188333026 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymg
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.188333026
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2728071400
Short name T1006
Test name
Test status
Simulation time 344996058 ps
CPU time 14.74 seconds
Started Feb 08 02:47:49 PM UTC 25
Finished Feb 08 02:48:05 PM UTC 25
Peak memory 226516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728071400 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.2728071400
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.2789313242
Short name T995
Test name
Test status
Simulation time 424875607 ps
CPU time 6.81 seconds
Started Feb 08 02:47:49 PM UTC 25
Finished Feb 08 02:47:58 PM UTC 25
Peak memory 225968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789313242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2789313242
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.1844193046
Short name T155
Test name
Test status
Simulation time 130141802 ps
CPU time 6.03 seconds
Started Feb 08 02:47:49 PM UTC 25
Finished Feb 08 02:47:57 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844193046 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.1844193046
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.245032555
Short name T998
Test name
Test status
Simulation time 45498487 ps
CPU time 1.98 seconds
Started Feb 08 02:47:57 PM UTC 25
Finished Feb 08 02:48:01 PM UTC 25
Peak memory 226076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450325
55 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.245032555
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.578822855
Short name T996
Test name
Test status
Simulation time 374695101 ps
CPU time 1.59 seconds
Started Feb 08 02:47:55 PM UTC 25
Finished Feb 08 02:47:58 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578822855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.578822855
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.4063322094
Short name T993
Test name
Test status
Simulation time 37768278 ps
CPU time 0.93 seconds
Started Feb 08 02:47:54 PM UTC 25
Finished Feb 08 02:47:56 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063322094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4063322094
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3791449757
Short name T1000
Test name
Test status
Simulation time 84641129 ps
CPU time 3.19 seconds
Started Feb 08 02:47:57 PM UTC 25
Finished Feb 08 02:48:02 PM UTC 25
Peak memory 215724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791449757 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.3791449757
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2331794758
Short name T994
Test name
Test status
Simulation time 76166958 ps
CPU time 3.19 seconds
Started Feb 08 02:47:52 PM UTC 25
Finished Feb 08 02:47:57 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331794758 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.2331794758
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3458772830
Short name T1001
Test name
Test status
Simulation time 900689103 ps
CPU time 7.42 seconds
Started Feb 08 02:47:54 PM UTC 25
Finished Feb 08 02:48:03 PM UTC 25
Peak memory 232420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458772830 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.3458772830
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.1402017060
Short name T997
Test name
Test status
Simulation time 751103372 ps
CPU time 4.74 seconds
Started Feb 08 02:47:54 PM UTC 25
Finished Feb 08 02:48:00 PM UTC 25
Peak memory 227996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402017060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1402017060
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.914610987
Short name T168
Test name
Test status
Simulation time 124094905 ps
CPU time 4.44 seconds
Started Feb 08 02:47:54 PM UTC 25
Finished Feb 08 02:48:00 PM UTC 25
Peak memory 226264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914610987 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.914610987
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.577169998
Short name T1005
Test name
Test status
Simulation time 106592849 ps
CPU time 1.59 seconds
Started Feb 08 02:48:02 PM UTC 25
Finished Feb 08 02:48:05 PM UTC 25
Peak memory 213112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5771699
98 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.577169998
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.2941959791
Short name T1003
Test name
Test status
Simulation time 110205033 ps
CPU time 1.87 seconds
Started Feb 08 02:48:01 PM UTC 25
Finished Feb 08 02:48:04 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941959791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2941959791
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.2255048003
Short name T1002
Test name
Test status
Simulation time 67799122 ps
CPU time 0.84 seconds
Started Feb 08 02:48:01 PM UTC 25
Finished Feb 08 02:48:03 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255048003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2255048003
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3283414589
Short name T1007
Test name
Test status
Simulation time 712279469 ps
CPU time 2.22 seconds
Started Feb 08 02:48:02 PM UTC 25
Finished Feb 08 02:48:06 PM UTC 25
Peak memory 215960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283414589 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.3283414589
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3087744744
Short name T999
Test name
Test status
Simulation time 96227331 ps
CPU time 2.32 seconds
Started Feb 08 02:47:57 PM UTC 25
Finished Feb 08 02:48:01 PM UTC 25
Peak memory 226324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087744744 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.3087744744
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3795680330
Short name T1013
Test name
Test status
Simulation time 1140876712 ps
CPU time 11.79 seconds
Started Feb 08 02:47:57 PM UTC 25
Finished Feb 08 02:48:10 PM UTC 25
Peak memory 226304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795680330 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.3795680330
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.1002083908
Short name T1004
Test name
Test status
Simulation time 966863975 ps
CPU time 5.16 seconds
Started Feb 08 02:47:59 PM UTC 25
Finished Feb 08 02:48:05 PM UTC 25
Peak memory 228252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002083908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1002083908
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3181387491
Short name T1014
Test name
Test status
Simulation time 46326732 ps
CPU time 2.6 seconds
Started Feb 08 02:48:07 PM UTC 25
Finished Feb 08 02:48:11 PM UTC 25
Peak memory 228064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181387
491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3181387491
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.606578100
Short name T1009
Test name
Test status
Simulation time 52726712 ps
CPU time 1.43 seconds
Started Feb 08 02:48:06 PM UTC 25
Finished Feb 08 02:48:09 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606578100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.606578100
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.3939819529
Short name T1008
Test name
Test status
Simulation time 19032777 ps
CPU time 0.91 seconds
Started Feb 08 02:48:05 PM UTC 25
Finished Feb 08 02:48:07 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939819529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3939819529
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1812413338
Short name T1015
Test name
Test status
Simulation time 108814744 ps
CPU time 4.52 seconds
Started Feb 08 02:48:06 PM UTC 25
Finished Feb 08 02:48:12 PM UTC 25
Peak memory 216116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812413338 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.1812413338
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3241621919
Short name T1010
Test name
Test status
Simulation time 184259436 ps
CPU time 4.13 seconds
Started Feb 08 02:48:03 PM UTC 25
Finished Feb 08 02:48:09 PM UTC 25
Peak memory 226328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241621919 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.3241621919
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1819732514
Short name T1012
Test name
Test status
Simulation time 94867562 ps
CPU time 5.65 seconds
Started Feb 08 02:48:03 PM UTC 25
Finished Feb 08 02:48:10 PM UTC 25
Peak memory 226656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819732514 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.1819732514
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1879747403
Short name T1011
Test name
Test status
Simulation time 106534860 ps
CPU time 3.66 seconds
Started Feb 08 02:48:05 PM UTC 25
Finished Feb 08 02:48:10 PM UTC 25
Peak memory 225876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879747403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1879747403
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.681568744
Short name T1019
Test name
Test status
Simulation time 26089205 ps
CPU time 1.72 seconds
Started Feb 08 02:48:12 PM UTC 25
Finished Feb 08 02:48:15 PM UTC 25
Peak memory 226108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6815687
44 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.681568744
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.748852396
Short name T1017
Test name
Test status
Simulation time 23553136 ps
CPU time 1.52 seconds
Started Feb 08 02:48:11 PM UTC 25
Finished Feb 08 02:48:14 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748852396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.748852396
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.2268748854
Short name T1016
Test name
Test status
Simulation time 32409444 ps
CPU time 0.97 seconds
Started Feb 08 02:48:10 PM UTC 25
Finished Feb 08 02:48:12 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268748854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2268748854
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.628450942
Short name T1022
Test name
Test status
Simulation time 105810202 ps
CPU time 3.72 seconds
Started Feb 08 02:48:11 PM UTC 25
Finished Feb 08 02:48:16 PM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628450942 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ke
ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.628450942
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3189124510
Short name T1020
Test name
Test status
Simulation time 257518358 ps
CPU time 7.03 seconds
Started Feb 08 02:48:07 PM UTC 25
Finished Feb 08 02:48:15 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189124510 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.3189124510
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.708188269
Short name T1027
Test name
Test status
Simulation time 4650953228 ps
CPU time 10.58 seconds
Started Feb 08 02:48:08 PM UTC 25
Finished Feb 08 02:48:20 PM UTC 25
Peak memory 226348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708188269 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.708188269
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.1870802897
Short name T1018
Test name
Test status
Simulation time 140576878 ps
CPU time 3.46 seconds
Started Feb 08 02:48:09 PM UTC 25
Finished Feb 08 02:48:14 PM UTC 25
Peak memory 225972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870802897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1870802897
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3134434966
Short name T1029
Test name
Test status
Simulation time 42500051 ps
CPU time 2.42 seconds
Started Feb 08 02:48:17 PM UTC 25
Finished Feb 08 02:48:21 PM UTC 25
Peak memory 226016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134434
966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3134434966
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.990075632
Short name T1025
Test name
Test status
Simulation time 11401931 ps
CPU time 1.26 seconds
Started Feb 08 02:48:16 PM UTC 25
Finished Feb 08 02:48:18 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990075632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.990075632
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3394367845
Short name T1024
Test name
Test status
Simulation time 27164488 ps
CPU time 0.87 seconds
Started Feb 08 02:48:16 PM UTC 25
Finished Feb 08 02:48:18 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394367845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3394367845
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2342438401
Short name T1026
Test name
Test status
Simulation time 269311203 ps
CPU time 1.6 seconds
Started Feb 08 02:48:17 PM UTC 25
Finished Feb 08 02:48:20 PM UTC 25
Peak memory 213164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342438401 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.2342438401
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2634968714
Short name T1021
Test name
Test status
Simulation time 153028285 ps
CPU time 2.44 seconds
Started Feb 08 02:48:12 PM UTC 25
Finished Feb 08 02:48:16 PM UTC 25
Peak memory 226468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634968714 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.2634968714
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2089719376
Short name T1030
Test name
Test status
Simulation time 868328465 ps
CPU time 6.24 seconds
Started Feb 08 02:48:13 PM UTC 25
Finished Feb 08 02:48:21 PM UTC 25
Peak memory 232728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089719376 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.2089719376
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.7085374
Short name T1023
Test name
Test status
Simulation time 441183905 ps
CPU time 2.46 seconds
Started Feb 08 02:48:13 PM UTC 25
Finished Feb 08 02:48:17 PM UTC 25
Peak memory 226040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7085374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.7085374
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2890949565
Short name T1033
Test name
Test status
Simulation time 37192916 ps
CPU time 1.66 seconds
Started Feb 08 02:48:21 PM UTC 25
Finished Feb 08 02:48:24 PM UTC 25
Peak memory 213172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890949
565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2890949565
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.2208783035
Short name T1032
Test name
Test status
Simulation time 26114055 ps
CPU time 1.42 seconds
Started Feb 08 02:48:21 PM UTC 25
Finished Feb 08 02:48:24 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208783035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2208783035
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.777727667
Short name T1031
Test name
Test status
Simulation time 27436351 ps
CPU time 0.91 seconds
Started Feb 08 02:48:20 PM UTC 25
Finished Feb 08 02:48:22 PM UTC 25
Peak memory 213164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777727667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.777727667
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1194869393
Short name T1034
Test name
Test status
Simulation time 265014054 ps
CPU time 2.61 seconds
Started Feb 08 02:48:21 PM UTC 25
Finished Feb 08 02:48:25 PM UTC 25
Peak memory 215796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194869393 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.1194869393
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2410567142
Short name T1028
Test name
Test status
Simulation time 56940146 ps
CPU time 2.33 seconds
Started Feb 08 02:48:17 PM UTC 25
Finished Feb 08 02:48:21 PM UTC 25
Peak memory 226532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410567142 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.2410567142
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3141353865
Short name T1040
Test name
Test status
Simulation time 219849336 ps
CPU time 7.6 seconds
Started Feb 08 02:48:18 PM UTC 25
Finished Feb 08 02:48:27 PM UTC 25
Peak memory 226532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141353865 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.3141353865
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.3067271356
Short name T1038
Test name
Test status
Simulation time 621238625 ps
CPU time 6.57 seconds
Started Feb 08 02:48:18 PM UTC 25
Finished Feb 08 02:48:26 PM UTC 25
Peak memory 226204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067271356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3067271356
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.3472456405
Short name T1036
Test name
Test status
Simulation time 402210153 ps
CPU time 4.97 seconds
Started Feb 08 02:48:20 PM UTC 25
Finished Feb 08 02:48:26 PM UTC 25
Peak memory 226204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472456405 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.3472456405
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.672392378
Short name T1042
Test name
Test status
Simulation time 46120719 ps
CPU time 2.03 seconds
Started Feb 08 02:48:26 PM UTC 25
Finished Feb 08 02:48:30 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6723923
78 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.672392378
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.1967354402
Short name T1041
Test name
Test status
Simulation time 16885324 ps
CPU time 1.46 seconds
Started Feb 08 02:48:25 PM UTC 25
Finished Feb 08 02:48:28 PM UTC 25
Peak memory 213080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967354402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1967354402
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.3279621598
Short name T1039
Test name
Test status
Simulation time 18571590 ps
CPU time 1.23 seconds
Started Feb 08 02:48:25 PM UTC 25
Finished Feb 08 02:48:27 PM UTC 25
Peak memory 213192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279621598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3279621598
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3605209815
Short name T1043
Test name
Test status
Simulation time 838712605 ps
CPU time 2.29 seconds
Started Feb 08 02:48:26 PM UTC 25
Finished Feb 08 02:48:30 PM UTC 25
Peak memory 216060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605209815 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.3605209815
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.53272824
Short name T1035
Test name
Test status
Simulation time 753006533 ps
CPU time 2.75 seconds
Started Feb 08 02:48:21 PM UTC 25
Finished Feb 08 02:48:25 PM UTC 25
Peak memory 226276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53272824 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.53272824
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.697141733
Short name T1045
Test name
Test status
Simulation time 346195439 ps
CPU time 7.62 seconds
Started Feb 08 02:48:23 PM UTC 25
Finished Feb 08 02:48:32 PM UTC 25
Peak memory 226564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697141733 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.697141733
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3837408196
Short name T1037
Test name
Test status
Simulation time 68085933 ps
CPU time 2.13 seconds
Started Feb 08 02:48:23 PM UTC 25
Finished Feb 08 02:48:26 PM UTC 25
Peak memory 226068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837408196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3837408196
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2406832779
Short name T1052
Test name
Test status
Simulation time 22470973 ps
CPU time 1.66 seconds
Started Feb 08 02:48:31 PM UTC 25
Finished Feb 08 02:48:34 PM UTC 25
Peak memory 213276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406832
779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2406832779
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.1284263933
Short name T1047
Test name
Test status
Simulation time 99770803 ps
CPU time 1.51 seconds
Started Feb 08 02:48:29 PM UTC 25
Finished Feb 08 02:48:32 PM UTC 25
Peak memory 215956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284263933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1284263933
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.1323038908
Short name T1044
Test name
Test status
Simulation time 17090642 ps
CPU time 0.93 seconds
Started Feb 08 02:48:29 PM UTC 25
Finished Feb 08 02:48:31 PM UTC 25
Peak memory 212888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323038908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1323038908
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3505831775
Short name T1050
Test name
Test status
Simulation time 202846639 ps
CPU time 2.63 seconds
Started Feb 08 02:48:29 PM UTC 25
Finished Feb 08 02:48:33 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505831775 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.3505831775
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.770535508
Short name T1051
Test name
Test status
Simulation time 1810786849 ps
CPU time 4.63 seconds
Started Feb 08 02:48:28 PM UTC 25
Finished Feb 08 02:48:34 PM UTC 25
Peak memory 226204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770535508 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymg
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.770535508
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.556344271
Short name T1060
Test name
Test status
Simulation time 620382228 ps
CPU time 7.93 seconds
Started Feb 08 02:48:28 PM UTC 25
Finished Feb 08 02:48:37 PM UTC 25
Peak memory 226532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556344271 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.556344271
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.1422182092
Short name T1046
Test name
Test status
Simulation time 39921761 ps
CPU time 2.76 seconds
Started Feb 08 02:48:28 PM UTC 25
Finished Feb 08 02:48:32 PM UTC 25
Peak memory 228276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422182092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1422182092
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.3243043814
Short name T1053
Test name
Test status
Simulation time 79686610 ps
CPU time 3.36 seconds
Started Feb 08 02:48:29 PM UTC 25
Finished Feb 08 02:48:34 PM UTC 25
Peak memory 226064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243043814 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.3243043814
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.2048504562
Short name T929
Test name
Test status
Simulation time 187368543 ps
CPU time 6.5 seconds
Started Feb 08 02:46:52 PM UTC 25
Finished Feb 08 02:47:00 PM UTC 25
Peak memory 215668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048504562 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2048504562
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3607156429
Short name T192
Test name
Test status
Simulation time 4938799395 ps
CPU time 12.6 seconds
Started Feb 08 02:46:52 PM UTC 25
Finished Feb 08 02:47:06 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607156429 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3607156429
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3066637390
Short name T201
Test name
Test status
Simulation time 18907307 ps
CPU time 1.38 seconds
Started Feb 08 02:46:50 PM UTC 25
Finished Feb 08 02:46:52 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066637390 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3066637390
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3966352896
Short name T928
Test name
Test status
Simulation time 21705650 ps
CPU time 1.78 seconds
Started Feb 08 02:46:53 PM UTC 25
Finished Feb 08 02:46:56 PM UTC 25
Peak memory 228064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966352
896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3966352896
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.3137485187
Short name T144
Test name
Test status
Simulation time 18117282 ps
CPU time 1.26 seconds
Started Feb 08 02:46:51 PM UTC 25
Finished Feb 08 02:46:53 PM UTC 25
Peak memory 213164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137485187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3137485187
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.348875793
Short name T926
Test name
Test status
Simulation time 11429270 ps
CPU time 0.92 seconds
Started Feb 08 02:46:49 PM UTC 25
Finished Feb 08 02:46:51 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348875793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.348875793
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2101691197
Short name T145
Test name
Test status
Simulation time 241918773 ps
CPU time 2.6 seconds
Started Feb 08 02:46:53 PM UTC 25
Finished Feb 08 02:46:57 PM UTC 25
Peak memory 215728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101691197 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.2101691197
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.442995549
Short name T124
Test name
Test status
Simulation time 258346006 ps
CPU time 2.5 seconds
Started Feb 08 02:46:44 PM UTC 25
Finished Feb 08 02:46:48 PM UTC 25
Peak memory 226280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442995549 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymg
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.442995549
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2234635160
Short name T122
Test name
Test status
Simulation time 1085648358 ps
CPU time 5.62 seconds
Started Feb 08 02:46:45 PM UTC 25
Finished Feb 08 02:46:52 PM UTC 25
Peak memory 226564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234635160 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.2234635160
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.1012618028
Short name T200
Test name
Test status
Simulation time 116224230 ps
CPU time 2.98 seconds
Started Feb 08 02:46:46 PM UTC 25
Finished Feb 08 02:46:51 PM UTC 25
Peak memory 225952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012618028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1012618028
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.1932865006
Short name T1048
Test name
Test status
Simulation time 14559667 ps
CPU time 0.95 seconds
Started Feb 08 02:48:31 PM UTC 25
Finished Feb 08 02:48:33 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932865006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1932865006
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.2506709058
Short name T1049
Test name
Test status
Simulation time 9290907 ps
CPU time 1.02 seconds
Started Feb 08 02:48:31 PM UTC 25
Finished Feb 08 02:48:33 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506709058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2506709058
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.1237390610
Short name T1054
Test name
Test status
Simulation time 27478930 ps
CPU time 0.98 seconds
Started Feb 08 02:48:32 PM UTC 25
Finished Feb 08 02:48:34 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237390610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1237390610
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.1641429664
Short name T1055
Test name
Test status
Simulation time 28809145 ps
CPU time 0.82 seconds
Started Feb 08 02:48:34 PM UTC 25
Finished Feb 08 02:48:36 PM UTC 25
Peak memory 213200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641429664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1641429664
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1844638407
Short name T1056
Test name
Test status
Simulation time 13029346 ps
CPU time 0.99 seconds
Started Feb 08 02:48:34 PM UTC 25
Finished Feb 08 02:48:36 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844638407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1844638407
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.2508055854
Short name T1059
Test name
Test status
Simulation time 43078719 ps
CPU time 1.12 seconds
Started Feb 08 02:48:34 PM UTC 25
Finished Feb 08 02:48:36 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508055854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2508055854
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.1652952234
Short name T1057
Test name
Test status
Simulation time 22252542 ps
CPU time 0.89 seconds
Started Feb 08 02:48:34 PM UTC 25
Finished Feb 08 02:48:36 PM UTC 25
Peak memory 213052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652952234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1652952234
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.564609344
Short name T1058
Test name
Test status
Simulation time 17530386 ps
CPU time 1.01 seconds
Started Feb 08 02:48:34 PM UTC 25
Finished Feb 08 02:48:36 PM UTC 25
Peak memory 213268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564609344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.564609344
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2621342852
Short name T1065
Test name
Test status
Simulation time 22547821 ps
CPU time 1.23 seconds
Started Feb 08 02:48:35 PM UTC 25
Finished Feb 08 02:48:38 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621342852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2621342852
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3501301519
Short name T1063
Test name
Test status
Simulation time 28146686 ps
CPU time 1.02 seconds
Started Feb 08 02:48:35 PM UTC 25
Finished Feb 08 02:48:38 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501301519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3501301519
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.3035060665
Short name T941
Test name
Test status
Simulation time 1032050998 ps
CPU time 11.08 seconds
Started Feb 08 02:47:01 PM UTC 25
Finished Feb 08 02:47:14 PM UTC 25
Peak memory 215760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035060665 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3035060665
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1542339399
Short name T938
Test name
Test status
Simulation time 565759155 ps
CPU time 9.57 seconds
Started Feb 08 02:47:01 PM UTC 25
Finished Feb 08 02:47:12 PM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542339399 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1542339399
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1978428580
Short name T931
Test name
Test status
Simulation time 272104583 ps
CPU time 1.49 seconds
Started Feb 08 02:46:58 PM UTC 25
Finished Feb 08 02:47:01 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978428580 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1978428580
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.539398968
Short name T193
Test name
Test status
Simulation time 52773969 ps
CPU time 1.45 seconds
Started Feb 08 02:47:04 PM UTC 25
Finished Feb 08 02:47:06 PM UTC 25
Peak memory 213280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5393989
68 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.539398968
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.3022845276
Short name T932
Test name
Test status
Simulation time 31974387 ps
CPU time 1.19 seconds
Started Feb 08 02:47:00 PM UTC 25
Finished Feb 08 02:47:03 PM UTC 25
Peak memory 213164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022845276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3022845276
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.733789587
Short name T930
Test name
Test status
Simulation time 34254665 ps
CPU time 1.03 seconds
Started Feb 08 02:46:58 PM UTC 25
Finished Feb 08 02:47:00 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733789587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.733789587
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.233316739
Short name T934
Test name
Test status
Simulation time 233509850 ps
CPU time 2.48 seconds
Started Feb 08 02:47:02 PM UTC 25
Finished Feb 08 02:47:06 PM UTC 25
Peak memory 215728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233316739 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ke
ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.233316739
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4189303518
Short name T125
Test name
Test status
Simulation time 1085583985 ps
CPU time 2.95 seconds
Started Feb 08 02:46:53 PM UTC 25
Finished Feb 08 02:46:57 PM UTC 25
Peak memory 226536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189303518 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.4189303518
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1925457487
Short name T123
Test name
Test status
Simulation time 307235459 ps
CPU time 5.81 seconds
Started Feb 08 02:46:54 PM UTC 25
Finished Feb 08 02:47:01 PM UTC 25
Peak memory 226468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925457487 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.1925457487
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.1398191994
Short name T933
Test name
Test status
Simulation time 285195023 ps
CPU time 4.49 seconds
Started Feb 08 02:46:57 PM UTC 25
Finished Feb 08 02:47:03 PM UTC 25
Peak memory 226112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398191994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1398191994
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.2121457714
Short name T164
Test name
Test status
Simulation time 226306581 ps
CPU time 5.99 seconds
Started Feb 08 02:46:57 PM UTC 25
Finished Feb 08 02:47:04 PM UTC 25
Peak memory 215824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121457714 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.2121457714
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.1292100654
Short name T1064
Test name
Test status
Simulation time 46770106 ps
CPU time 1.14 seconds
Started Feb 08 02:48:35 PM UTC 25
Finished Feb 08 02:48:38 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292100654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1292100654
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.1704905694
Short name T1061
Test name
Test status
Simulation time 11567227 ps
CPU time 0.9 seconds
Started Feb 08 02:48:35 PM UTC 25
Finished Feb 08 02:48:38 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704905694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1704905694
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.108360910
Short name T1062
Test name
Test status
Simulation time 36020822 ps
CPU time 0.91 seconds
Started Feb 08 02:48:36 PM UTC 25
Finished Feb 08 02:48:38 PM UTC 25
Peak memory 213164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108360910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.108360910
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.1710479296
Short name T1066
Test name
Test status
Simulation time 26017095 ps
CPU time 0.94 seconds
Started Feb 08 02:48:37 PM UTC 25
Finished Feb 08 02:48:39 PM UTC 25
Peak memory 213072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710479296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1710479296
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1651023384
Short name T1067
Test name
Test status
Simulation time 41876434 ps
CPU time 1.03 seconds
Started Feb 08 02:48:37 PM UTC 25
Finished Feb 08 02:48:39 PM UTC 25
Peak memory 213076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651023384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1651023384
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.1794529101
Short name T1069
Test name
Test status
Simulation time 38489969 ps
CPU time 1.09 seconds
Started Feb 08 02:48:37 PM UTC 25
Finished Feb 08 02:48:40 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794529101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1794529101
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.836582290
Short name T1070
Test name
Test status
Simulation time 32963358 ps
CPU time 1 seconds
Started Feb 08 02:48:37 PM UTC 25
Finished Feb 08 02:48:40 PM UTC 25
Peak memory 213164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836582290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.836582290
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.2233256871
Short name T1068
Test name
Test status
Simulation time 33495588 ps
CPU time 0.9 seconds
Started Feb 08 02:48:37 PM UTC 25
Finished Feb 08 02:48:40 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233256871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2233256871
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.1126776369
Short name T1076
Test name
Test status
Simulation time 221095742 ps
CPU time 1.29 seconds
Started Feb 08 02:48:39 PM UTC 25
Finished Feb 08 02:48:42 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126776369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1126776369
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.3691094729
Short name T1074
Test name
Test status
Simulation time 17392069 ps
CPU time 1.16 seconds
Started Feb 08 02:48:39 PM UTC 25
Finished Feb 08 02:48:42 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691094729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3691094729
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.798622235
Short name T944
Test name
Test status
Simulation time 128871988 ps
CPU time 3.51 seconds
Started Feb 08 02:47:12 PM UTC 25
Finished Feb 08 02:47:18 PM UTC 25
Peak memory 215872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798622235 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.798622235
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1298623435
Short name T950
Test name
Test status
Simulation time 1740208401 ps
CPU time 8.57 seconds
Started Feb 08 02:47:12 PM UTC 25
Finished Feb 08 02:47:23 PM UTC 25
Peak memory 215716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298623435 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1298623435
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1789153385
Short name T936
Test name
Test status
Simulation time 60765581 ps
CPU time 1.42 seconds
Started Feb 08 02:47:08 PM UTC 25
Finished Feb 08 02:47:11 PM UTC 25
Peak memory 213168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789153385 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1789153385
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1082762601
Short name T943
Test name
Test status
Simulation time 25719662 ps
CPU time 2.03 seconds
Started Feb 08 02:47:13 PM UTC 25
Finished Feb 08 02:47:17 PM UTC 25
Peak memory 226296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082762
601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1082762601
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.4270976851
Short name T940
Test name
Test status
Simulation time 76404991 ps
CPU time 1.33 seconds
Started Feb 08 02:47:10 PM UTC 25
Finished Feb 08 02:47:13 PM UTC 25
Peak memory 213164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270976851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4270976851
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.505185139
Short name T935
Test name
Test status
Simulation time 11844158 ps
CPU time 0.91 seconds
Started Feb 08 02:47:07 PM UTC 25
Finished Feb 08 02:47:09 PM UTC 25
Peak memory 213108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505185139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.505185139
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1408846894
Short name T942
Test name
Test status
Simulation time 20106559 ps
CPU time 1.54 seconds
Started Feb 08 02:47:13 PM UTC 25
Finished Feb 08 02:47:17 PM UTC 25
Peak memory 212904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408846894 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.1408846894
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.525680270
Short name T213
Test name
Test status
Simulation time 70962016 ps
CPU time 2.03 seconds
Started Feb 08 02:47:04 PM UTC 25
Finished Feb 08 02:47:07 PM UTC 25
Peak memory 226232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525680270 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymg
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.525680270
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2321393461
Short name T121
Test name
Test status
Simulation time 136410734 ps
CPU time 4.01 seconds
Started Feb 08 02:47:06 PM UTC 25
Finished Feb 08 02:47:11 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321393461 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.2321393461
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.2876564391
Short name T939
Test name
Test status
Simulation time 223744147 ps
CPU time 4.45 seconds
Started Feb 08 02:47:07 PM UTC 25
Finished Feb 08 02:47:13 PM UTC 25
Peak memory 225848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876564391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2876564391
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.1103358204
Short name T171
Test name
Test status
Simulation time 100287532 ps
CPU time 3.52 seconds
Started Feb 08 02:47:07 PM UTC 25
Finished Feb 08 02:47:12 PM UTC 25
Peak memory 225968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103358204 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.1103358204
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.3027294754
Short name T1071
Test name
Test status
Simulation time 52083554 ps
CPU time 0.94 seconds
Started Feb 08 02:48:39 PM UTC 25
Finished Feb 08 02:48:42 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027294754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3027294754
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.3936725277
Short name T1072
Test name
Test status
Simulation time 136628744 ps
CPU time 0.9 seconds
Started Feb 08 02:48:39 PM UTC 25
Finished Feb 08 02:48:42 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936725277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3936725277
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.1276845759
Short name T1073
Test name
Test status
Simulation time 115375199 ps
CPU time 0.95 seconds
Started Feb 08 02:48:40 PM UTC 25
Finished Feb 08 02:48:42 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276845759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1276845759
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.4089088190
Short name T1075
Test name
Test status
Simulation time 38236981 ps
CPU time 1.04 seconds
Started Feb 08 02:48:40 PM UTC 25
Finished Feb 08 02:48:42 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089088190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4089088190
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.898154165
Short name T1078
Test name
Test status
Simulation time 13869002 ps
CPU time 1.14 seconds
Started Feb 08 02:48:42 PM UTC 25
Finished Feb 08 02:48:45 PM UTC 25
Peak memory 213164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898154165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.898154165
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.4091128527
Short name T1081
Test name
Test status
Simulation time 28381787 ps
CPU time 1.23 seconds
Started Feb 08 02:48:42 PM UTC 25
Finished Feb 08 02:48:45 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091128527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4091128527
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.2756540095
Short name T1079
Test name
Test status
Simulation time 15083334 ps
CPU time 1.13 seconds
Started Feb 08 02:48:42 PM UTC 25
Finished Feb 08 02:48:45 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756540095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2756540095
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.2708231305
Short name T1077
Test name
Test status
Simulation time 12892605 ps
CPU time 0.92 seconds
Started Feb 08 02:48:42 PM UTC 25
Finished Feb 08 02:48:45 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708231305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2708231305
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.3907232735
Short name T1080
Test name
Test status
Simulation time 12746592 ps
CPU time 1.12 seconds
Started Feb 08 02:48:42 PM UTC 25
Finished Feb 08 02:48:45 PM UTC 25
Peak memory 213104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907232735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3907232735
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.4283489845
Short name T1082
Test name
Test status
Simulation time 17945915 ps
CPU time 1.07 seconds
Started Feb 08 02:48:44 PM UTC 25
Finished Feb 08 02:48:46 PM UTC 25
Peak memory 213272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283489845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4283489845
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1797186419
Short name T948
Test name
Test status
Simulation time 32831888 ps
CPU time 1.37 seconds
Started Feb 08 02:47:19 PM UTC 25
Finished Feb 08 02:47:22 PM UTC 25
Peak memory 213172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797186
419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1797186419
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.1756760439
Short name T947
Test name
Test status
Simulation time 23672359 ps
CPU time 1.22 seconds
Started Feb 08 02:47:19 PM UTC 25
Finished Feb 08 02:47:21 PM UTC 25
Peak memory 212888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756760439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1756760439
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.1670226722
Short name T946
Test name
Test status
Simulation time 19268294 ps
CPU time 1.06 seconds
Started Feb 08 02:47:18 PM UTC 25
Finished Feb 08 02:47:20 PM UTC 25
Peak memory 213108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670226722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1670226722
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.650187312
Short name T952
Test name
Test status
Simulation time 711808126 ps
CPU time 4.3 seconds
Started Feb 08 02:47:19 PM UTC 25
Finished Feb 08 02:47:25 PM UTC 25
Peak memory 215456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650187312 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/ke
ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.650187312
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.205789667
Short name T945
Test name
Test status
Simulation time 236775881 ps
CPU time 2.5 seconds
Started Feb 08 02:47:13 PM UTC 25
Finished Feb 08 02:47:18 PM UTC 25
Peak memory 225884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205789667 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymg
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.205789667
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.1790346278
Short name T949
Test name
Test status
Simulation time 576693544 ps
CPU time 5.31 seconds
Started Feb 08 02:47:15 PM UTC 25
Finished Feb 08 02:47:22 PM UTC 25
Peak memory 228000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790346278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1790346278
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1996597772
Short name T957
Test name
Test status
Simulation time 90875049 ps
CPU time 1.95 seconds
Started Feb 08 02:47:25 PM UTC 25
Finished Feb 08 02:47:29 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996597
772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1996597772
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.414747012
Short name T953
Test name
Test status
Simulation time 102551894 ps
CPU time 1.61 seconds
Started Feb 08 02:47:24 PM UTC 25
Finished Feb 08 02:47:27 PM UTC 25
Peak memory 213268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414747012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.414747012
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.2261068749
Short name T954
Test name
Test status
Simulation time 40996380 ps
CPU time 1.06 seconds
Started Feb 08 02:47:23 PM UTC 25
Finished Feb 08 02:47:26 PM UTC 25
Peak memory 213276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261068749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2261068749
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3277758056
Short name T960
Test name
Test status
Simulation time 1677386702 ps
CPU time 4.09 seconds
Started Feb 08 02:47:25 PM UTC 25
Finished Feb 08 02:47:31 PM UTC 25
Peak memory 215632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277758056 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.3277758056
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1072533886
Short name T955
Test name
Test status
Simulation time 114009964 ps
CPU time 4.19 seconds
Started Feb 08 02:47:21 PM UTC 25
Finished Feb 08 02:47:27 PM UTC 25
Peak memory 226268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072533886 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.1072533886
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1135616713
Short name T962
Test name
Test status
Simulation time 2965014358 ps
CPU time 9.83 seconds
Started Feb 08 02:47:21 PM UTC 25
Finished Feb 08 02:47:32 PM UTC 25
Peak memory 226604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135616713 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.1135616713
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.2687474021
Short name T956
Test name
Test status
Simulation time 75191831 ps
CPU time 3.32 seconds
Started Feb 08 02:47:22 PM UTC 25
Finished Feb 08 02:47:27 PM UTC 25
Peak memory 228376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687474021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2687474021
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.655107860
Short name T964
Test name
Test status
Simulation time 53098270 ps
CPU time 2.02 seconds
Started Feb 08 02:47:31 PM UTC 25
Finished Feb 08 02:47:35 PM UTC 25
Peak memory 226144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6551078
60 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.655107860
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.4063357679
Short name T963
Test name
Test status
Simulation time 116911344 ps
CPU time 1.87 seconds
Started Feb 08 02:47:30 PM UTC 25
Finished Feb 08 02:47:33 PM UTC 25
Peak memory 213164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063357679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.4063357679
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.3935618590
Short name T958
Test name
Test status
Simulation time 33655924 ps
CPU time 1.01 seconds
Started Feb 08 02:47:28 PM UTC 25
Finished Feb 08 02:47:31 PM UTC 25
Peak memory 213276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935618590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3935618590
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3776162743
Short name T965
Test name
Test status
Simulation time 305953066 ps
CPU time 2.37 seconds
Started Feb 08 02:47:31 PM UTC 25
Finished Feb 08 02:47:35 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776162743 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.3776162743
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1975714815
Short name T959
Test name
Test status
Simulation time 68632914 ps
CPU time 2.47 seconds
Started Feb 08 02:47:27 PM UTC 25
Finished Feb 08 02:47:31 PM UTC 25
Peak memory 225992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975714815 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.1975714815
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1436697233
Short name T966
Test name
Test status
Simulation time 647761266 ps
CPU time 7.93 seconds
Started Feb 08 02:47:27 PM UTC 25
Finished Feb 08 02:47:36 PM UTC 25
Peak memory 226000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436697233 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.1436697233
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.2669855038
Short name T961
Test name
Test status
Simulation time 405099746 ps
CPU time 2.03 seconds
Started Feb 08 02:47:28 PM UTC 25
Finished Feb 08 02:47:31 PM UTC 25
Peak memory 225968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669855038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2669855038
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.4168919297
Short name T175
Test name
Test status
Simulation time 95516970 ps
CPU time 3.73 seconds
Started Feb 08 02:47:28 PM UTC 25
Finished Feb 08 02:47:33 PM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168919297 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.4168919297
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3136736486
Short name T971
Test name
Test status
Simulation time 26860072 ps
CPU time 1.48 seconds
Started Feb 08 02:47:36 PM UTC 25
Finished Feb 08 02:47:39 PM UTC 25
Peak memory 213172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136736
486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3136736486
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.2263837616
Short name T969
Test name
Test status
Simulation time 16633376 ps
CPU time 1.15 seconds
Started Feb 08 02:47:35 PM UTC 25
Finished Feb 08 02:47:37 PM UTC 25
Peak memory 213268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263837616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2263837616
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.3387384980
Short name T967
Test name
Test status
Simulation time 12079805 ps
CPU time 0.89 seconds
Started Feb 08 02:47:35 PM UTC 25
Finished Feb 08 02:47:37 PM UTC 25
Peak memory 213108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387384980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3387384980
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3061894689
Short name T972
Test name
Test status
Simulation time 22952706 ps
CPU time 1.98 seconds
Started Feb 08 02:47:36 PM UTC 25
Finished Feb 08 02:47:39 PM UTC 25
Peak memory 215984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061894689 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.3061894689
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.505302532
Short name T970
Test name
Test status
Simulation time 182318446 ps
CPU time 4.77 seconds
Started Feb 08 02:47:32 PM UTC 25
Finished Feb 08 02:47:39 PM UTC 25
Peak memory 230752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505302532 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymg
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.505302532
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2102807519
Short name T978
Test name
Test status
Simulation time 1379348239 ps
CPU time 11.08 seconds
Started Feb 08 02:47:32 PM UTC 25
Finished Feb 08 02:47:45 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102807519 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.2102807519
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.3620537712
Short name T968
Test name
Test status
Simulation time 32573129 ps
CPU time 2.38 seconds
Started Feb 08 02:47:33 PM UTC 25
Finished Feb 08 02:47:37 PM UTC 25
Peak memory 226072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620537712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3620537712
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.3954268098
Short name T161
Test name
Test status
Simulation time 114871841 ps
CPU time 4.84 seconds
Started Feb 08 02:47:34 PM UTC 25
Finished Feb 08 02:47:40 PM UTC 25
Peak memory 225872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954268098 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.3954268098
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1974477288
Short name T977
Test name
Test status
Simulation time 205565499 ps
CPU time 2.54 seconds
Started Feb 08 02:47:41 PM UTC 25
Finished Feb 08 02:47:44 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974477
288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1974477288
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.108909863
Short name T973
Test name
Test status
Simulation time 10462653 ps
CPU time 1.08 seconds
Started Feb 08 02:47:39 PM UTC 25
Finished Feb 08 02:47:42 PM UTC 25
Peak memory 213164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108909863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.108909863
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.1010504541
Short name T974
Test name
Test status
Simulation time 20383293 ps
CPU time 1.28 seconds
Started Feb 08 02:47:39 PM UTC 25
Finished Feb 08 02:47:42 PM UTC 25
Peak memory 213108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010504541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1010504541
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.10119510
Short name T976
Test name
Test status
Simulation time 26533763 ps
CPU time 2.1 seconds
Started Feb 08 02:47:41 PM UTC 25
Finished Feb 08 02:47:44 PM UTC 25
Peak memory 215724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10119510 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/key
mgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.10119510
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3571271273
Short name T975
Test name
Test status
Simulation time 483741050 ps
CPU time 4.37 seconds
Started Feb 08 02:47:37 PM UTC 25
Finished Feb 08 02:47:43 PM UTC 25
Peak memory 226400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571271273 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keym
gr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.3571271273
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4228679037
Short name T984
Test name
Test status
Simulation time 374533010 ps
CPU time 9.14 seconds
Started Feb 08 02:47:38 PM UTC 25
Finished Feb 08 02:47:49 PM UTC 25
Peak memory 226300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228679037 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.4228679037
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.2681251779
Short name T979
Test name
Test status
Simulation time 143902471 ps
CPU time 5.74 seconds
Started Feb 08 02:47:38 PM UTC 25
Finished Feb 08 02:47:46 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681251779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +U
VM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2681251779
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.836475722
Short name T156
Test name
Test status
Simulation time 927974653 ps
CPU time 7.38 seconds
Started Feb 08 02:47:38 PM UTC 25
Finished Feb 08 02:47:47 PM UTC 25
Peak memory 225872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836475722 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.836475722
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.509852086
Short name T19
Test name
Test status
Simulation time 127830204 ps
CPU time 6.72 seconds
Started Feb 08 12:47:03 PM UTC 25
Finished Feb 08 12:47:11 PM UTC 25
Peak memory 220588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509852086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cus
tom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.keymgr_custom_cm.509852086
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.837192622
Short name T18
Test name
Test status
Simulation time 543274436 ps
CPU time 19.69 seconds
Started Feb 08 12:46:43 PM UTC 25
Finished Feb 08 12:47:05 PM UTC 25
Peak memory 224416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837192622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.837192622
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.2052887833
Short name T38
Test name
Test status
Simulation time 722658865 ps
CPU time 7.6 seconds
Started Feb 08 12:47:01 PM UTC 25
Finished Feb 08 12:47:10 PM UTC 25
Peak memory 216140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052887833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2052887833
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.1115634100
Short name T15
Test name
Test status
Simulation time 132365746 ps
CPU time 3.11 seconds
Started Feb 08 12:46:53 PM UTC 25
Finished Feb 08 12:46:57 PM UTC 25
Peak memory 230616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115634100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 0.keymgr_lc_disable.1115634100
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.3390599172
Short name T2
Test name
Test status
Simulation time 43147925 ps
CPU time 3.08 seconds
Started Feb 08 12:45:57 PM UTC 25
Finished Feb 08 12:46:01 PM UTC 25
Peak memory 214480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390599172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.keymgr_sideload.3390599172
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.4195959070
Short name T14
Test name
Test status
Simulation time 5762690943 ps
CPU time 48.36 seconds
Started Feb 08 12:46:02 PM UTC 25
Finished Feb 08 12:46:52 PM UTC 25
Peak memory 218568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195959070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.4195959070
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.3649445778
Short name T4
Test name
Test status
Simulation time 57880696 ps
CPU time 3.78 seconds
Started Feb 08 12:46:30 PM UTC 25
Finished Feb 08 12:46:35 PM UTC 25
Peak memory 218520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649445778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3649445778
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.3605596426
Short name T36
Test name
Test status
Simulation time 97623650 ps
CPU time 3.47 seconds
Started Feb 08 12:47:05 PM UTC 25
Finished Feb 08 12:47:10 PM UTC 25
Peak memory 228660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605596426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3605596426
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.2286797363
Short name T1
Test name
Test status
Simulation time 176915854 ps
CPU time 5.59 seconds
Started Feb 08 12:45:49 PM UTC 25
Finished Feb 08 12:45:56 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286797363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.keymgr_smoke.2286797363
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.674574662
Short name T37
Test name
Test status
Simulation time 132099484 ps
CPU time 3.28 seconds
Started Feb 08 12:47:10 PM UTC 25
Finished Feb 08 12:47:15 PM UTC 25
Peak memory 220560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674574662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_syn
c_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.674574662
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.185759577
Short name T105
Test name
Test status
Simulation time 48650136 ps
CPU time 1.42 seconds
Started Feb 08 12:47:58 PM UTC 25
Finished Feb 08 12:48:00 PM UTC 25
Peak memory 214028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185759577 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.185759577
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.254509437
Short name T119
Test name
Test status
Simulation time 39809099 ps
CPU time 3.9 seconds
Started Feb 08 12:47:45 PM UTC 25
Finished Feb 08 12:47:51 PM UTC 25
Peak memory 226544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254509437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.254509437
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.1263057906
Short name T31
Test name
Test status
Simulation time 83296203 ps
CPU time 2.04 seconds
Started Feb 08 12:47:52 PM UTC 25
Finished Feb 08 12:47:55 PM UTC 25
Peak memory 224480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263057906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 1.keymgr_custom_cm.1263057906
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.2780473221
Short name T94
Test name
Test status
Simulation time 1250043368 ps
CPU time 5.99 seconds
Started Feb 08 12:47:50 PM UTC 25
Finished Feb 08 12:47:57 PM UTC 25
Peak memory 226528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780473221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2780473221
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.2719522445
Short name T57
Test name
Test status
Simulation time 77488715 ps
CPU time 3.55 seconds
Started Feb 08 12:47:46 PM UTC 25
Finished Feb 08 12:47:50 PM UTC 25
Peak memory 228760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719522445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 1.keymgr_lc_disable.2719522445
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_random.2621555745
Short name T113
Test name
Test status
Simulation time 201541171 ps
CPU time 4.84 seconds
Started Feb 08 12:47:40 PM UTC 25
Finished Feb 08 12:47:46 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621555745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.keymgr_random.2621555745
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.2953929026
Short name T110
Test name
Test status
Simulation time 102866747 ps
CPU time 4.16 seconds
Started Feb 08 12:47:34 PM UTC 25
Finished Feb 08 12:47:39 PM UTC 25
Peak memory 216352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953929026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.keymgr_sideload.2953929026
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.2984535311
Short name T112
Test name
Test status
Simulation time 125361136 ps
CPU time 5.37 seconds
Started Feb 08 12:47:38 PM UTC 25
Finished Feb 08 12:47:45 PM UTC 25
Peak memory 216264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984535311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2984535311
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.739405513
Short name T111
Test name
Test status
Simulation time 238592000 ps
CPU time 3.83 seconds
Started Feb 08 12:47:39 PM UTC 25
Finished Feb 08 12:47:44 PM UTC 25
Peak memory 218316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739405513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.739405513
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.271930958
Short name T222
Test name
Test status
Simulation time 1231649783 ps
CPU time 9.18 seconds
Started Feb 08 12:47:56 PM UTC 25
Finished Feb 08 12:48:06 PM UTC 25
Peak memory 218272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271930958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.271930958
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.2657685704
Short name T91
Test name
Test status
Simulation time 21341546 ps
CPU time 2.52 seconds
Started Feb 08 12:47:34 PM UTC 25
Finished Feb 08 12:47:38 PM UTC 25
Peak memory 216212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657685704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.keymgr_smoke.2657685704
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.1398712802
Short name T226
Test name
Test status
Simulation time 1619569328 ps
CPU time 10.77 seconds
Started Feb 08 12:47:48 PM UTC 25
Finished Feb 08 12:48:00 PM UTC 25
Peak memory 230532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398712802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1398712802
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.23100341
Short name T39
Test name
Test status
Simulation time 185286770 ps
CPU time 4.58 seconds
Started Feb 08 12:47:56 PM UTC 25
Finished Feb 08 12:48:02 PM UTC 25
Peak memory 220360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23100341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync
_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.23100341
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.3194249420
Short name T476
Test name
Test status
Simulation time 17306566 ps
CPU time 1.07 seconds
Started Feb 08 12:50:23 PM UTC 25
Finished Feb 08 12:50:26 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194249420 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3194249420
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.2521413282
Short name T43
Test name
Test status
Simulation time 327935758 ps
CPU time 3.17 seconds
Started Feb 08 12:50:20 PM UTC 25
Finished Feb 08 12:50:24 PM UTC 25
Peak memory 231468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521413282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 10.keymgr_custom_cm.2521413282
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.3934294475
Short name T477
Test name
Test status
Simulation time 2627654347 ps
CPU time 9.33 seconds
Started Feb 08 12:50:18 PM UTC 25
Finished Feb 08 12:50:28 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934294475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3934294475
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.4142586497
Short name T475
Test name
Test status
Simulation time 33896206 ps
CPU time 2.26 seconds
Started Feb 08 12:50:19 PM UTC 25
Finished Feb 08 12:50:22 PM UTC 25
Peak memory 224568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142586497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.4142586497
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.1834927892
Short name T447
Test name
Test status
Simulation time 153699691 ps
CPU time 4.04 seconds
Started Feb 08 12:50:18 PM UTC 25
Finished Feb 08 12:50:23 PM UTC 25
Peak memory 228568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834927892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 10.keymgr_lc_disable.1834927892
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_random.695457720
Short name T438
Test name
Test status
Simulation time 150841163 ps
CPU time 4.23 seconds
Started Feb 08 12:50:18 PM UTC 25
Finished Feb 08 12:50:23 PM UTC 25
Peak memory 224772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695457720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.keymgr_random.695457720
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.3105185387
Short name T434
Test name
Test status
Simulation time 965661956 ps
CPU time 3.6 seconds
Started Feb 08 12:50:15 PM UTC 25
Finished Feb 08 12:50:20 PM UTC 25
Peak memory 216204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105185387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.keymgr_sideload.3105185387
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.838502914
Short name T474
Test name
Test status
Simulation time 20772705 ps
CPU time 2.36 seconds
Started Feb 08 12:50:15 PM UTC 25
Finished Feb 08 12:50:19 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838502914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.838502914
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.3303774397
Short name T360
Test name
Test status
Simulation time 209839637 ps
CPU time 8.82 seconds
Started Feb 08 12:50:15 PM UTC 25
Finished Feb 08 12:50:26 PM UTC 25
Peak memory 218316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303774397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3303774397
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.4247446058
Short name T301
Test name
Test status
Simulation time 3454101565 ps
CPU time 8.57 seconds
Started Feb 08 12:50:17 PM UTC 25
Finished Feb 08 12:50:26 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247446058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.4247446058
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.357074053
Short name T451
Test name
Test status
Simulation time 445142046 ps
CPU time 2.23 seconds
Started Feb 08 12:50:20 PM UTC 25
Finished Feb 08 12:50:24 PM UTC 25
Peak memory 218324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357074053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.357074053
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.1017917438
Short name T437
Test name
Test status
Simulation time 82377903 ps
CPU time 2.2 seconds
Started Feb 08 12:50:14 PM UTC 25
Finished Feb 08 12:50:18 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017917438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.keymgr_smoke.1017917438
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.1375919484
Short name T247
Test name
Test status
Simulation time 1420550589 ps
CPU time 45.97 seconds
Started Feb 08 12:50:21 PM UTC 25
Finished Feb 08 12:51:09 PM UTC 25
Peak memory 231516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375919484 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1375919484
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.2846278700
Short name T287
Test name
Test status
Simulation time 90338392 ps
CPU time 5.45 seconds
Started Feb 08 12:50:19 PM UTC 25
Finished Feb 08 12:50:26 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846278700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2846278700
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.1749067369
Short name T69
Test name
Test status
Simulation time 100546479 ps
CPU time 2.36 seconds
Started Feb 08 12:50:21 PM UTC 25
Finished Feb 08 12:50:25 PM UTC 25
Peak memory 220416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749067369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1749067369
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.2163211571
Short name T481
Test name
Test status
Simulation time 16491763 ps
CPU time 1.08 seconds
Started Feb 08 12:50:32 PM UTC 25
Finished Feb 08 12:50:35 PM UTC 25
Peak memory 214756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163211571 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2163211571
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.2369125358
Short name T443
Test name
Test status
Simulation time 2559923724 ps
CPU time 38.01 seconds
Started Feb 08 12:50:27 PM UTC 25
Finished Feb 08 12:51:06 PM UTC 25
Peak memory 226572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369125358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2369125358
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.3574810821
Short name T30
Test name
Test status
Simulation time 225836372 ps
CPU time 6.93 seconds
Started Feb 08 12:50:31 PM UTC 25
Finished Feb 08 12:50:39 PM UTC 25
Peak memory 218792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574810821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 11.keymgr_custom_cm.3574810821
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.1563894818
Short name T322
Test name
Test status
Simulation time 490608000 ps
CPU time 3.43 seconds
Started Feb 08 12:50:27 PM UTC 25
Finished Feb 08 12:50:31 PM UTC 25
Peak memory 224392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563894818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1563894818
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.1313026515
Short name T288
Test name
Test status
Simulation time 39853628 ps
CPU time 2.86 seconds
Started Feb 08 12:50:29 PM UTC 25
Finished Feb 08 12:50:33 PM UTC 25
Peak memory 224564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313026515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1313026515
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.2736883644
Short name T379
Test name
Test status
Simulation time 90083144 ps
CPU time 3.86 seconds
Started Feb 08 12:50:31 PM UTC 25
Finished Feb 08 12:50:36 PM UTC 25
Peak memory 226384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736883644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2736883644
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.2306713654
Short name T245
Test name
Test status
Simulation time 143403497 ps
CPU time 3.38 seconds
Started Feb 08 12:50:27 PM UTC 25
Finished Feb 08 12:50:31 PM UTC 25
Peak memory 232564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306713654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 11.keymgr_lc_disable.2306713654
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_random.2454723278
Short name T435
Test name
Test status
Simulation time 484016826 ps
CPU time 9.87 seconds
Started Feb 08 12:50:27 PM UTC 25
Finished Feb 08 12:50:38 PM UTC 25
Peak memory 218124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454723278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.keymgr_random.2454723278
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.2708357119
Short name T489
Test name
Test status
Simulation time 837156209 ps
CPU time 26.04 seconds
Started Feb 08 12:50:24 PM UTC 25
Finished Feb 08 12:50:52 PM UTC 25
Peak memory 215776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708357119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.keymgr_sideload.2708357119
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.3033877643
Short name T479
Test name
Test status
Simulation time 75916640 ps
CPU time 4.04 seconds
Started Feb 08 12:50:26 PM UTC 25
Finished Feb 08 12:50:31 PM UTC 25
Peak memory 216456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033877643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3033877643
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.3209944599
Short name T480
Test name
Test status
Simulation time 149029244 ps
CPU time 6.21 seconds
Started Feb 08 12:50:24 PM UTC 25
Finished Feb 08 12:50:32 PM UTC 25
Peak memory 216528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209944599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3209944599
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.1605551635
Short name T385
Test name
Test status
Simulation time 129229638 ps
CPU time 3.34 seconds
Started Feb 08 12:50:26 PM UTC 25
Finished Feb 08 12:50:30 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605551635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1605551635
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.63653257
Short name T483
Test name
Test status
Simulation time 1997596648 ps
CPU time 6.4 seconds
Started Feb 08 12:50:31 PM UTC 25
Finished Feb 08 12:50:39 PM UTC 25
Peak memory 228584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63653257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_side
load_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.keymgr_sideload_protect.63653257
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.1918354516
Short name T478
Test name
Test status
Simulation time 77781502 ps
CPU time 3.87 seconds
Started Feb 08 12:50:24 PM UTC 25
Finished Feb 08 12:50:30 PM UTC 25
Peak memory 217972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918354516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.keymgr_smoke.1918354516
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.1160929970
Short name T282
Test name
Test status
Simulation time 505974171 ps
CPU time 7.24 seconds
Started Feb 08 12:50:28 PM UTC 25
Finished Feb 08 12:50:37 PM UTC 25
Peak memory 230800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160929970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1160929970
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.2492515635
Short name T134
Test name
Test status
Simulation time 80144268 ps
CPU time 3.39 seconds
Started Feb 08 12:50:32 PM UTC 25
Finished Feb 08 12:50:37 PM UTC 25
Peak memory 218308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492515635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2492515635
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.670188171
Short name T485
Test name
Test status
Simulation time 15412279 ps
CPU time 1.07 seconds
Started Feb 08 12:50:43 PM UTC 25
Finished Feb 08 12:50:46 PM UTC 25
Peak memory 213964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670188171 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.670188171
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.1778180294
Short name T486
Test name
Test status
Simulation time 67636350 ps
CPU time 4.17 seconds
Started Feb 08 12:50:41 PM UTC 25
Finished Feb 08 12:50:46 PM UTC 25
Peak memory 218620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778180294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 12.keymgr_custom_cm.1778180294
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.363977895
Short name T351
Test name
Test status
Simulation time 808894023 ps
CPU time 28.76 seconds
Started Feb 08 12:50:38 PM UTC 25
Finished Feb 08 12:51:09 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363977895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.363977895
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.1029607949
Short name T273
Test name
Test status
Simulation time 122357276 ps
CPU time 3.23 seconds
Started Feb 08 12:50:39 PM UTC 25
Finished Feb 08 12:50:44 PM UTC 25
Peak memory 224248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029607949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1029607949
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.2700265299
Short name T242
Test name
Test status
Simulation time 376554984 ps
CPU time 3.86 seconds
Started Feb 08 12:50:39 PM UTC 25
Finished Feb 08 12:50:45 PM UTC 25
Peak memory 226444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700265299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 12.keymgr_lc_disable.2700265299
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_random.1041614830
Short name T436
Test name
Test status
Simulation time 458035263 ps
CPU time 14.59 seconds
Started Feb 08 12:50:37 PM UTC 25
Finished Feb 08 12:50:53 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041614830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.keymgr_random.1041614830
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.1465170927
Short name T362
Test name
Test status
Simulation time 60543457 ps
CPU time 3.52 seconds
Started Feb 08 12:50:35 PM UTC 25
Finished Feb 08 12:50:39 PM UTC 25
Peak memory 218592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465170927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.keymgr_sideload.1465170927
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.629443382
Short name T337
Test name
Test status
Simulation time 785432301 ps
CPU time 6.73 seconds
Started Feb 08 12:50:36 PM UTC 25
Finished Feb 08 12:50:44 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629443382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.629443382
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.2942376738
Short name T411
Test name
Test status
Simulation time 67525435 ps
CPU time 2.38 seconds
Started Feb 08 12:50:35 PM UTC 25
Finished Feb 08 12:50:38 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942376738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2942376738
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.1013046553
Short name T484
Test name
Test status
Simulation time 93460226 ps
CPU time 3.56 seconds
Started Feb 08 12:50:36 PM UTC 25
Finished Feb 08 12:50:41 PM UTC 25
Peak memory 216400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013046553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1013046553
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.1744469830
Short name T325
Test name
Test status
Simulation time 475207799 ps
CPU time 6.01 seconds
Started Feb 08 12:50:41 PM UTC 25
Finished Feb 08 12:50:48 PM UTC 25
Peak memory 224824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744469830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1744469830
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.1603743888
Short name T482
Test name
Test status
Simulation time 391449663 ps
CPU time 3.74 seconds
Started Feb 08 12:50:34 PM UTC 25
Finished Feb 08 12:50:39 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603743888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.keymgr_smoke.1603743888
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.752323045
Short name T372
Test name
Test status
Simulation time 165984898 ps
CPU time 9.82 seconds
Started Feb 08 12:50:42 PM UTC 25
Finished Feb 08 12:50:53 PM UTC 25
Peak memory 226600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752323045 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.752323045
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.1019166824
Short name T495
Test name
Test status
Simulation time 479189410 ps
CPU time 19.34 seconds
Started Feb 08 12:50:39 PM UTC 25
Finished Feb 08 12:51:00 PM UTC 25
Peak memory 230644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019166824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1019166824
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.3981016532
Short name T118
Test name
Test status
Simulation time 132800193 ps
CPU time 2.54 seconds
Started Feb 08 12:50:41 PM UTC 25
Finished Feb 08 12:50:45 PM UTC 25
Peak memory 220768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981016532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3981016532
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.3019298997
Short name T493
Test name
Test status
Simulation time 8693501 ps
CPU time 0.99 seconds
Started Feb 08 12:50:54 PM UTC 25
Finished Feb 08 12:50:57 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019298997 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3019298997
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.1558101903
Short name T328
Test name
Test status
Simulation time 73467078 ps
CPU time 3.64 seconds
Started Feb 08 12:50:47 PM UTC 25
Finished Feb 08 12:50:52 PM UTC 25
Peak memory 224656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558101903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1558101903
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.1683898115
Short name T78
Test name
Test status
Simulation time 65834631 ps
CPU time 4.09 seconds
Started Feb 08 12:50:47 PM UTC 25
Finished Feb 08 12:50:52 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683898115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1683898115
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.298257379
Short name T315
Test name
Test status
Simulation time 119829837 ps
CPU time 4.42 seconds
Started Feb 08 12:50:52 PM UTC 25
Finished Feb 08 12:50:58 PM UTC 25
Peak memory 224336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298257379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.298257379
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_random.582703566
Short name T491
Test name
Test status
Simulation time 122344688 ps
CPU time 6.33 seconds
Started Feb 08 12:50:47 PM UTC 25
Finished Feb 08 12:50:54 PM UTC 25
Peak memory 218256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582703566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.keymgr_random.582703566
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.989778659
Short name T359
Test name
Test status
Simulation time 82484687 ps
CPU time 4.13 seconds
Started Feb 08 12:50:45 PM UTC 25
Finished Feb 08 12:50:51 PM UTC 25
Peak memory 216276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989778659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.keymgr_sideload.989778659
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.4190737757
Short name T349
Test name
Test status
Simulation time 70280723 ps
CPU time 4.85 seconds
Started Feb 08 12:50:46 PM UTC 25
Finished Feb 08 12:50:52 PM UTC 25
Peak memory 218336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190737757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.4190737757
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.1805283648
Short name T488
Test name
Test status
Simulation time 266503738 ps
CPU time 4.88 seconds
Started Feb 08 12:50:45 PM UTC 25
Finished Feb 08 12:50:52 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805283648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1805283648
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.2978828560
Short name T276
Test name
Test status
Simulation time 378767639 ps
CPU time 5.61 seconds
Started Feb 08 12:50:53 PM UTC 25
Finished Feb 08 12:51:00 PM UTC 25
Peak memory 220472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978828560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2978828560
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.1348563852
Short name T487
Test name
Test status
Simulation time 430588963 ps
CPU time 5.87 seconds
Started Feb 08 12:50:44 PM UTC 25
Finished Feb 08 12:50:52 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348563852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.keymgr_smoke.1348563852
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.2090537015
Short name T492
Test name
Test status
Simulation time 179920626 ps
CPU time 5.39 seconds
Started Feb 08 12:50:50 PM UTC 25
Finished Feb 08 12:50:57 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090537015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2090537015
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.3824659216
Short name T132
Test name
Test status
Simulation time 88209162 ps
CPU time 2.89 seconds
Started Feb 08 12:50:53 PM UTC 25
Finished Feb 08 12:50:58 PM UTC 25
Peak memory 220448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824659216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3824659216
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.4276260649
Short name T499
Test name
Test status
Simulation time 17707930 ps
CPU time 1.01 seconds
Started Feb 08 12:51:03 PM UTC 25
Finished Feb 08 12:51:06 PM UTC 25
Peak memory 214756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276260649 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4276260649
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.2477517371
Short name T427
Test name
Test status
Simulation time 124859537 ps
CPU time 3.21 seconds
Started Feb 08 12:50:57 PM UTC 25
Finished Feb 08 12:51:02 PM UTC 25
Peak memory 224396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477517371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2477517371
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.50414893
Short name T32
Test name
Test status
Simulation time 75533763 ps
CPU time 3.03 seconds
Started Feb 08 12:51:01 PM UTC 25
Finished Feb 08 12:51:05 PM UTC 25
Peak memory 218344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50414893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cust
om_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 14.keymgr_custom_cm.50414893
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.1846318019
Short name T271
Test name
Test status
Simulation time 133520557 ps
CPU time 4.25 seconds
Started Feb 08 12:50:58 PM UTC 25
Finished Feb 08 12:51:04 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846318019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1846318019
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.3606392275
Short name T319
Test name
Test status
Simulation time 756563844 ps
CPU time 3.7 seconds
Started Feb 08 12:51:00 PM UTC 25
Finished Feb 08 12:51:05 PM UTC 25
Peak memory 224528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606392275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3606392275
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.2668359403
Short name T501
Test name
Test status
Simulation time 517504396 ps
CPU time 7.74 seconds
Started Feb 08 12:50:58 PM UTC 25
Finished Feb 08 12:51:08 PM UTC 25
Peak memory 218368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668359403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 14.keymgr_lc_disable.2668359403
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_random.881777357
Short name T415
Test name
Test status
Simulation time 85873442 ps
CPU time 3.41 seconds
Started Feb 08 12:50:57 PM UTC 25
Finished Feb 08 12:51:02 PM UTC 25
Peak memory 232516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881777357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.keymgr_random.881777357
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.3416816800
Short name T364
Test name
Test status
Simulation time 104476223 ps
CPU time 3.66 seconds
Started Feb 08 12:50:55 PM UTC 25
Finished Feb 08 12:51:00 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416816800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.keymgr_sideload.3416816800
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.3163731597
Short name T494
Test name
Test status
Simulation time 160649674 ps
CPU time 2.9 seconds
Started Feb 08 12:50:56 PM UTC 25
Finished Feb 08 12:51:00 PM UTC 25
Peak memory 216456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163731597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3163731597
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.2408687554
Short name T496
Test name
Test status
Simulation time 585796383 ps
CPU time 3.42 seconds
Started Feb 08 12:50:56 PM UTC 25
Finished Feb 08 12:51:00 PM UTC 25
Peak memory 218344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408687554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2408687554
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.2214371240
Short name T505
Test name
Test status
Simulation time 309402306 ps
CPU time 12.74 seconds
Started Feb 08 12:50:57 PM UTC 25
Finished Feb 08 12:51:12 PM UTC 25
Peak memory 216168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214371240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2214371240
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.4003740951
Short name T498
Test name
Test status
Simulation time 125980253 ps
CPU time 3.14 seconds
Started Feb 08 12:51:01 PM UTC 25
Finished Feb 08 12:51:06 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003740951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4003740951
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.296765467
Short name T512
Test name
Test status
Simulation time 1647599949 ps
CPU time 28.03 seconds
Started Feb 08 12:50:55 PM UTC 25
Finished Feb 08 12:51:24 PM UTC 25
Peak memory 218332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296765467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.keymgr_smoke.296765467
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.2329607931
Short name T248
Test name
Test status
Simulation time 12633739689 ps
CPU time 124.59 seconds
Started Feb 08 12:51:01 PM UTC 25
Finished Feb 08 12:53:08 PM UTC 25
Peak memory 228624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329607931 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2329607931
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all_with_rand_reset.780934023
Short name T129
Test name
Test status
Simulation time 412885385 ps
CPU time 17.23 seconds
Started Feb 08 12:51:01 PM UTC 25
Finished Feb 08 12:51:20 PM UTC 25
Peak memory 230668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=780934023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_
reset.780934023
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.3298735316
Short name T497
Test name
Test status
Simulation time 60458951 ps
CPU time 1.94 seconds
Started Feb 08 12:51:01 PM UTC 25
Finished Feb 08 12:51:04 PM UTC 25
Peak memory 218056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298735316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3298735316
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.689173393
Short name T506
Test name
Test status
Simulation time 44846063 ps
CPU time 1.29 seconds
Started Feb 08 12:51:11 PM UTC 25
Finished Feb 08 12:51:14 PM UTC 25
Peak memory 214752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689173393 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.689173393
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.3575221851
Short name T269
Test name
Test status
Simulation time 43081031 ps
CPU time 3.78 seconds
Started Feb 08 12:51:06 PM UTC 25
Finished Feb 08 12:51:11 PM UTC 25
Peak memory 226436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575221851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3575221851
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.1026717813
Short name T394
Test name
Test status
Simulation time 24359449 ps
CPU time 2.58 seconds
Started Feb 08 12:51:08 PM UTC 25
Finished Feb 08 12:51:12 PM UTC 25
Peak memory 224464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026717813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1026717813
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_random.50983203
Short name T384
Test name
Test status
Simulation time 45614089 ps
CPU time 3.94 seconds
Started Feb 08 12:51:06 PM UTC 25
Finished Feb 08 12:51:11 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50983203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_rand
om_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.keymgr_random.50983203
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.3595530454
Short name T534
Test name
Test status
Simulation time 6171279602 ps
CPU time 49.37 seconds
Started Feb 08 12:51:04 PM UTC 25
Finished Feb 08 12:51:56 PM UTC 25
Peak memory 218316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595530454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.keymgr_sideload.3595530454
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.3358555117
Short name T502
Test name
Test status
Simulation time 84941857 ps
CPU time 3.02 seconds
Started Feb 08 12:51:06 PM UTC 25
Finished Feb 08 12:51:10 PM UTC 25
Peak memory 218504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358555117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3358555117
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.4246614222
Short name T503
Test name
Test status
Simulation time 102619551 ps
CPU time 3.05 seconds
Started Feb 08 12:51:06 PM UTC 25
Finished Feb 08 12:51:10 PM UTC 25
Peak memory 216188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246614222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4246614222
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.1452695697
Short name T504
Test name
Test status
Simulation time 439354258 ps
CPU time 3.79 seconds
Started Feb 08 12:51:06 PM UTC 25
Finished Feb 08 12:51:11 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452695697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1452695697
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.604593421
Short name T430
Test name
Test status
Simulation time 121861305 ps
CPU time 2.84 seconds
Started Feb 08 12:51:09 PM UTC 25
Finished Feb 08 12:51:13 PM UTC 25
Peak memory 218324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604593421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.604593421
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.1209550360
Short name T500
Test name
Test status
Simulation time 127249721 ps
CPU time 2.81 seconds
Started Feb 08 12:51:03 PM UTC 25
Finished Feb 08 12:51:07 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209550360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.keymgr_smoke.1209550360
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.1539327447
Short name T283
Test name
Test status
Simulation time 1397246512 ps
CPU time 30.4 seconds
Started Feb 08 12:51:11 PM UTC 25
Finished Feb 08 12:51:43 PM UTC 25
Peak memory 230608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539327447 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1539327447
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all_with_rand_reset.98640442
Short name T79
Test name
Test status
Simulation time 483221085 ps
CPU time 9.96 seconds
Started Feb 08 12:51:11 PM UTC 25
Finished Feb 08 12:51:23 PM UTC 25
Peak memory 231340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=98640442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_r
eset.98640442
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.3813931062
Short name T347
Test name
Test status
Simulation time 311389338 ps
CPU time 6.68 seconds
Started Feb 08 12:51:07 PM UTC 25
Finished Feb 08 12:51:15 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813931062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3813931062
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.2904070535
Short name T422
Test name
Test status
Simulation time 270583298 ps
CPU time 2.71 seconds
Started Feb 08 12:51:10 PM UTC 25
Finished Feb 08 12:51:14 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904070535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2904070535
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.3037399917
Short name T510
Test name
Test status
Simulation time 23482466 ps
CPU time 0.94 seconds
Started Feb 08 12:51:19 PM UTC 25
Finished Feb 08 12:51:22 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037399917 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3037399917
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.2048012265
Short name T284
Test name
Test status
Simulation time 48265370 ps
CPU time 4.78 seconds
Started Feb 08 12:51:14 PM UTC 25
Finished Feb 08 12:51:20 PM UTC 25
Peak memory 226804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048012265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2048012265
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.1458716772
Short name T277
Test name
Test status
Simulation time 88900019 ps
CPU time 3.45 seconds
Started Feb 08 12:51:14 PM UTC 25
Finished Feb 08 12:51:19 PM UTC 25
Peak memory 224404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458716772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1458716772
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.3390167326
Short name T316
Test name
Test status
Simulation time 250489767 ps
CPU time 3.79 seconds
Started Feb 08 12:51:15 PM UTC 25
Finished Feb 08 12:51:20 PM UTC 25
Peak memory 226680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390167326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3390167326
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.3716859392
Short name T73
Test name
Test status
Simulation time 130445214 ps
CPU time 6.24 seconds
Started Feb 08 12:51:14 PM UTC 25
Finished Feb 08 12:51:21 PM UTC 25
Peak memory 218620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716859392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 16.keymgr_lc_disable.3716859392
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_random.3937544455
Short name T516
Test name
Test status
Simulation time 1033409842 ps
CPU time 12.77 seconds
Started Feb 08 12:51:13 PM UTC 25
Finished Feb 08 12:51:27 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937544455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.keymgr_random.3937544455
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.2975055705
Short name T509
Test name
Test status
Simulation time 237332255 ps
CPU time 4.71 seconds
Started Feb 08 12:51:11 PM UTC 25
Finished Feb 08 12:51:18 PM UTC 25
Peak memory 216340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975055705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.keymgr_sideload.2975055705
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.1144323967
Short name T541
Test name
Test status
Simulation time 9043737819 ps
CPU time 49.47 seconds
Started Feb 08 12:51:13 PM UTC 25
Finished Feb 08 12:52:04 PM UTC 25
Peak memory 218252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144323967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1144323967
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.1176502151
Short name T508
Test name
Test status
Simulation time 82942523 ps
CPU time 2.97 seconds
Started Feb 08 12:51:13 PM UTC 25
Finished Feb 08 12:51:17 PM UTC 25
Peak memory 218272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176502151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1176502151
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.3620395133
Short name T545
Test name
Test status
Simulation time 16958485367 ps
CPU time 53.44 seconds
Started Feb 08 12:51:13 PM UTC 25
Finished Feb 08 12:52:08 PM UTC 25
Peak memory 218576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620395133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3620395133
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.686675210
Short name T270
Test name
Test status
Simulation time 1450402071 ps
CPU time 15.9 seconds
Started Feb 08 12:51:17 PM UTC 25
Finished Feb 08 12:51:35 PM UTC 25
Peak memory 224468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686675210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.686675210
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.1819785698
Short name T507
Test name
Test status
Simulation time 108469242 ps
CPU time 3.41 seconds
Started Feb 08 12:51:11 PM UTC 25
Finished Feb 08 12:51:16 PM UTC 25
Peak memory 216528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819785698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.keymgr_smoke.1819785698
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.1091747153
Short name T246
Test name
Test status
Simulation time 3630375781 ps
CPU time 21.52 seconds
Started Feb 08 12:51:17 PM UTC 25
Finished Feb 08 12:51:40 PM UTC 25
Peak memory 232608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091747153 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1091747153
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all_with_rand_reset.2157164352
Short name T131
Test name
Test status
Simulation time 344936391 ps
CPU time 17.52 seconds
Started Feb 08 12:51:18 PM UTC 25
Finished Feb 08 12:51:37 PM UTC 25
Peak memory 232756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2157164352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand
_reset.2157164352
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.1604095486
Short name T514
Test name
Test status
Simulation time 762342922 ps
CPU time 9.81 seconds
Started Feb 08 12:51:15 PM UTC 25
Finished Feb 08 12:51:26 PM UTC 25
Peak memory 218224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604095486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1604095486
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.3139124189
Short name T130
Test name
Test status
Simulation time 65826833 ps
CPU time 2.47 seconds
Started Feb 08 12:51:17 PM UTC 25
Finished Feb 08 12:51:21 PM UTC 25
Peak memory 218160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139124189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3139124189
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.327658281
Short name T521
Test name
Test status
Simulation time 15997071 ps
CPU time 1.35 seconds
Started Feb 08 12:51:30 PM UTC 25
Finished Feb 08 12:51:32 PM UTC 25
Peak memory 214144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327658281 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.327658281
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.2123498699
Short name T419
Test name
Test status
Simulation time 144076410 ps
CPU time 2.8 seconds
Started Feb 08 12:51:23 PM UTC 25
Finished Feb 08 12:51:27 PM UTC 25
Peak memory 224464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123498699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2123498699
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.3881027525
Short name T285
Test name
Test status
Simulation time 3122463953 ps
CPU time 7.55 seconds
Started Feb 08 12:51:24 PM UTC 25
Finished Feb 08 12:51:33 PM UTC 25
Peak memory 228700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881027525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3881027525
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.1284553554
Short name T522
Test name
Test status
Simulation time 105801774 ps
CPU time 6.2 seconds
Started Feb 08 12:51:26 PM UTC 25
Finished Feb 08 12:51:34 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284553554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1284553554
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.1176882045
Short name T397
Test name
Test status
Simulation time 148476252 ps
CPU time 2.96 seconds
Started Feb 08 12:51:27 PM UTC 25
Finished Feb 08 12:51:32 PM UTC 25
Peak memory 224408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176882045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1176882045
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.556081493
Short name T369
Test name
Test status
Simulation time 365741331 ps
CPU time 3.07 seconds
Started Feb 08 12:51:24 PM UTC 25
Finished Feb 08 12:51:28 PM UTC 25
Peak memory 218524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556081493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 17.keymgr_lc_disable.556081493
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_random.824527399
Short name T388
Test name
Test status
Simulation time 366096036 ps
CPU time 4.46 seconds
Started Feb 08 12:51:22 PM UTC 25
Finished Feb 08 12:51:28 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824527399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.keymgr_random.824527399
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.2105569584
Short name T513
Test name
Test status
Simulation time 383451496 ps
CPU time 2.88 seconds
Started Feb 08 12:51:21 PM UTC 25
Finished Feb 08 12:51:25 PM UTC 25
Peak memory 216176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105569584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.keymgr_sideload.2105569584
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.3062979956
Short name T519
Test name
Test status
Simulation time 947754626 ps
CPU time 8.03 seconds
Started Feb 08 12:51:21 PM UTC 25
Finished Feb 08 12:51:30 PM UTC 25
Peak memory 216436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062979956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3062979956
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.2952162953
Short name T517
Test name
Test status
Simulation time 437005169 ps
CPU time 5.29 seconds
Started Feb 08 12:51:21 PM UTC 25
Finished Feb 08 12:51:27 PM UTC 25
Peak memory 216196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952162953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2952162953
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.2564596424
Short name T518
Test name
Test status
Simulation time 163563346 ps
CPU time 6.39 seconds
Started Feb 08 12:51:22 PM UTC 25
Finished Feb 08 12:51:30 PM UTC 25
Peak memory 216164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564596424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2564596424
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.2999518683
Short name T323
Test name
Test status
Simulation time 119223720 ps
CPU time 5.4 seconds
Started Feb 08 12:51:28 PM UTC 25
Finished Feb 08 12:51:36 PM UTC 25
Peak memory 226196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999518683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2999518683
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.3252850604
Short name T515
Test name
Test status
Simulation time 95598289 ps
CPU time 4.3 seconds
Started Feb 08 12:51:21 PM UTC 25
Finished Feb 08 12:51:26 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252850604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.keymgr_smoke.3252850604
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.2505348955
Short name T313
Test name
Test status
Simulation time 399860707 ps
CPU time 16.22 seconds
Started Feb 08 12:51:28 PM UTC 25
Finished Feb 08 12:51:47 PM UTC 25
Peak memory 226440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505348955 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2505348955
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all_with_rand_reset.2023772110
Short name T133
Test name
Test status
Simulation time 530962163 ps
CPU time 10.29 seconds
Started Feb 08 12:51:29 PM UTC 25
Finished Feb 08 12:51:41 PM UTC 25
Peak memory 230936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2023772110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand
_reset.2023772110
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.1935148682
Short name T524
Test name
Test status
Simulation time 880386736 ps
CPU time 8.3 seconds
Started Feb 08 12:51:25 PM UTC 25
Finished Feb 08 12:51:35 PM UTC 25
Peak memory 224388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935148682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1935148682
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.3752634736
Short name T220
Test name
Test status
Simulation time 54904647 ps
CPU time 1.47 seconds
Started Feb 08 12:51:28 PM UTC 25
Finished Feb 08 12:51:32 PM UTC 25
Peak memory 216804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752634736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3752634736
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.3629518972
Short name T529
Test name
Test status
Simulation time 11062369 ps
CPU time 1.14 seconds
Started Feb 08 12:51:41 PM UTC 25
Finished Feb 08 12:51:44 PM UTC 25
Peak memory 214632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629518972 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3629518972
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.1840291956
Short name T536
Test name
Test status
Simulation time 2673077753 ps
CPU time 20.72 seconds
Started Feb 08 12:51:35 PM UTC 25
Finished Feb 08 12:51:57 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840291956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1840291956
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.301894005
Short name T97
Test name
Test status
Simulation time 759764821 ps
CPU time 6.27 seconds
Started Feb 08 12:51:36 PM UTC 25
Finished Feb 08 12:51:44 PM UTC 25
Peak memory 218564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301894005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hws
w_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.301894005
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.1473796033
Short name T374
Test name
Test status
Simulation time 45081274 ps
CPU time 3.12 seconds
Started Feb 08 12:51:36 PM UTC 25
Finished Feb 08 12:51:41 PM UTC 25
Peak memory 226640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473796033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1473796033
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.2721957991
Short name T528
Test name
Test status
Simulation time 429501783 ps
CPU time 6.72 seconds
Started Feb 08 12:51:35 PM UTC 25
Finished Feb 08 12:51:43 PM UTC 25
Peak memory 226520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721957991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 18.keymgr_lc_disable.2721957991
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_random.4028179757
Short name T382
Test name
Test status
Simulation time 1233981392 ps
CPU time 5.67 seconds
Started Feb 08 12:51:33 PM UTC 25
Finished Feb 08 12:51:40 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028179757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.keymgr_random.4028179757
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.3855048063
Short name T400
Test name
Test status
Simulation time 848174235 ps
CPU time 7.88 seconds
Started Feb 08 12:51:32 PM UTC 25
Finished Feb 08 12:51:41 PM UTC 25
Peak memory 218516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855048063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.keymgr_sideload.3855048063
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.4177750593
Short name T525
Test name
Test status
Simulation time 48707560 ps
CPU time 2.51 seconds
Started Feb 08 12:51:33 PM UTC 25
Finished Feb 08 12:51:37 PM UTC 25
Peak memory 216236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177750593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4177750593
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.487045400
Short name T526
Test name
Test status
Simulation time 105362691 ps
CPU time 4.86 seconds
Started Feb 08 12:51:33 PM UTC 25
Finished Feb 08 12:51:39 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487045400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.487045400
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.2697332927
Short name T527
Test name
Test status
Simulation time 66098017 ps
CPU time 3.95 seconds
Started Feb 08 12:51:38 PM UTC 25
Finished Feb 08 12:51:43 PM UTC 25
Peak memory 218324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697332927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2697332927
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.3357757316
Short name T523
Test name
Test status
Simulation time 63532516 ps
CPU time 2.79 seconds
Started Feb 08 12:51:31 PM UTC 25
Finished Feb 08 12:51:35 PM UTC 25
Peak memory 218268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357757316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.keymgr_smoke.3357757316
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.3382590013
Short name T329
Test name
Test status
Simulation time 364338375 ps
CPU time 19.63 seconds
Started Feb 08 12:51:39 PM UTC 25
Finished Feb 08 12:52:00 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382590013 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3382590013
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.1801309833
Short name T402
Test name
Test status
Simulation time 2494451720 ps
CPU time 19.36 seconds
Started Feb 08 12:51:36 PM UTC 25
Finished Feb 08 12:51:57 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801309833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1801309833
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.3463737218
Short name T535
Test name
Test status
Simulation time 1335941069 ps
CPU time 16.47 seconds
Started Feb 08 12:51:39 PM UTC 25
Finished Feb 08 12:51:57 PM UTC 25
Peak memory 220496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463737218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3463737218
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.371290258
Short name T533
Test name
Test status
Simulation time 29929536 ps
CPU time 0.96 seconds
Started Feb 08 12:51:53 PM UTC 25
Finished Feb 08 12:51:55 PM UTC 25
Peak memory 213964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371290258 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.371290258
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.1003000344
Short name T35
Test name
Test status
Simulation time 133584453 ps
CPU time 2.18 seconds
Started Feb 08 12:51:47 PM UTC 25
Finished Feb 08 12:51:51 PM UTC 25
Peak memory 232904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003000344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 19.keymgr_custom_cm.1003000344
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.2692220511
Short name T548
Test name
Test status
Simulation time 991319015 ps
CPU time 24.07 seconds
Started Feb 08 12:51:45 PM UTC 25
Finished Feb 08 12:52:11 PM UTC 25
Peak memory 218224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692220511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2692220511
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.2281580695
Short name T100
Test name
Test status
Simulation time 1557118287 ps
CPU time 10.03 seconds
Started Feb 08 12:51:46 PM UTC 25
Finished Feb 08 12:51:57 PM UTC 25
Peak memory 224656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281580695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2281580695
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.1797905799
Short name T530
Test name
Test status
Simulation time 82349705 ps
CPU time 3.62 seconds
Started Feb 08 12:51:46 PM UTC 25
Finished Feb 08 12:51:51 PM UTC 25
Peak memory 224336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797905799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1797905799
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_random.3163284952
Short name T520
Test name
Test status
Simulation time 95062748 ps
CPU time 3.15 seconds
Started Feb 08 12:51:44 PM UTC 25
Finished Feb 08 12:51:48 PM UTC 25
Peak memory 228460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163284952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.keymgr_random.3163284952
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.3043468444
Short name T268
Test name
Test status
Simulation time 34357472 ps
CPU time 2.62 seconds
Started Feb 08 12:51:41 PM UTC 25
Finished Feb 08 12:51:45 PM UTC 25
Peak memory 216464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043468444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.keymgr_sideload.3043468444
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.1508653970
Short name T531
Test name
Test status
Simulation time 697816591 ps
CPU time 8.93 seconds
Started Feb 08 12:51:41 PM UTC 25
Finished Feb 08 12:51:52 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508653970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1508653970
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.1381586171
Short name T539
Test name
Test status
Simulation time 572689164 ps
CPU time 19.13 seconds
Started Feb 08 12:51:41 PM UTC 25
Finished Feb 08 12:52:02 PM UTC 25
Peak memory 218500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381586171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1381586171
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.921916632
Short name T537
Test name
Test status
Simulation time 350518667 ps
CPU time 13.45 seconds
Started Feb 08 12:51:43 PM UTC 25
Finished Feb 08 12:51:58 PM UTC 25
Peak memory 218316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921916632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.921916632
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.2421862222
Short name T389
Test name
Test status
Simulation time 198044316 ps
CPU time 6.6 seconds
Started Feb 08 12:51:49 PM UTC 25
Finished Feb 08 12:51:57 PM UTC 25
Peak memory 218172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421862222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2421862222
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.231367099
Short name T511
Test name
Test status
Simulation time 545656724 ps
CPU time 5.75 seconds
Started Feb 08 12:51:41 PM UTC 25
Finished Feb 08 12:51:49 PM UTC 25
Peak memory 216288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231367099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.keymgr_smoke.231367099
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.1338338329
Short name T243
Test name
Test status
Simulation time 1957976908 ps
CPU time 40.93 seconds
Started Feb 08 12:51:51 PM UTC 25
Finished Feb 08 12:52:34 PM UTC 25
Peak memory 226768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338338329 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1338338329
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.781500819
Short name T414
Test name
Test status
Simulation time 264247702 ps
CPU time 9.67 seconds
Started Feb 08 12:51:45 PM UTC 25
Finished Feb 08 12:51:56 PM UTC 25
Peak memory 228560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781500819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_
invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.781500819
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.1439489864
Short name T106
Test name
Test status
Simulation time 17458662 ps
CPU time 0.95 seconds
Started Feb 08 12:48:18 PM UTC 25
Finished Feb 08 12:48:20 PM UTC 25
Peak memory 214760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439489864 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1439489864
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.1509646860
Short name T51
Test name
Test status
Simulation time 51274150 ps
CPU time 2.66 seconds
Started Feb 08 12:48:07 PM UTC 25
Finished Feb 08 12:48:11 PM UTC 25
Peak memory 218328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509646860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1509646860
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.1566840363
Short name T107
Test name
Test status
Simulation time 354707808 ps
CPU time 6.04 seconds
Started Feb 08 12:48:11 PM UTC 25
Finished Feb 08 12:48:18 PM UTC 25
Peak memory 226456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566840363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1566840363
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.3656832875
Short name T49
Test name
Test status
Simulation time 1099396722 ps
CPU time 4.78 seconds
Started Feb 08 12:48:09 PM UTC 25
Finished Feb 08 12:48:16 PM UTC 25
Peak memory 230544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656832875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 2.keymgr_lc_disable.3656832875
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.330053670
Short name T13
Test name
Test status
Simulation time 492801931 ps
CPU time 8.49 seconds
Started Feb 08 12:48:18 PM UTC 25
Finished Feb 08 12:48:28 PM UTC 25
Peak memory 254484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330053670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.330053670
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.1861759409
Short name T230
Test name
Test status
Simulation time 36117188 ps
CPU time 2.42 seconds
Started Feb 08 12:48:01 PM UTC 25
Finished Feb 08 12:48:05 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861759409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.keymgr_sideload.1861759409
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.1908062742
Short name T231
Test name
Test status
Simulation time 210884069 ps
CPU time 3.56 seconds
Started Feb 08 12:48:05 PM UTC 25
Finished Feb 08 12:48:10 PM UTC 25
Peak memory 218420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908062742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1908062742
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.25572478
Short name T236
Test name
Test status
Simulation time 47021517 ps
CPU time 3.41 seconds
Started Feb 08 12:48:05 PM UTC 25
Finished Feb 08 12:48:10 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25572478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.25572478
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.219721118
Short name T227
Test name
Test status
Simulation time 580229362 ps
CPU time 3.95 seconds
Started Feb 08 12:48:12 PM UTC 25
Finished Feb 08 12:48:17 PM UTC 25
Peak memory 218256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219721118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.219721118
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.374782058
Short name T229
Test name
Test status
Simulation time 114249642 ps
CPU time 4.24 seconds
Started Feb 08 12:48:01 PM UTC 25
Finished Feb 08 12:48:06 PM UTC 25
Peak memory 218596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374782058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.keymgr_smoke.374782058
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.2395010220
Short name T224
Test name
Test status
Simulation time 297127637 ps
CPU time 3.81 seconds
Started Feb 08 12:48:10 PM UTC 25
Finished Feb 08 12:48:16 PM UTC 25
Peak memory 224668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395010220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2395010220
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.4249195423
Short name T40
Test name
Test status
Simulation time 130244273 ps
CPU time 4.55 seconds
Started Feb 08 12:48:16 PM UTC 25
Finished Feb 08 12:48:22 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249195423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.4249195423
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.2835926832
Short name T542
Test name
Test status
Simulation time 14728104 ps
CPU time 1.26 seconds
Started Feb 08 12:52:02 PM UTC 25
Finished Feb 08 12:52:04 PM UTC 25
Peak memory 214068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835926832 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2835926832
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.3851400443
Short name T373
Test name
Test status
Simulation time 1010398233 ps
CPU time 5.53 seconds
Started Feb 08 12:51:58 PM UTC 25
Finished Feb 08 12:52:05 PM UTC 25
Peak memory 224432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851400443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3851400443
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.244797193
Short name T258
Test name
Test status
Simulation time 47994259 ps
CPU time 3.13 seconds
Started Feb 08 12:51:58 PM UTC 25
Finished Feb 08 12:52:03 PM UTC 25
Peak memory 230776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244797193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hws
w_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.244797193
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.2807551965
Short name T355
Test name
Test status
Simulation time 216232364 ps
CPU time 6.72 seconds
Started Feb 08 12:51:58 PM UTC 25
Finished Feb 08 12:52:06 PM UTC 25
Peak memory 232756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807551965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2807551965
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_random.4061530322
Short name T565
Test name
Test status
Simulation time 5140887581 ps
CPU time 30.2 seconds
Started Feb 08 12:51:57 PM UTC 25
Finished Feb 08 12:52:29 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061530322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.keymgr_random.4061530322
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.3482617544
Short name T403
Test name
Test status
Simulation time 358531083 ps
CPU time 8.47 seconds
Started Feb 08 12:51:53 PM UTC 25
Finished Feb 08 12:52:03 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482617544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.keymgr_sideload.3482617544
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.306286980
Short name T404
Test name
Test status
Simulation time 22334232 ps
CPU time 2.6 seconds
Started Feb 08 12:51:54 PM UTC 25
Finished Feb 08 12:51:58 PM UTC 25
Peak memory 216316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306286980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.306286980
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.1596045812
Short name T538
Test name
Test status
Simulation time 1017854809 ps
CPU time 3.99 seconds
Started Feb 08 12:51:53 PM UTC 25
Finished Feb 08 12:51:58 PM UTC 25
Peak memory 218508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596045812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1596045812
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.2128074778
Short name T556
Test name
Test status
Simulation time 1657968222 ps
CPU time 21.98 seconds
Started Feb 08 12:51:56 PM UTC 25
Finished Feb 08 12:52:19 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128074778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2128074778
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.715777386
Short name T295
Test name
Test status
Simulation time 580199720 ps
CPU time 3.48 seconds
Started Feb 08 12:51:58 PM UTC 25
Finished Feb 08 12:52:03 PM UTC 25
Peak memory 218580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715777386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.715777386
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.4182898261
Short name T440
Test name
Test status
Simulation time 386009463 ps
CPU time 5.71 seconds
Started Feb 08 12:51:53 PM UTC 25
Finished Feb 08 12:52:00 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182898261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.keymgr_smoke.4182898261
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.676411483
Short name T550
Test name
Test status
Simulation time 219074986 ps
CPU time 10.83 seconds
Started Feb 08 12:52:01 PM UTC 25
Finished Feb 08 12:52:13 PM UTC 25
Peak memory 231048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=676411483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_
reset.676411483
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.718441155
Short name T540
Test name
Test status
Simulation time 48076694 ps
CPU time 3.77 seconds
Started Feb 08 12:51:58 PM UTC 25
Finished Feb 08 12:52:03 PM UTC 25
Peak memory 216436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718441155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_
invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.718441155
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.3429061909
Short name T169
Test name
Test status
Simulation time 228060913 ps
CPU time 2.58 seconds
Started Feb 08 12:51:59 PM UTC 25
Finished Feb 08 12:52:04 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429061909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3429061909
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.1098401321
Short name T553
Test name
Test status
Simulation time 36939448 ps
CPU time 1.09 seconds
Started Feb 08 12:52:11 PM UTC 25
Finished Feb 08 12:52:13 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098401321 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1098401321
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.663776974
Short name T264
Test name
Test status
Simulation time 146127097 ps
CPU time 3.52 seconds
Started Feb 08 12:52:05 PM UTC 25
Finished Feb 08 12:52:10 PM UTC 25
Peak memory 224584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663776974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.663776974
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.1545962218
Short name T549
Test name
Test status
Simulation time 64786870 ps
CPU time 3.02 seconds
Started Feb 08 12:52:08 PM UTC 25
Finished Feb 08 12:52:12 PM UTC 25
Peak memory 230500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545962218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 21.keymgr_custom_cm.1545962218
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.1899915163
Short name T572
Test name
Test status
Simulation time 899353325 ps
CPU time 26.65 seconds
Started Feb 08 12:52:05 PM UTC 25
Finished Feb 08 12:52:34 PM UTC 25
Peak memory 218260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899915163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1899915163
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.3424635938
Short name T259
Test name
Test status
Simulation time 736750753 ps
CPU time 5.86 seconds
Started Feb 08 12:52:06 PM UTC 25
Finished Feb 08 12:52:14 PM UTC 25
Peak memory 218244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424635938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3424635938
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.225679286
Short name T292
Test name
Test status
Simulation time 49766881 ps
CPU time 3.24 seconds
Started Feb 08 12:52:08 PM UTC 25
Finished Feb 08 12:52:12 PM UTC 25
Peak memory 232440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225679286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.225679286
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.1115387559
Short name T333
Test name
Test status
Simulation time 157002630 ps
CPU time 6.46 seconds
Started Feb 08 12:52:05 PM UTC 25
Finished Feb 08 12:52:13 PM UTC 25
Peak memory 220304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115387559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 21.keymgr_lc_disable.1115387559
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_random.3607106842
Short name T366
Test name
Test status
Simulation time 911365092 ps
CPU time 8.46 seconds
Started Feb 08 12:52:05 PM UTC 25
Finished Feb 08 12:52:15 PM UTC 25
Peak memory 228568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607106842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.keymgr_random.3607106842
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.2134725831
Short name T577
Test name
Test status
Simulation time 1089682725 ps
CPU time 31.04 seconds
Started Feb 08 12:52:04 PM UTC 25
Finished Feb 08 12:52:37 PM UTC 25
Peak memory 216276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134725831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.keymgr_sideload.2134725831
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.1141434092
Short name T547
Test name
Test status
Simulation time 134817875 ps
CPU time 3.33 seconds
Started Feb 08 12:52:04 PM UTC 25
Finished Feb 08 12:52:09 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141434092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1141434092
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.1153752113
Short name T546
Test name
Test status
Simulation time 135777026 ps
CPU time 3.06 seconds
Started Feb 08 12:52:04 PM UTC 25
Finished Feb 08 12:52:08 PM UTC 25
Peak memory 218628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153752113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1153752113
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.512335789
Short name T567
Test name
Test status
Simulation time 901476106 ps
CPU time 23.78 seconds
Started Feb 08 12:52:04 PM UTC 25
Finished Feb 08 12:52:29 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512335789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.512335789
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.2957433975
Short name T551
Test name
Test status
Simulation time 320593238 ps
CPU time 2.81 seconds
Started Feb 08 12:52:09 PM UTC 25
Finished Feb 08 12:52:13 PM UTC 25
Peak memory 226516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957433975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2957433975
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.3184862807
Short name T543
Test name
Test status
Simulation time 104652712 ps
CPU time 3.17 seconds
Started Feb 08 12:52:03 PM UTC 25
Finished Feb 08 12:52:07 PM UTC 25
Peak memory 216208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184862807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.keymgr_smoke.3184862807
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.922521974
Short name T80
Test name
Test status
Simulation time 1871001944 ps
CPU time 21.24 seconds
Started Feb 08 12:52:09 PM UTC 25
Finished Feb 08 12:52:32 PM UTC 25
Peak memory 226444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922521974 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.922521974
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all_with_rand_reset.4135517868
Short name T157
Test name
Test status
Simulation time 361575127 ps
CPU time 19 seconds
Started Feb 08 12:52:10 PM UTC 25
Finished Feb 08 12:52:30 PM UTC 25
Peak memory 231808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=4135517868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand
_reset.4135517868
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.2734847541
Short name T554
Test name
Test status
Simulation time 82396683 ps
CPU time 5.51 seconds
Started Feb 08 12:52:06 PM UTC 25
Finished Feb 08 12:52:13 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734847541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2734847541
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.1309413187
Short name T552
Test name
Test status
Simulation time 94859693 ps
CPU time 3.15 seconds
Started Feb 08 12:52:09 PM UTC 25
Finished Feb 08 12:52:13 PM UTC 25
Peak memory 220432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309413187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1309413187
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.2351000551
Short name T562
Test name
Test status
Simulation time 8540888 ps
CPU time 0.9 seconds
Started Feb 08 12:52:21 PM UTC 25
Finished Feb 08 12:52:23 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351000551 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2351000551
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.479517945
Short name T557
Test name
Test status
Simulation time 220593992 ps
CPU time 3.68 seconds
Started Feb 08 12:52:14 PM UTC 25
Finished Feb 08 12:52:20 PM UTC 25
Peak memory 228588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479517945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.479517945
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.580675542
Short name T103
Test name
Test status
Simulation time 273188116 ps
CPU time 7.08 seconds
Started Feb 08 12:52:15 PM UTC 25
Finished Feb 08 12:52:23 PM UTC 25
Peak memory 232624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580675542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hws
w_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.580675542
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.222178544
Short name T356
Test name
Test status
Simulation time 37744783 ps
CPU time 3.38 seconds
Started Feb 08 12:52:16 PM UTC 25
Finished Feb 08 12:52:21 PM UTC 25
Peak memory 231836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222178544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.222178544
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.436570150
Short name T559
Test name
Test status
Simulation time 198978216 ps
CPU time 4.66 seconds
Started Feb 08 12:52:14 PM UTC 25
Finished Feb 08 12:52:21 PM UTC 25
Peak memory 232556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436570150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 22.keymgr_lc_disable.436570150
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_random.1148106765
Short name T558
Test name
Test status
Simulation time 102440350 ps
CPU time 4.26 seconds
Started Feb 08 12:52:14 PM UTC 25
Finished Feb 08 12:52:20 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148106765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.keymgr_random.1148106765
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.3321240679
Short name T334
Test name
Test status
Simulation time 105675668 ps
CPU time 5.05 seconds
Started Feb 08 12:52:12 PM UTC 25
Finished Feb 08 12:52:18 PM UTC 25
Peak memory 218352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321240679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.keymgr_sideload.3321240679
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.4285270885
Short name T560
Test name
Test status
Simulation time 180210126 ps
CPU time 7.04 seconds
Started Feb 08 12:52:13 PM UTC 25
Finished Feb 08 12:52:22 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285270885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.4285270885
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.4261537823
Short name T561
Test name
Test status
Simulation time 295430499 ps
CPU time 7.33 seconds
Started Feb 08 12:52:13 PM UTC 25
Finished Feb 08 12:52:22 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261537823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.4261537823
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.4180190999
Short name T604
Test name
Test status
Simulation time 4066683782 ps
CPU time 42.32 seconds
Started Feb 08 12:52:13 PM UTC 25
Finished Feb 08 12:52:57 PM UTC 25
Peak memory 218576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180190999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4180190999
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.4167596153
Short name T563
Test name
Test status
Simulation time 459211391 ps
CPU time 2.56 seconds
Started Feb 08 12:52:20 PM UTC 25
Finished Feb 08 12:52:24 PM UTC 25
Peak memory 226440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167596153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.4167596153
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.347555717
Short name T555
Test name
Test status
Simulation time 765195533 ps
CPU time 5.59 seconds
Started Feb 08 12:52:11 PM UTC 25
Finished Feb 08 12:52:18 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347555717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 22.keymgr_smoke.347555717
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.1530528208
Short name T250
Test name
Test status
Simulation time 400356217 ps
CPU time 12.71 seconds
Started Feb 08 12:52:21 PM UTC 25
Finished Feb 08 12:52:35 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530528208 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1530528208
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all_with_rand_reset.2766092010
Short name T576
Test name
Test status
Simulation time 1080211472 ps
CPU time 13.99 seconds
Started Feb 08 12:52:21 PM UTC 25
Finished Feb 08 12:52:36 PM UTC 25
Peak memory 232684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2766092010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand
_reset.2766092010
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.2210881560
Short name T341
Test name
Test status
Simulation time 136245519 ps
CPU time 4.21 seconds
Started Feb 08 12:52:15 PM UTC 25
Finished Feb 08 12:52:20 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210881560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2210881560
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.1413633715
Short name T421
Test name
Test status
Simulation time 48782950 ps
CPU time 2.2 seconds
Started Feb 08 12:52:20 PM UTC 25
Finished Feb 08 12:52:23 PM UTC 25
Peak memory 218576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413633715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1413633715
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.2599932200
Short name T574
Test name
Test status
Simulation time 10289354 ps
CPU time 1.1 seconds
Started Feb 08 12:52:32 PM UTC 25
Finished Feb 08 12:52:35 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599932200 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2599932200
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.2873514146
Short name T575
Test name
Test status
Simulation time 376734335 ps
CPU time 4.83 seconds
Started Feb 08 12:52:30 PM UTC 25
Finished Feb 08 12:52:36 PM UTC 25
Peak memory 228868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873514146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 23.keymgr_custom_cm.2873514146
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.1887724273
Short name T569
Test name
Test status
Simulation time 93858141 ps
CPU time 4.68 seconds
Started Feb 08 12:52:24 PM UTC 25
Finished Feb 08 12:52:31 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887724273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1887724273
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.3784985894
Short name T570
Test name
Test status
Simulation time 38766865 ps
CPU time 1.94 seconds
Started Feb 08 12:52:29 PM UTC 25
Finished Feb 08 12:52:32 PM UTC 25
Peak memory 224996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784985894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3784985894
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.3518768355
Short name T568
Test name
Test status
Simulation time 105175929 ps
CPU time 4.55 seconds
Started Feb 08 12:52:25 PM UTC 25
Finished Feb 08 12:52:31 PM UTC 25
Peak memory 218328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518768355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 23.keymgr_lc_disable.3518768355
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_random.71000899
Short name T571
Test name
Test status
Simulation time 425179159 ps
CPU time 5.94 seconds
Started Feb 08 12:52:24 PM UTC 25
Finished Feb 08 12:52:32 PM UTC 25
Peak memory 224464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71000899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_rand
om_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 23.keymgr_random.71000899
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.561591266
Short name T566
Test name
Test status
Simulation time 125493817 ps
CPU time 5.19 seconds
Started Feb 08 12:52:22 PM UTC 25
Finished Feb 08 12:52:29 PM UTC 25
Peak memory 218388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561591266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.keymgr_sideload.561591266
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.2660227226
Short name T564
Test name
Test status
Simulation time 54263633 ps
CPU time 3.46 seconds
Started Feb 08 12:52:23 PM UTC 25
Finished Feb 08 12:52:28 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660227226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2660227226
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.4181555200
Short name T405
Test name
Test status
Simulation time 813204160 ps
CPU time 10.52 seconds
Started Feb 08 12:52:22 PM UTC 25
Finished Feb 08 12:52:34 PM UTC 25
Peak memory 218268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181555200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4181555200
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.1901092774
Short name T611
Test name
Test status
Simulation time 887994540 ps
CPU time 35.59 seconds
Started Feb 08 12:52:24 PM UTC 25
Finished Feb 08 12:53:02 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901092774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1901092774
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.1873386847
Short name T584
Test name
Test status
Simulation time 376831726 ps
CPU time 10.33 seconds
Started Feb 08 12:52:31 PM UTC 25
Finished Feb 08 12:52:43 PM UTC 25
Peak memory 224660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873386847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1873386847
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.1080258340
Short name T593
Test name
Test status
Simulation time 4059801088 ps
CPU time 26.43 seconds
Started Feb 08 12:52:22 PM UTC 25
Finished Feb 08 12:52:50 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080258340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.keymgr_smoke.1080258340
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.1066725465
Short name T386
Test name
Test status
Simulation time 318222881 ps
CPU time 6.67 seconds
Started Feb 08 12:52:26 PM UTC 25
Finished Feb 08 12:52:34 PM UTC 25
Peak memory 224492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066725465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1066725465
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.1903243662
Short name T573
Test name
Test status
Simulation time 91550514 ps
CPU time 1.53 seconds
Started Feb 08 12:52:31 PM UTC 25
Finished Feb 08 12:52:34 PM UTC 25
Peak memory 216804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903243662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1903243662
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.2059803360
Short name T583
Test name
Test status
Simulation time 33775730 ps
CPU time 1 seconds
Started Feb 08 12:52:40 PM UTC 25
Finished Feb 08 12:52:43 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059803360 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2059803360
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.1970432579
Short name T361
Test name
Test status
Simulation time 270890183 ps
CPU time 15.93 seconds
Started Feb 08 12:52:36 PM UTC 25
Finished Feb 08 12:52:53 PM UTC 25
Peak memory 224656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970432579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1970432579
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.1144285277
Short name T582
Test name
Test status
Simulation time 379718739 ps
CPU time 3.28 seconds
Started Feb 08 12:52:38 PM UTC 25
Finished Feb 08 12:52:43 PM UTC 25
Peak memory 231940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144285277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 24.keymgr_custom_cm.1144285277
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.3945665590
Short name T352
Test name
Test status
Simulation time 491310602 ps
CPU time 4.64 seconds
Started Feb 08 12:52:36 PM UTC 25
Finished Feb 08 12:52:42 PM UTC 25
Peak memory 218480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945665590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3945665590
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.3413652536
Short name T396
Test name
Test status
Simulation time 766080029 ps
CPU time 5.17 seconds
Started Feb 08 12:52:37 PM UTC 25
Finished Feb 08 12:52:44 PM UTC 25
Peak memory 231692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413652536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3413652536
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.579218977
Short name T392
Test name
Test status
Simulation time 115737444 ps
CPU time 3.01 seconds
Started Feb 08 12:52:37 PM UTC 25
Finished Feb 08 12:52:41 PM UTC 25
Peak memory 224456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579218977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.579218977
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.4031890072
Short name T580
Test name
Test status
Simulation time 51763704 ps
CPU time 3.2 seconds
Started Feb 08 12:52:36 PM UTC 25
Finished Feb 08 12:52:40 PM UTC 25
Peak memory 218148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031890072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 24.keymgr_lc_disable.4031890072
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_random.2513293481
Short name T544
Test name
Test status
Simulation time 140673215 ps
CPU time 3.03 seconds
Started Feb 08 12:52:35 PM UTC 25
Finished Feb 08 12:52:39 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513293481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.keymgr_random.2513293481
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.504912160
Short name T433
Test name
Test status
Simulation time 783600047 ps
CPU time 8.14 seconds
Started Feb 08 12:52:33 PM UTC 25
Finished Feb 08 12:52:43 PM UTC 25
Peak memory 218188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504912160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.keymgr_sideload.504912160
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.1284655650
Short name T581
Test name
Test status
Simulation time 120141097 ps
CPU time 4.87 seconds
Started Feb 08 12:52:34 PM UTC 25
Finished Feb 08 12:52:41 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284655650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1284655650
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.2762822539
Short name T578
Test name
Test status
Simulation time 30217369 ps
CPU time 2.52 seconds
Started Feb 08 12:52:34 PM UTC 25
Finished Feb 08 12:52:38 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762822539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2762822539
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.561569837
Short name T406
Test name
Test status
Simulation time 83072476 ps
CPU time 2.48 seconds
Started Feb 08 12:52:35 PM UTC 25
Finished Feb 08 12:52:38 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561569837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.561569837
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.283615895
Short name T585
Test name
Test status
Simulation time 123416689 ps
CPU time 3.94 seconds
Started Feb 08 12:52:38 PM UTC 25
Finished Feb 08 12:52:43 PM UTC 25
Peak memory 228756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283615895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.283615895
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.2225271009
Short name T579
Test name
Test status
Simulation time 345701352 ps
CPU time 4.72 seconds
Started Feb 08 12:52:33 PM UTC 25
Finished Feb 08 12:52:40 PM UTC 25
Peak memory 218164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225271009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.keymgr_smoke.2225271009
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all_with_rand_reset.1232015467
Short name T595
Test name
Test status
Simulation time 367921014 ps
CPU time 12.17 seconds
Started Feb 08 12:52:39 PM UTC 25
Finished Feb 08 12:52:53 PM UTC 25
Peak memory 232948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1232015467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand
_reset.1232015467
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.1090416230
Short name T587
Test name
Test status
Simulation time 318566109 ps
CPU time 9.82 seconds
Started Feb 08 12:52:36 PM UTC 25
Finished Feb 08 12:52:47 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090416230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1090416230
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.949405628
Short name T166
Test name
Test status
Simulation time 49832222 ps
CPU time 3.42 seconds
Started Feb 08 12:52:39 PM UTC 25
Finished Feb 08 12:52:44 PM UTC 25
Peak memory 220484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949405628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_syn
c_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.949405628
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.4105942198
Short name T596
Test name
Test status
Simulation time 22840526 ps
CPU time 1.02 seconds
Started Feb 08 12:52:50 PM UTC 25
Finished Feb 08 12:52:53 PM UTC 25
Peak memory 214008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105942198 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.4105942198
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.3932132747
Short name T307
Test name
Test status
Simulation time 61664525 ps
CPU time 5.76 seconds
Started Feb 08 12:52:44 PM UTC 25
Finished Feb 08 12:52:51 PM UTC 25
Peak memory 226456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932132747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3932132747
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.3358411418
Short name T592
Test name
Test status
Simulation time 217014773 ps
CPU time 4.16 seconds
Started Feb 08 12:52:44 PM UTC 25
Finished Feb 08 12:52:49 PM UTC 25
Peak memory 220292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358411418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3358411418
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.1330563339
Short name T96
Test name
Test status
Simulation time 1501286205 ps
CPU time 28.37 seconds
Started Feb 08 12:52:45 PM UTC 25
Finished Feb 08 12:53:15 PM UTC 25
Peak memory 232716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330563339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1330563339
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.1668317916
Short name T330
Test name
Test status
Simulation time 66196883 ps
CPU time 2.31 seconds
Started Feb 08 12:52:45 PM UTC 25
Finished Feb 08 12:52:49 PM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668317916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1668317916
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.1993011783
Short name T591
Test name
Test status
Simulation time 270069403 ps
CPU time 4.14 seconds
Started Feb 08 12:52:44 PM UTC 25
Finished Feb 08 12:52:49 PM UTC 25
Peak memory 230956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993011783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 25.keymgr_lc_disable.1993011783
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_random.637673283
Short name T594
Test name
Test status
Simulation time 105154024 ps
CPU time 6.79 seconds
Started Feb 08 12:52:44 PM UTC 25
Finished Feb 08 12:52:52 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637673283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.keymgr_random.637673283
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.2379992840
Short name T602
Test name
Test status
Simulation time 1244631338 ps
CPU time 14.24 seconds
Started Feb 08 12:52:41 PM UTC 25
Finished Feb 08 12:52:57 PM UTC 25
Peak memory 218252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379992840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.keymgr_sideload.2379992840
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.2784407251
Short name T588
Test name
Test status
Simulation time 303836990 ps
CPU time 4.31 seconds
Started Feb 08 12:52:43 PM UTC 25
Finished Feb 08 12:52:48 PM UTC 25
Peak memory 218224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784407251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2784407251
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.3902570030
Short name T590
Test name
Test status
Simulation time 385537609 ps
CPU time 6.01 seconds
Started Feb 08 12:52:41 PM UTC 25
Finished Feb 08 12:52:49 PM UTC 25
Peak memory 216524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902570030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3902570030
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.2287801945
Short name T589
Test name
Test status
Simulation time 747303628 ps
CPU time 4.73 seconds
Started Feb 08 12:52:43 PM UTC 25
Finished Feb 08 12:52:49 PM UTC 25
Peak memory 218472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287801945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2287801945
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.2853350399
Short name T598
Test name
Test status
Simulation time 78079711 ps
CPU time 4.13 seconds
Started Feb 08 12:52:48 PM UTC 25
Finished Feb 08 12:52:54 PM UTC 25
Peak memory 226436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853350399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2853350399
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.2781987566
Short name T586
Test name
Test status
Simulation time 402035877 ps
CPU time 3.71 seconds
Started Feb 08 12:52:40 PM UTC 25
Finished Feb 08 12:52:45 PM UTC 25
Peak memory 216464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781987566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.keymgr_smoke.2781987566
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.1770731081
Short name T81
Test name
Test status
Simulation time 2760371482 ps
CPU time 41.73 seconds
Started Feb 08 12:52:49 PM UTC 25
Finished Feb 08 12:53:33 PM UTC 25
Peak memory 232876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770731081 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1770731081
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.1406269206
Short name T367
Test name
Test status
Simulation time 59158727 ps
CPU time 4.74 seconds
Started Feb 08 12:52:44 PM UTC 25
Finished Feb 08 12:52:50 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406269206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1406269206
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.3729801536
Short name T597
Test name
Test status
Simulation time 198110674 ps
CPU time 2.62 seconds
Started Feb 08 12:52:49 PM UTC 25
Finished Feb 08 12:52:53 PM UTC 25
Peak memory 218380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729801536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3729801536
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.2192262707
Short name T610
Test name
Test status
Simulation time 10586657 ps
CPU time 0.94 seconds
Started Feb 08 12:52:58 PM UTC 25
Finished Feb 08 12:53:01 PM UTC 25
Peak memory 214604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192262707 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2192262707
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.1762666869
Short name T448
Test name
Test status
Simulation time 2463170169 ps
CPU time 58.76 seconds
Started Feb 08 12:52:54 PM UTC 25
Finished Feb 08 12:53:55 PM UTC 25
Peak memory 224528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762666869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1762666869
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.999665166
Short name T609
Test name
Test status
Simulation time 49327889 ps
CPU time 3.14 seconds
Started Feb 08 12:52:56 PM UTC 25
Finished Feb 08 12:53:01 PM UTC 25
Peak memory 224476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999665166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cus
tom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.keymgr_custom_cm.999665166
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.3097322738
Short name T607
Test name
Test status
Simulation time 124157709 ps
CPU time 4.02 seconds
Started Feb 08 12:52:54 PM UTC 25
Finished Feb 08 12:53:00 PM UTC 25
Peak memory 218316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097322738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3097322738
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.137302756
Short name T332
Test name
Test status
Simulation time 58117486 ps
CPU time 2.34 seconds
Started Feb 08 12:52:55 PM UTC 25
Finished Feb 08 12:52:59 PM UTC 25
Peak memory 224460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137302756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hws
w_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.137302756
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_random.110726916
Short name T618
Test name
Test status
Simulation time 554351273 ps
CPU time 16.56 seconds
Started Feb 08 12:52:53 PM UTC 25
Finished Feb 08 12:53:11 PM UTC 25
Peak memory 230620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110726916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.keymgr_random.110726916
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.879120036
Short name T605
Test name
Test status
Simulation time 932922314 ps
CPU time 6.7 seconds
Started Feb 08 12:52:50 PM UTC 25
Finished Feb 08 12:52:59 PM UTC 25
Peak memory 218516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879120036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.keymgr_sideload.879120036
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.1150421267
Short name T601
Test name
Test status
Simulation time 54131077 ps
CPU time 2.76 seconds
Started Feb 08 12:52:52 PM UTC 25
Finished Feb 08 12:52:56 PM UTC 25
Peak memory 216456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150421267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1150421267
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.2337067949
Short name T599
Test name
Test status
Simulation time 104796543 ps
CPU time 1.86 seconds
Started Feb 08 12:52:52 PM UTC 25
Finished Feb 08 12:52:55 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337067949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2337067949
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.2200449785
Short name T600
Test name
Test status
Simulation time 155744534 ps
CPU time 2.64 seconds
Started Feb 08 12:52:52 PM UTC 25
Finished Feb 08 12:52:56 PM UTC 25
Peak memory 216208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200449785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2200449785
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.158637403
Short name T608
Test name
Test status
Simulation time 116038011 ps
CPU time 2.46 seconds
Started Feb 08 12:52:56 PM UTC 25
Finished Feb 08 12:53:01 PM UTC 25
Peak memory 216276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158637403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.158637403
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.3682796424
Short name T603
Test name
Test status
Simulation time 209434918 ps
CPU time 5.5 seconds
Started Feb 08 12:52:50 PM UTC 25
Finished Feb 08 12:52:57 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682796424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.keymgr_smoke.3682796424
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all_with_rand_reset.302769851
Short name T626
Test name
Test status
Simulation time 5145884211 ps
CPU time 16.46 seconds
Started Feb 08 12:52:58 PM UTC 25
Finished Feb 08 12:53:17 PM UTC 25
Peak memory 232748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=302769851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_
reset.302769851
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.2586314608
Short name T308
Test name
Test status
Simulation time 1117525535 ps
CPU time 6 seconds
Started Feb 08 12:52:54 PM UTC 25
Finished Feb 08 12:53:02 PM UTC 25
Peak memory 220368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586314608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2586314608
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.280773840
Short name T643
Test name
Test status
Simulation time 4901950197 ps
CPU time 30.3 seconds
Started Feb 08 12:52:57 PM UTC 25
Finished Feb 08 12:53:30 PM UTC 25
Peak memory 220380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280773840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_syn
c_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.280773840
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.3981419824
Short name T619
Test name
Test status
Simulation time 85589302 ps
CPU time 1.22 seconds
Started Feb 08 12:53:09 PM UTC 25
Finished Feb 08 12:53:11 PM UTC 25
Peak memory 213980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981419824 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3981419824
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.173587652
Short name T424
Test name
Test status
Simulation time 63569009 ps
CPU time 4.99 seconds
Started Feb 08 12:53:02 PM UTC 25
Finished Feb 08 12:53:08 PM UTC 25
Peak memory 232600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173587652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.173587652
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.3957297937
Short name T429
Test name
Test status
Simulation time 49785869 ps
CPU time 2.76 seconds
Started Feb 08 12:53:04 PM UTC 25
Finished Feb 08 12:53:08 PM UTC 25
Peak memory 228844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957297937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 27.keymgr_custom_cm.3957297937
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.2472359624
Short name T615
Test name
Test status
Simulation time 135713037 ps
CPU time 3.4 seconds
Started Feb 08 12:53:02 PM UTC 25
Finished Feb 08 12:53:07 PM UTC 25
Peak memory 218288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472359624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2472359624
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.1085197088
Short name T101
Test name
Test status
Simulation time 321003563 ps
CPU time 4.75 seconds
Started Feb 08 12:53:03 PM UTC 25
Finished Feb 08 12:53:09 PM UTC 25
Peak memory 226704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085197088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1085197088
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.4108400582
Short name T393
Test name
Test status
Simulation time 132233161 ps
CPU time 2.65 seconds
Started Feb 08 12:53:03 PM UTC 25
Finished Feb 08 12:53:07 PM UTC 25
Peak memory 226556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108400582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.4108400582
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.536297942
Short name T616
Test name
Test status
Simulation time 168397673 ps
CPU time 3.45 seconds
Started Feb 08 12:53:03 PM UTC 25
Finished Feb 08 12:53:08 PM UTC 25
Peak memory 226716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536297942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 27.keymgr_lc_disable.536297942
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_random.3204424859
Short name T296
Test name
Test status
Simulation time 176487377 ps
CPU time 6.1 seconds
Started Feb 08 12:53:02 PM UTC 25
Finished Feb 08 12:53:09 PM UTC 25
Peak memory 224544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204424859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.keymgr_random.3204424859
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.1246463633
Short name T614
Test name
Test status
Simulation time 459771485 ps
CPU time 4.7 seconds
Started Feb 08 12:53:00 PM UTC 25
Finished Feb 08 12:53:06 PM UTC 25
Peak memory 218260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246463633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.keymgr_sideload.1246463633
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.2903503998
Short name T617
Test name
Test status
Simulation time 216474479 ps
CPU time 8.27 seconds
Started Feb 08 12:53:01 PM UTC 25
Finished Feb 08 12:53:11 PM UTC 25
Peak memory 218404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903503998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2903503998
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.112153825
Short name T628
Test name
Test status
Simulation time 2109906539 ps
CPU time 16.03 seconds
Started Feb 08 12:53:00 PM UTC 25
Finished Feb 08 12:53:17 PM UTC 25
Peak memory 218508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112153825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.112153825
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.1265705758
Short name T613
Test name
Test status
Simulation time 221528106 ps
CPU time 3.02 seconds
Started Feb 08 12:53:01 PM UTC 25
Finished Feb 08 12:53:05 PM UTC 25
Peak memory 216036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265705758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1265705758
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.3551802360
Short name T620
Test name
Test status
Simulation time 269645714 ps
CPU time 4.67 seconds
Started Feb 08 12:53:07 PM UTC 25
Finished Feb 08 12:53:13 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551802360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3551802360
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.1676456482
Short name T612
Test name
Test status
Simulation time 315570659 ps
CPU time 2.93 seconds
Started Feb 08 12:52:58 PM UTC 25
Finished Feb 08 12:53:03 PM UTC 25
Peak memory 216100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676456482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.keymgr_smoke.1676456482
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.366793685
Short name T370
Test name
Test status
Simulation time 166324129 ps
CPU time 3.73 seconds
Started Feb 08 12:53:03 PM UTC 25
Finished Feb 08 12:53:08 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366793685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_
invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.366793685
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.3168173242
Short name T431
Test name
Test status
Simulation time 1331832826 ps
CPU time 9.2 seconds
Started Feb 08 12:53:07 PM UTC 25
Finished Feb 08 12:53:17 PM UTC 25
Peak memory 220548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168173242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3168173242
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.3715091478
Short name T630
Test name
Test status
Simulation time 10734094 ps
CPU time 1.19 seconds
Started Feb 08 12:53:16 PM UTC 25
Finished Feb 08 12:53:19 PM UTC 25
Peak memory 214004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715091478 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3715091478
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.2090788985
Short name T412
Test name
Test status
Simulation time 34992889 ps
CPU time 2.86 seconds
Started Feb 08 12:53:10 PM UTC 25
Finished Feb 08 12:53:14 PM UTC 25
Peak memory 232604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090788985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2090788985
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.2151036428
Short name T633
Test name
Test status
Simulation time 229054379 ps
CPU time 3.86 seconds
Started Feb 08 12:53:14 PM UTC 25
Finished Feb 08 12:53:19 PM UTC 25
Peak memory 227064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151036428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 28.keymgr_custom_cm.2151036428
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.3635454574
Short name T625
Test name
Test status
Simulation time 41031268 ps
CPU time 2.39 seconds
Started Feb 08 12:53:11 PM UTC 25
Finished Feb 08 12:53:15 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635454574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3635454574
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.3157140751
Short name T629
Test name
Test status
Simulation time 287796256 ps
CPU time 3.2 seconds
Started Feb 08 12:53:14 PM UTC 25
Finished Feb 08 12:53:18 PM UTC 25
Peak memory 224660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157140751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3157140751
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.385872939
Short name T606
Test name
Test status
Simulation time 56808483 ps
CPU time 3.93 seconds
Started Feb 08 12:53:12 PM UTC 25
Finished Feb 08 12:53:18 PM UTC 25
Peak memory 232560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385872939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 28.keymgr_lc_disable.385872939
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_random.277642895
Short name T627
Test name
Test status
Simulation time 188386811 ps
CPU time 5.63 seconds
Started Feb 08 12:53:10 PM UTC 25
Finished Feb 08 12:53:17 PM UTC 25
Peak memory 218296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277642895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.keymgr_random.277642895
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.480428266
Short name T621
Test name
Test status
Simulation time 39231869 ps
CPU time 3.1 seconds
Started Feb 08 12:53:09 PM UTC 25
Finished Feb 08 12:53:13 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480428266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 28.keymgr_sideload.480428266
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.1573245900
Short name T624
Test name
Test status
Simulation time 68587558 ps
CPU time 3.66 seconds
Started Feb 08 12:53:09 PM UTC 25
Finished Feb 08 12:53:14 PM UTC 25
Peak memory 216520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573245900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1573245900
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.3793130161
Short name T673
Test name
Test status
Simulation time 1321950243 ps
CPU time 36.13 seconds
Started Feb 08 12:53:09 PM UTC 25
Finished Feb 08 12:53:47 PM UTC 25
Peak memory 218040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793130161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3793130161
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.2098702595
Short name T622
Test name
Test status
Simulation time 34974700 ps
CPU time 3.18 seconds
Started Feb 08 12:53:09 PM UTC 25
Finished Feb 08 12:53:14 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098702595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2098702595
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.852286317
Short name T655
Test name
Test status
Simulation time 696475214 ps
CPU time 20.08 seconds
Started Feb 08 12:53:15 PM UTC 25
Finished Feb 08 12:53:37 PM UTC 25
Peak memory 226708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852286317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.852286317
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.725487437
Short name T623
Test name
Test status
Simulation time 118726495 ps
CPU time 3.38 seconds
Started Feb 08 12:53:09 PM UTC 25
Finished Feb 08 12:53:14 PM UTC 25
Peak memory 216204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725487437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.keymgr_smoke.725487437
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.1588495660
Short name T339
Test name
Test status
Simulation time 241848912 ps
CPU time 7.49 seconds
Started Feb 08 12:53:15 PM UTC 25
Finished Feb 08 12:53:24 PM UTC 25
Peak memory 232604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588495660 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1588495660
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all_with_rand_reset.2159433495
Short name T658
Test name
Test status
Simulation time 1158008600 ps
CPU time 23.01 seconds
Started Feb 08 12:53:15 PM UTC 25
Finished Feb 08 12:53:39 PM UTC 25
Peak memory 232800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2159433495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand
_reset.2159433495
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.3684410125
Short name T631
Test name
Test status
Simulation time 304614932 ps
CPU time 4.7 seconds
Started Feb 08 12:53:12 PM UTC 25
Finished Feb 08 12:53:18 PM UTC 25
Peak memory 218244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684410125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3684410125
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.2833893593
Short name T632
Test name
Test status
Simulation time 469853155 ps
CPU time 2.72 seconds
Started Feb 08 12:53:15 PM UTC 25
Finished Feb 08 12:53:19 PM UTC 25
Peak memory 218576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833893593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2833893593
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.1059480633
Short name T640
Test name
Test status
Simulation time 32225896 ps
CPU time 1.11 seconds
Started Feb 08 12:53:25 PM UTC 25
Finished Feb 08 12:53:28 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059480633 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1059480633
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.701472661
Short name T635
Test name
Test status
Simulation time 175924282 ps
CPU time 3.86 seconds
Started Feb 08 12:53:20 PM UTC 25
Finished Feb 08 12:53:25 PM UTC 25
Peak memory 228480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701472661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.701472661
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.1580822669
Short name T98
Test name
Test status
Simulation time 436055051 ps
CPU time 8.35 seconds
Started Feb 08 12:53:20 PM UTC 25
Finished Feb 08 12:53:29 PM UTC 25
Peak memory 232524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580822669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1580822669
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.3089305821
Short name T418
Test name
Test status
Simulation time 218179668 ps
CPU time 4.31 seconds
Started Feb 08 12:53:20 PM UTC 25
Finished Feb 08 12:53:25 PM UTC 25
Peak memory 224336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089305821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3089305821
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_random.3684008133
Short name T638
Test name
Test status
Simulation time 418953009 ps
CPU time 5.77 seconds
Started Feb 08 12:53:18 PM UTC 25
Finished Feb 08 12:53:26 PM UTC 25
Peak memory 218304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684008133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.keymgr_random.3684008133
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.2077642302
Short name T636
Test name
Test status
Simulation time 500967357 ps
CPU time 5.78 seconds
Started Feb 08 12:53:18 PM UTC 25
Finished Feb 08 12:53:25 PM UTC 25
Peak memory 216468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077642302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.keymgr_sideload.2077642302
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.309961233
Short name T641
Test name
Test status
Simulation time 688866772 ps
CPU time 8.18 seconds
Started Feb 08 12:53:18 PM UTC 25
Finished Feb 08 12:53:28 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309961233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.309961233
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.63304443
Short name T639
Test name
Test status
Simulation time 128450782 ps
CPU time 6.8 seconds
Started Feb 08 12:53:18 PM UTC 25
Finished Feb 08 12:53:26 PM UTC 25
Peak memory 216188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63304443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.63304443
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.1303259900
Short name T700
Test name
Test status
Simulation time 1766951404 ps
CPU time 42.5 seconds
Started Feb 08 12:53:18 PM UTC 25
Finished Feb 08 12:54:03 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303259900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1303259900
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.1882987942
Short name T642
Test name
Test status
Simulation time 251655439 ps
CPU time 4.96 seconds
Started Feb 08 12:53:22 PM UTC 25
Finished Feb 08 12:53:28 PM UTC 25
Peak memory 224548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882987942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1882987942
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.3516699136
Short name T634
Test name
Test status
Simulation time 147123812 ps
CPU time 3.56 seconds
Started Feb 08 12:53:16 PM UTC 25
Finished Feb 08 12:53:21 PM UTC 25
Peak memory 218484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516699136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.keymgr_smoke.3516699136
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.3846869752
Short name T649
Test name
Test status
Simulation time 1521965714 ps
CPU time 11.86 seconds
Started Feb 08 12:53:20 PM UTC 25
Finished Feb 08 12:53:33 PM UTC 25
Peak memory 226544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846869752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3846869752
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.714921717
Short name T637
Test name
Test status
Simulation time 111719874 ps
CPU time 2.11 seconds
Started Feb 08 12:53:22 PM UTC 25
Finished Feb 08 12:53:25 PM UTC 25
Peak memory 218576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714921717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_syn
c_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.714921717
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.2445558011
Short name T461
Test name
Test status
Simulation time 35221386 ps
CPU time 0.95 seconds
Started Feb 08 12:48:36 PM UTC 25
Finished Feb 08 12:48:39 PM UTC 25
Peak memory 214032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445558011 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2445558011
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.370356544
Short name T136
Test name
Test status
Simulation time 42569483 ps
CPU time 3.83 seconds
Started Feb 08 12:48:26 PM UTC 25
Finished Feb 08 12:48:31 PM UTC 25
Peak memory 232904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370356544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.370356544
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.2305961287
Short name T28
Test name
Test status
Simulation time 132056607 ps
CPU time 5.75 seconds
Started Feb 08 12:48:30 PM UTC 25
Finished Feb 08 12:48:37 PM UTC 25
Peak memory 218780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305961287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 3.keymgr_custom_cm.2305961287
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.1595131668
Short name T71
Test name
Test status
Simulation time 73160622 ps
CPU time 4.73 seconds
Started Feb 08 12:48:28 PM UTC 25
Finished Feb 08 12:48:35 PM UTC 25
Peak memory 218472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595131668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1595131668
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.1650321835
Short name T23
Test name
Test status
Simulation time 1206853432 ps
CPU time 11.01 seconds
Started Feb 08 12:48:30 PM UTC 25
Finished Feb 08 12:48:42 PM UTC 25
Peak memory 218484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650321835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1650321835
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.702001444
Short name T95
Test name
Test status
Simulation time 131529896 ps
CPU time 4.75 seconds
Started Feb 08 12:48:30 PM UTC 25
Finished Feb 08 12:48:36 PM UTC 25
Peak memory 232440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702001444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.702001444
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.251745520
Short name T233
Test name
Test status
Simulation time 82829501 ps
CPU time 5.51 seconds
Started Feb 08 12:48:28 PM UTC 25
Finished Feb 08 12:48:35 PM UTC 25
Peak memory 216160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251745520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 3.keymgr_lc_disable.251745520
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_random.1908632479
Short name T232
Test name
Test status
Simulation time 139833194 ps
CPU time 7.57 seconds
Started Feb 08 12:48:26 PM UTC 25
Finished Feb 08 12:48:35 PM UTC 25
Peak memory 218244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908632479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.keymgr_random.1908632479
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.1209678479
Short name T109
Test name
Test status
Simulation time 3222093128 ps
CPU time 9.27 seconds
Started Feb 08 12:48:35 PM UTC 25
Finished Feb 08 12:48:46 PM UTC 25
Peak memory 260496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209678479 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1209678479
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.1678179510
Short name T208
Test name
Test status
Simulation time 24634210 ps
CPU time 2.61 seconds
Started Feb 08 12:48:22 PM UTC 25
Finished Feb 08 12:48:25 PM UTC 25
Peak memory 218268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678179510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.keymgr_sideload.1678179510
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.1418622592
Short name T209
Test name
Test status
Simulation time 151807267 ps
CPU time 3.07 seconds
Started Feb 08 12:48:23 PM UTC 25
Finished Feb 08 12:48:27 PM UTC 25
Peak memory 216172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418622592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1418622592
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.2513270131
Short name T211
Test name
Test status
Simulation time 303329560 ps
CPU time 5.75 seconds
Started Feb 08 12:48:22 PM UTC 25
Finished Feb 08 12:48:29 PM UTC 25
Peak memory 218324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513270131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2513270131
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.3888526528
Short name T210
Test name
Test status
Simulation time 106161426 ps
CPU time 4.27 seconds
Started Feb 08 12:48:23 PM UTC 25
Finished Feb 08 12:48:28 PM UTC 25
Peak memory 216236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888526528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3888526528
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.3227857428
Short name T265
Test name
Test status
Simulation time 51072287 ps
CPU time 2.97 seconds
Started Feb 08 12:48:30 PM UTC 25
Finished Feb 08 12:48:34 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227857428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3227857428
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.2179371994
Short name T207
Test name
Test status
Simulation time 445084141 ps
CPU time 4.63 seconds
Started Feb 08 12:48:19 PM UTC 25
Finished Feb 08 12:48:25 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179371994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.keymgr_smoke.2179371994
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.4110803000
Short name T290
Test name
Test status
Simulation time 11209423501 ps
CPU time 105.16 seconds
Started Feb 08 12:48:28 PM UTC 25
Finished Feb 08 12:50:16 PM UTC 25
Peak memory 218308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110803000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4110803000
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.3361738708
Short name T654
Test name
Test status
Simulation time 47159374 ps
CPU time 1.19 seconds
Started Feb 08 12:53:34 PM UTC 25
Finished Feb 08 12:53:36 PM UTC 25
Peak memory 214756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361738708 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3361738708
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.1767020640
Short name T428
Test name
Test status
Simulation time 1015716329 ps
CPU time 8.52 seconds
Started Feb 08 12:53:29 PM UTC 25
Finished Feb 08 12:53:39 PM UTC 25
Peak memory 224456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767020640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1767020640
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.412530037
Short name T650
Test name
Test status
Simulation time 51347074 ps
CPU time 2.57 seconds
Started Feb 08 12:53:29 PM UTC 25
Finished Feb 08 12:53:33 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412530037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.412530037
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.1552591995
Short name T661
Test name
Test status
Simulation time 3154135673 ps
CPU time 8.76 seconds
Started Feb 08 12:53:30 PM UTC 25
Finished Feb 08 12:53:40 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552591995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1552591995
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.3194651630
Short name T331
Test name
Test status
Simulation time 314559763 ps
CPU time 2.16 seconds
Started Feb 08 12:53:31 PM UTC 25
Finished Feb 08 12:53:34 PM UTC 25
Peak memory 226392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194651630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3194651630
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.735570599
Short name T651
Test name
Test status
Simulation time 388360038 ps
CPU time 3.62 seconds
Started Feb 08 12:53:29 PM UTC 25
Finished Feb 08 12:53:34 PM UTC 25
Peak memory 230568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735570599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 30.keymgr_lc_disable.735570599
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_random.1969250788
Short name T646
Test name
Test status
Simulation time 188054044 ps
CPU time 3.23 seconds
Started Feb 08 12:53:28 PM UTC 25
Finished Feb 08 12:53:32 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969250788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.keymgr_random.1969250788
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.1694351066
Short name T645
Test name
Test status
Simulation time 75083802 ps
CPU time 3.97 seconds
Started Feb 08 12:53:26 PM UTC 25
Finished Feb 08 12:53:32 PM UTC 25
Peak memory 218228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694351066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.keymgr_sideload.1694351066
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.2827525746
Short name T648
Test name
Test status
Simulation time 213119345 ps
CPU time 4.51 seconds
Started Feb 08 12:53:27 PM UTC 25
Finished Feb 08 12:53:32 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827525746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2827525746
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.442706368
Short name T644
Test name
Test status
Simulation time 37084409 ps
CPU time 3.2 seconds
Started Feb 08 12:53:26 PM UTC 25
Finished Feb 08 12:53:31 PM UTC 25
Peak memory 216460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442706368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.442706368
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.323260338
Short name T647
Test name
Test status
Simulation time 53603013 ps
CPU time 3.39 seconds
Started Feb 08 12:53:28 PM UTC 25
Finished Feb 08 12:53:32 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323260338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.323260338
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.3872445921
Short name T653
Test name
Test status
Simulation time 27092359 ps
CPU time 2.11 seconds
Started Feb 08 12:53:32 PM UTC 25
Finished Feb 08 12:53:36 PM UTC 25
Peak memory 224776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872445921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3872445921
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.1661970579
Short name T659
Test name
Test status
Simulation time 1202028348 ps
CPU time 12.21 seconds
Started Feb 08 12:53:26 PM UTC 25
Finished Feb 08 12:53:40 PM UTC 25
Peak memory 217960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661970579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.keymgr_smoke.1661970579
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.240027480
Short name T203
Test name
Test status
Simulation time 1856309657 ps
CPU time 35.36 seconds
Started Feb 08 12:53:33 PM UTC 25
Finished Feb 08 12:54:11 PM UTC 25
Peak memory 226644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240027480 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.240027480
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all_with_rand_reset.505512928
Short name T675
Test name
Test status
Simulation time 826618411 ps
CPU time 13.18 seconds
Started Feb 08 12:53:33 PM UTC 25
Finished Feb 08 12:53:48 PM UTC 25
Peak memory 232752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=505512928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_
reset.505512928
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.3364585327
Short name T652
Test name
Test status
Simulation time 61434430 ps
CPU time 4.11 seconds
Started Feb 08 12:53:29 PM UTC 25
Finished Feb 08 12:53:35 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364585327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3364585327
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.3169734326
Short name T173
Test name
Test status
Simulation time 291344004 ps
CPU time 3.93 seconds
Started Feb 08 12:53:33 PM UTC 25
Finished Feb 08 12:53:39 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169734326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3169734326
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.2444593327
Short name T666
Test name
Test status
Simulation time 13932245 ps
CPU time 1.35 seconds
Started Feb 08 12:53:41 PM UTC 25
Finished Feb 08 12:53:44 PM UTC 25
Peak memory 214148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444593327 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2444593327
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.2526630548
Short name T667
Test name
Test status
Simulation time 134785873 ps
CPU time 3.77 seconds
Started Feb 08 12:53:39 PM UTC 25
Finished Feb 08 12:53:44 PM UTC 25
Peak memory 230620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526630548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 31.keymgr_custom_cm.2526630548
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.4265924007
Short name T662
Test name
Test status
Simulation time 135734740 ps
CPU time 2.93 seconds
Started Feb 08 12:53:36 PM UTC 25
Finished Feb 08 12:53:40 PM UTC 25
Peak memory 218420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265924007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.4265924007
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.4154864611
Short name T664
Test name
Test status
Simulation time 55782154 ps
CPU time 2.57 seconds
Started Feb 08 12:53:38 PM UTC 25
Finished Feb 08 12:53:42 PM UTC 25
Peak memory 224684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154864611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.4154864611
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.1771132195
Short name T660
Test name
Test status
Simulation time 69582182 ps
CPU time 2.64 seconds
Started Feb 08 12:53:36 PM UTC 25
Finished Feb 08 12:53:40 PM UTC 25
Peak memory 232748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771132195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 31.keymgr_lc_disable.1771132195
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_random.1899859888
Short name T669
Test name
Test status
Simulation time 1191722246 ps
CPU time 7.99 seconds
Started Feb 08 12:53:35 PM UTC 25
Finished Feb 08 12:53:44 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899859888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.keymgr_random.1899859888
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.3413607998
Short name T368
Test name
Test status
Simulation time 245671590 ps
CPU time 3.17 seconds
Started Feb 08 12:53:34 PM UTC 25
Finished Feb 08 12:53:38 PM UTC 25
Peak memory 218348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413607998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.keymgr_sideload.3413607998
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.2264185849
Short name T663
Test name
Test status
Simulation time 127267251 ps
CPU time 5.24 seconds
Started Feb 08 12:53:35 PM UTC 25
Finished Feb 08 12:53:42 PM UTC 25
Peak memory 216140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264185849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2264185849
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.345370908
Short name T668
Test name
Test status
Simulation time 547674837 ps
CPU time 7.3 seconds
Started Feb 08 12:53:35 PM UTC 25
Finished Feb 08 12:53:44 PM UTC 25
Peak memory 216160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345370908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.345370908
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.3087676920
Short name T657
Test name
Test status
Simulation time 254520676 ps
CPU time 3.01 seconds
Started Feb 08 12:53:35 PM UTC 25
Finished Feb 08 12:53:39 PM UTC 25
Peak memory 218336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087676920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3087676920
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.3979642019
Short name T665
Test name
Test status
Simulation time 158064126 ps
CPU time 2.56 seconds
Started Feb 08 12:53:40 PM UTC 25
Finished Feb 08 12:53:44 PM UTC 25
Peak memory 218440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979642019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3979642019
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.53074436
Short name T656
Test name
Test status
Simulation time 83694935 ps
CPU time 2.96 seconds
Started Feb 08 12:53:34 PM UTC 25
Finished Feb 08 12:53:38 PM UTC 25
Peak memory 218252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53074436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.keymgr_smoke.53074436
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.2340042127
Short name T722
Test name
Test status
Simulation time 2010203334 ps
CPU time 33.84 seconds
Started Feb 08 12:53:40 PM UTC 25
Finished Feb 08 12:54:15 PM UTC 25
Peak memory 226436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340042127 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2340042127
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all_with_rand_reset.3734514008
Short name T321
Test name
Test status
Simulation time 103230954 ps
CPU time 6.87 seconds
Started Feb 08 12:53:41 PM UTC 25
Finished Feb 08 12:53:49 PM UTC 25
Peak memory 230856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3734514008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand
_reset.3734514008
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.1154991229
Short name T728
Test name
Test status
Simulation time 1263770951 ps
CPU time 37.69 seconds
Started Feb 08 12:53:37 PM UTC 25
Finished Feb 08 12:54:17 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154991229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1154991229
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.2566088462
Short name T162
Test name
Test status
Simulation time 59677929 ps
CPU time 1.85 seconds
Started Feb 08 12:53:40 PM UTC 25
Finished Feb 08 12:53:43 PM UTC 25
Peak memory 218056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566088462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2566088462
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.633053423
Short name T679
Test name
Test status
Simulation time 14691184 ps
CPU time 1.14 seconds
Started Feb 08 12:53:47 PM UTC 25
Finished Feb 08 12:53:49 PM UTC 25
Peak memory 214752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633053423 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.633053423
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.1883498820
Short name T457
Test name
Test status
Simulation time 235191305 ps
CPU time 4.18 seconds
Started Feb 08 12:53:43 PM UTC 25
Finished Feb 08 12:53:49 PM UTC 25
Peak memory 226440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883498820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1883498820
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.1041039920
Short name T687
Test name
Test status
Simulation time 899141404 ps
CPU time 8.75 seconds
Started Feb 08 12:53:43 PM UTC 25
Finished Feb 08 12:53:54 PM UTC 25
Peak memory 218244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041039920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1041039920
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.1780738594
Short name T680
Test name
Test status
Simulation time 90882172 ps
CPU time 3.69 seconds
Started Feb 08 12:53:45 PM UTC 25
Finished Feb 08 12:53:50 PM UTC 25
Peak memory 224336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780738594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1780738594
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.840327221
Short name T676
Test name
Test status
Simulation time 42701279 ps
CPU time 3.61 seconds
Started Feb 08 12:53:43 PM UTC 25
Finished Feb 08 12:53:48 PM UTC 25
Peak memory 230544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840327221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 32.keymgr_lc_disable.840327221
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_random.1507506025
Short name T681
Test name
Test status
Simulation time 2350069848 ps
CPU time 6.13 seconds
Started Feb 08 12:53:42 PM UTC 25
Finished Feb 08 12:53:50 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507506025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.keymgr_random.1507506025
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.3976813245
Short name T670
Test name
Test status
Simulation time 48493704 ps
CPU time 2.55 seconds
Started Feb 08 12:53:41 PM UTC 25
Finished Feb 08 12:53:45 PM UTC 25
Peak memory 218252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976813245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.keymgr_sideload.3976813245
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.4158552824
Short name T703
Test name
Test status
Simulation time 826662736 ps
CPU time 21.34 seconds
Started Feb 08 12:53:41 PM UTC 25
Finished Feb 08 12:54:04 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158552824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4158552824
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.3047950528
Short name T674
Test name
Test status
Simulation time 377876430 ps
CPU time 5.64 seconds
Started Feb 08 12:53:41 PM UTC 25
Finished Feb 08 12:53:48 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047950528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3047950528
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.1465258409
Short name T672
Test name
Test status
Simulation time 938662958 ps
CPU time 3.55 seconds
Started Feb 08 12:53:41 PM UTC 25
Finished Feb 08 12:53:46 PM UTC 25
Peak memory 216336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465258409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1465258409
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.2222456060
Short name T677
Test name
Test status
Simulation time 127474122 ps
CPU time 2.52 seconds
Started Feb 08 12:53:45 PM UTC 25
Finished Feb 08 12:53:49 PM UTC 25
Peak memory 218288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222456060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2222456060
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.3307094515
Short name T671
Test name
Test status
Simulation time 137436675 ps
CPU time 2.98 seconds
Started Feb 08 12:53:41 PM UTC 25
Finished Feb 08 12:53:45 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307094515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.keymgr_smoke.3307094515
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.776567920
Short name T736
Test name
Test status
Simulation time 8536753516 ps
CPU time 34.02 seconds
Started Feb 08 12:53:46 PM UTC 25
Finished Feb 08 12:54:21 PM UTC 25
Peak memory 226768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776567920 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.776567920
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all_with_rand_reset.1934820545
Short name T190
Test name
Test status
Simulation time 493096037 ps
CPU time 3.35 seconds
Started Feb 08 12:53:46 PM UTC 25
Finished Feb 08 12:53:51 PM UTC 25
Peak memory 224524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1934820545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand
_reset.1934820545
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.1231001456
Short name T678
Test name
Test status
Simulation time 86046647 ps
CPU time 3.8 seconds
Started Feb 08 12:53:43 PM UTC 25
Finished Feb 08 12:53:49 PM UTC 25
Peak memory 218316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231001456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1231001456
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.2580062130
Short name T206
Test name
Test status
Simulation time 313787268 ps
CPU time 2.1 seconds
Started Feb 08 12:53:46 PM UTC 25
Finished Feb 08 12:53:49 PM UTC 25
Peak memory 220368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580062130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2580062130
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.3858009642
Short name T689
Test name
Test status
Simulation time 17991926 ps
CPU time 0.75 seconds
Started Feb 08 12:53:52 PM UTC 25
Finished Feb 08 12:53:54 PM UTC 25
Peak memory 214756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858009642 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3858009642
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.1401990740
Short name T450
Test name
Test status
Simulation time 924370532 ps
CPU time 8.5 seconds
Started Feb 08 12:53:49 PM UTC 25
Finished Feb 08 12:54:00 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401990740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1401990740
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.1861906239
Short name T383
Test name
Test status
Simulation time 61274423 ps
CPU time 3.06 seconds
Started Feb 08 12:53:51 PM UTC 25
Finished Feb 08 12:53:55 PM UTC 25
Peak memory 224364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861906239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 33.keymgr_custom_cm.1861906239
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.2596288201
Short name T688
Test name
Test status
Simulation time 114642350 ps
CPU time 2.87 seconds
Started Feb 08 12:53:49 PM UTC 25
Finished Feb 08 12:53:54 PM UTC 25
Peak memory 218316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596288201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2596288201
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.2183887582
Short name T260
Test name
Test status
Simulation time 46858653 ps
CPU time 3.87 seconds
Started Feb 08 12:53:50 PM UTC 25
Finished Feb 08 12:53:55 PM UTC 25
Peak memory 218244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183887582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2183887582
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.4033159246
Short name T377
Test name
Test status
Simulation time 361262519 ps
CPU time 4.16 seconds
Started Feb 08 12:53:51 PM UTC 25
Finished Feb 08 12:53:56 PM UTC 25
Peak memory 232760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033159246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4033159246
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.3784849914
Short name T62
Test name
Test status
Simulation time 85237754 ps
CPU time 3.9 seconds
Started Feb 08 12:53:50 PM UTC 25
Finished Feb 08 12:53:55 PM UTC 25
Peak memory 224472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784849914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 33.keymgr_lc_disable.3784849914
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_random.3188572029
Short name T409
Test name
Test status
Simulation time 425856978 ps
CPU time 8.12 seconds
Started Feb 08 12:53:49 PM UTC 25
Finished Feb 08 12:53:59 PM UTC 25
Peak memory 218400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188572029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.keymgr_random.3188572029
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.832365611
Short name T685
Test name
Test status
Simulation time 65310150 ps
CPU time 2.38 seconds
Started Feb 08 12:53:48 PM UTC 25
Finished Feb 08 12:53:52 PM UTC 25
Peak memory 218252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832365611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 33.keymgr_sideload.832365611
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.4292887153
Short name T683
Test name
Test status
Simulation time 85064461 ps
CPU time 1.76 seconds
Started Feb 08 12:53:48 PM UTC 25
Finished Feb 08 12:53:51 PM UTC 25
Peak memory 218020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292887153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4292887153
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.2371105550
Short name T684
Test name
Test status
Simulation time 66964677 ps
CPU time 2.49 seconds
Started Feb 08 12:53:48 PM UTC 25
Finished Feb 08 12:53:52 PM UTC 25
Peak memory 216196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371105550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2371105550
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.2122410750
Short name T691
Test name
Test status
Simulation time 270773420 ps
CPU time 4.26 seconds
Started Feb 08 12:53:49 PM UTC 25
Finished Feb 08 12:53:55 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122410750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2122410750
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.1365006414
Short name T702
Test name
Test status
Simulation time 1489773393 ps
CPU time 10.74 seconds
Started Feb 08 12:53:51 PM UTC 25
Finished Feb 08 12:54:03 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365006414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1365006414
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.3204682777
Short name T686
Test name
Test status
Simulation time 1761385517 ps
CPU time 5.01 seconds
Started Feb 08 12:53:47 PM UTC 25
Finished Feb 08 12:53:53 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204682777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.keymgr_smoke.3204682777
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.617717248
Short name T63
Test name
Test status
Simulation time 1015212562 ps
CPU time 34.92 seconds
Started Feb 08 12:53:51 PM UTC 25
Finished Feb 08 12:54:28 PM UTC 25
Peak memory 232448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617717248 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.617717248
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.3405336220
Short name T706
Test name
Test status
Simulation time 169697732 ps
CPU time 12.1 seconds
Started Feb 08 12:53:51 PM UTC 25
Finished Feb 08 12:54:05 PM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3405336220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand
_reset.3405336220
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.2181287782
Short name T690
Test name
Test status
Simulation time 66695875 ps
CPU time 3.44 seconds
Started Feb 08 12:53:50 PM UTC 25
Finished Feb 08 12:53:54 PM UTC 25
Peak memory 218244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181287782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2181287782
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.2394641076
Short name T693
Test name
Test status
Simulation time 169627098 ps
CPU time 2.86 seconds
Started Feb 08 12:53:51 PM UTC 25
Finished Feb 08 12:53:55 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394641076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2394641076
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.1550466504
Short name T699
Test name
Test status
Simulation time 19558677 ps
CPU time 1.1 seconds
Started Feb 08 12:54:00 PM UTC 25
Finished Feb 08 12:54:03 PM UTC 25
Peak memory 214756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550466504 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1550466504
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.960805173
Short name T459
Test name
Test status
Simulation time 50173623 ps
CPU time 2.85 seconds
Started Feb 08 12:53:55 PM UTC 25
Finished Feb 08 12:54:00 PM UTC 25
Peak memory 223964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960805173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.960805173
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.1078890652
Short name T256
Test name
Test status
Simulation time 705093747 ps
CPU time 6.68 seconds
Started Feb 08 12:53:57 PM UTC 25
Finished Feb 08 12:54:05 PM UTC 25
Peak memory 218260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078890652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 34.keymgr_custom_cm.1078890652
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.2089582335
Short name T698
Test name
Test status
Simulation time 315774461 ps
CPU time 5.63 seconds
Started Feb 08 12:53:55 PM UTC 25
Finished Feb 08 12:54:02 PM UTC 25
Peak memory 226540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089582335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2089582335
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.121154519
Short name T375
Test name
Test status
Simulation time 960106363 ps
CPU time 3.96 seconds
Started Feb 08 12:53:56 PM UTC 25
Finished Feb 08 12:54:01 PM UTC 25
Peak memory 224388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121154519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hws
w_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.121154519
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.1784246516
Short name T357
Test name
Test status
Simulation time 549752590 ps
CPU time 4.95 seconds
Started Feb 08 12:53:57 PM UTC 25
Finished Feb 08 12:54:03 PM UTC 25
Peak memory 224436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784246516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1784246516
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.38464249
Short name T241
Test name
Test status
Simulation time 469837246 ps
CPU time 4.08 seconds
Started Feb 08 12:53:55 PM UTC 25
Finished Feb 08 12:54:01 PM UTC 25
Peak memory 228056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38464249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_d
isable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.keymgr_lc_disable.38464249
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_random.3950508705
Short name T705
Test name
Test status
Simulation time 243088907 ps
CPU time 8.65 seconds
Started Feb 08 12:53:54 PM UTC 25
Finished Feb 08 12:54:04 PM UTC 25
Peak memory 224656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950508705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.keymgr_random.3950508705
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.2404530661
Short name T694
Test name
Test status
Simulation time 87235590 ps
CPU time 2.32 seconds
Started Feb 08 12:53:53 PM UTC 25
Finished Feb 08 12:53:57 PM UTC 25
Peak memory 216392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404530661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.keymgr_sideload.2404530661
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.3697214812
Short name T726
Test name
Test status
Simulation time 3196502653 ps
CPU time 20.61 seconds
Started Feb 08 12:53:54 PM UTC 25
Finished Feb 08 12:54:16 PM UTC 25
Peak memory 218440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697214812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3697214812
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.1265565765
Short name T695
Test name
Test status
Simulation time 211906150 ps
CPU time 2.79 seconds
Started Feb 08 12:53:53 PM UTC 25
Finished Feb 08 12:53:57 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265565765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1265565765
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.4214462239
Short name T697
Test name
Test status
Simulation time 913094313 ps
CPU time 5.06 seconds
Started Feb 08 12:53:54 PM UTC 25
Finished Feb 08 12:54:01 PM UTC 25
Peak memory 218336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214462239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.4214462239
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.2754122527
Short name T303
Test name
Test status
Simulation time 221861752 ps
CPU time 3.35 seconds
Started Feb 08 12:53:57 PM UTC 25
Finished Feb 08 12:54:01 PM UTC 25
Peak memory 218228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754122527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2754122527
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.900421819
Short name T696
Test name
Test status
Simulation time 225894596 ps
CPU time 6.38 seconds
Started Feb 08 12:53:52 PM UTC 25
Finished Feb 08 12:54:00 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900421819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.keymgr_smoke.900421819
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.1195945254
Short name T918
Test name
Test status
Simulation time 17967370355 ps
CPU time 157.79 seconds
Started Feb 08 12:53:58 PM UTC 25
Finished Feb 08 12:56:39 PM UTC 25
Peak memory 228624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195945254 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1195945254
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.2424106298
Short name T717
Test name
Test status
Simulation time 465033177 ps
CPU time 12.25 seconds
Started Feb 08 12:53:58 PM UTC 25
Finished Feb 08 12:54:12 PM UTC 25
Peak memory 232768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2424106298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand
_reset.2424106298
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.254409268
Short name T701
Test name
Test status
Simulation time 211443139 ps
CPU time 5.87 seconds
Started Feb 08 12:53:56 PM UTC 25
Finished Feb 08 12:54:03 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254409268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_
invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.254409268
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.1495893231
Short name T152
Test name
Test status
Simulation time 58436572 ps
CPU time 1.9 seconds
Started Feb 08 12:53:58 PM UTC 25
Finished Feb 08 12:54:01 PM UTC 25
Peak memory 218056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495893231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1495893231
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.2260592059
Short name T710
Test name
Test status
Simulation time 10048296 ps
CPU time 1.01 seconds
Started Feb 08 12:54:06 PM UTC 25
Finished Feb 08 12:54:08 PM UTC 25
Peak memory 213436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260592059 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2260592059
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.3667226776
Short name T445
Test name
Test status
Simulation time 293208527 ps
CPU time 10.55 seconds
Started Feb 08 12:54:02 PM UTC 25
Finished Feb 08 12:54:14 PM UTC 25
Peak memory 224720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667226776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3667226776
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.153120099
Short name T756
Test name
Test status
Simulation time 2159983831 ps
CPU time 26.71 seconds
Started Feb 08 12:54:02 PM UTC 25
Finished Feb 08 12:54:31 PM UTC 25
Peak memory 218304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153120099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.153120099
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.3444118558
Short name T709
Test name
Test status
Simulation time 60122644 ps
CPU time 2.3 seconds
Started Feb 08 12:54:04 PM UTC 25
Finished Feb 08 12:54:07 PM UTC 25
Peak memory 226544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444118558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3444118558
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.657829850
Short name T712
Test name
Test status
Simulation time 523334011 ps
CPU time 4.89 seconds
Started Feb 08 12:54:04 PM UTC 25
Finished Feb 08 12:54:10 PM UTC 25
Peak memory 230580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657829850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.657829850
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.3383854384
Short name T714
Test name
Test status
Simulation time 510220634 ps
CPU time 5.51 seconds
Started Feb 08 12:54:04 PM UTC 25
Finished Feb 08 12:54:11 PM UTC 25
Peak memory 226712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383854384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 35.keymgr_lc_disable.3383854384
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_random.3974900990
Short name T363
Test name
Test status
Simulation time 884305309 ps
CPU time 7.1 seconds
Started Feb 08 12:54:02 PM UTC 25
Finished Feb 08 12:54:11 PM UTC 25
Peak memory 216464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974900990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.keymgr_random.3974900990
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.3028830897
Short name T715
Test name
Test status
Simulation time 487849363 ps
CPU time 8.16 seconds
Started Feb 08 12:54:01 PM UTC 25
Finished Feb 08 12:54:11 PM UTC 25
Peak memory 216148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028830897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.keymgr_sideload.3028830897
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.576078991
Short name T707
Test name
Test status
Simulation time 334761249 ps
CPU time 2.58 seconds
Started Feb 08 12:54:01 PM UTC 25
Finished Feb 08 12:54:05 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576078991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.576078991
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.1804780564
Short name T708
Test name
Test status
Simulation time 115164809 ps
CPU time 3.27 seconds
Started Feb 08 12:54:01 PM UTC 25
Finished Feb 08 12:54:06 PM UTC 25
Peak memory 216412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804780564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1804780564
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.3494878855
Short name T718
Test name
Test status
Simulation time 385370634 ps
CPU time 9.35 seconds
Started Feb 08 12:54:02 PM UTC 25
Finished Feb 08 12:54:13 PM UTC 25
Peak memory 218244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494878855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3494878855
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.1825085145
Short name T711
Test name
Test status
Simulation time 201522554 ps
CPU time 4.34 seconds
Started Feb 08 12:54:04 PM UTC 25
Finished Feb 08 12:54:10 PM UTC 25
Peak memory 228644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825085145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1825085145
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.742826336
Short name T704
Test name
Test status
Simulation time 233685035 ps
CPU time 2.79 seconds
Started Feb 08 12:54:00 PM UTC 25
Finished Feb 08 12:54:04 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742826336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.keymgr_smoke.742826336
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.761312439
Short name T727
Test name
Test status
Simulation time 650433575 ps
CPU time 10.18 seconds
Started Feb 08 12:54:05 PM UTC 25
Finished Feb 08 12:54:17 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761312439 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.761312439
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.3804770063
Short name T716
Test name
Test status
Simulation time 197443102 ps
CPU time 6.3 seconds
Started Feb 08 12:54:04 PM UTC 25
Finished Feb 08 12:54:11 PM UTC 25
Peak memory 228584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804770063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3804770063
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.3748699680
Short name T720
Test name
Test status
Simulation time 269590867 ps
CPU time 7.57 seconds
Started Feb 08 12:54:05 PM UTC 25
Finished Feb 08 12:54:14 PM UTC 25
Peak memory 220460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748699680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3748699680
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.759601005
Short name T731
Test name
Test status
Simulation time 29851311 ps
CPU time 1.08 seconds
Started Feb 08 12:54:15 PM UTC 25
Finished Feb 08 12:54:18 PM UTC 25
Peak memory 213964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759601005 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.759601005
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.1104491133
Short name T460
Test name
Test status
Simulation time 4455428990 ps
CPU time 55.16 seconds
Started Feb 08 12:54:10 PM UTC 25
Finished Feb 08 12:55:07 PM UTC 25
Peak memory 226504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104491133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1104491133
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.2063156379
Short name T744
Test name
Test status
Simulation time 2896446886 ps
CPU time 13.45 seconds
Started Feb 08 12:54:12 PM UTC 25
Finished Feb 08 12:54:27 PM UTC 25
Peak memory 228832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063156379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 36.keymgr_custom_cm.2063156379
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.1397069790
Short name T725
Test name
Test status
Simulation time 141566153 ps
CPU time 3.43 seconds
Started Feb 08 12:54:12 PM UTC 25
Finished Feb 08 12:54:16 PM UTC 25
Peak memory 214688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397069790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1397069790
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.1131275014
Short name T293
Test name
Test status
Simulation time 308407317 ps
CPU time 10.9 seconds
Started Feb 08 12:54:12 PM UTC 25
Finished Feb 08 12:54:24 PM UTC 25
Peak memory 231020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131275014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1131275014
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.1126135797
Short name T730
Test name
Test status
Simulation time 434242282 ps
CPU time 4.41 seconds
Started Feb 08 12:54:12 PM UTC 25
Finished Feb 08 12:54:18 PM UTC 25
Peak memory 224668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126135797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1126135797
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.4145688504
Short name T729
Test name
Test status
Simulation time 103612033 ps
CPU time 3.72 seconds
Started Feb 08 12:54:12 PM UTC 25
Finished Feb 08 12:54:17 PM UTC 25
Peak memory 219248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145688504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 36.keymgr_lc_disable.4145688504
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_random.3208517878
Short name T724
Test name
Test status
Simulation time 244619172 ps
CPU time 5.68 seconds
Started Feb 08 12:54:09 PM UTC 25
Finished Feb 08 12:54:16 PM UTC 25
Peak memory 218612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208517878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.keymgr_random.3208517878
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.2365224955
Short name T721
Test name
Test status
Simulation time 363024458 ps
CPU time 7.35 seconds
Started Feb 08 12:54:06 PM UTC 25
Finished Feb 08 12:54:15 PM UTC 25
Peak memory 218324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365224955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.keymgr_sideload.2365224955
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.2012137498
Short name T692
Test name
Test status
Simulation time 463623536 ps
CPU time 14.06 seconds
Started Feb 08 12:54:08 PM UTC 25
Finished Feb 08 12:54:24 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012137498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2012137498
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.1173088364
Short name T723
Test name
Test status
Simulation time 479510428 ps
CPU time 7.79 seconds
Started Feb 08 12:54:07 PM UTC 25
Finished Feb 08 12:54:16 PM UTC 25
Peak memory 216464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173088364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1173088364
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.3394126194
Short name T719
Test name
Test status
Simulation time 196563696 ps
CPU time 3.19 seconds
Started Feb 08 12:54:09 PM UTC 25
Finished Feb 08 12:54:14 PM UTC 25
Peak memory 216196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394126194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3394126194
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.3105824570
Short name T732
Test name
Test status
Simulation time 137020277 ps
CPU time 4.63 seconds
Started Feb 08 12:54:13 PM UTC 25
Finished Feb 08 12:54:19 PM UTC 25
Peak memory 224468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105824570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3105824570
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.706436720
Short name T713
Test name
Test status
Simulation time 237288654 ps
CPU time 2.8 seconds
Started Feb 08 12:54:06 PM UTC 25
Finished Feb 08 12:54:10 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706436720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 36.keymgr_smoke.706436720
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.1824220761
Short name T338
Test name
Test status
Simulation time 485882868 ps
CPU time 20.73 seconds
Started Feb 08 12:54:14 PM UTC 25
Finished Feb 08 12:54:36 PM UTC 25
Peak memory 226436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824220761 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1824220761
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.3091237863
Short name T734
Test name
Test status
Simulation time 356415486 ps
CPU time 7.04 seconds
Started Feb 08 12:54:12 PM UTC 25
Finished Feb 08 12:54:20 PM UTC 25
Peak memory 217956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091237863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3091237863
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.1290402562
Short name T170
Test name
Test status
Simulation time 1028934115 ps
CPU time 3.78 seconds
Started Feb 08 12:54:13 PM UTC 25
Finished Feb 08 12:54:18 PM UTC 25
Peak memory 220452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290402562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1290402562
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.558245973
Short name T742
Test name
Test status
Simulation time 61142459 ps
CPU time 1.18 seconds
Started Feb 08 12:54:22 PM UTC 25
Finished Feb 08 12:54:25 PM UTC 25
Peak memory 213672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558245973 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.558245973
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.2478057477
Short name T240
Test name
Test status
Simulation time 93453067 ps
CPU time 3.7 seconds
Started Feb 08 12:54:19 PM UTC 25
Finished Feb 08 12:54:24 PM UTC 25
Peak memory 218340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478057477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 37.keymgr_custom_cm.2478057477
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.1988227343
Short name T738
Test name
Test status
Simulation time 80842629 ps
CPU time 3.01 seconds
Started Feb 08 12:54:18 PM UTC 25
Finished Feb 08 12:54:22 PM UTC 25
Peak memory 218276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988227343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1988227343
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.2728919118
Short name T380
Test name
Test status
Simulation time 323434757 ps
CPU time 5.37 seconds
Started Feb 08 12:54:18 PM UTC 25
Finished Feb 08 12:54:25 PM UTC 25
Peak memory 226444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728919118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2728919118
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.37381960
Short name T682
Test name
Test status
Simulation time 211143119 ps
CPU time 3.73 seconds
Started Feb 08 12:54:19 PM UTC 25
Finished Feb 08 12:54:24 PM UTC 25
Peak memory 226380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37381960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac
_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.37381960
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.3230963675
Short name T739
Test name
Test status
Simulation time 41764389 ps
CPU time 3.21 seconds
Started Feb 08 12:54:18 PM UTC 25
Finished Feb 08 12:54:22 PM UTC 25
Peak memory 224664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230963675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 37.keymgr_lc_disable.3230963675
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_random.233925636
Short name T343
Test name
Test status
Simulation time 365915098 ps
CPU time 4.93 seconds
Started Feb 08 12:54:18 PM UTC 25
Finished Feb 08 12:54:24 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233925636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 37.keymgr_random.233925636
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.1463165549
Short name T381
Test name
Test status
Simulation time 63537747 ps
CPU time 3.13 seconds
Started Feb 08 12:54:16 PM UTC 25
Finished Feb 08 12:54:21 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463165549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.keymgr_sideload.1463165549
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.1246708116
Short name T735
Test name
Test status
Simulation time 29773940 ps
CPU time 2.35 seconds
Started Feb 08 12:54:17 PM UTC 25
Finished Feb 08 12:54:21 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246708116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1246708116
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.1210299251
Short name T865
Test name
Test status
Simulation time 6209068885 ps
CPU time 66.66 seconds
Started Feb 08 12:54:16 PM UTC 25
Finished Feb 08 12:55:25 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210299251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1210299251
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.524563401
Short name T737
Test name
Test status
Simulation time 23970072 ps
CPU time 2.38 seconds
Started Feb 08 12:54:18 PM UTC 25
Finished Feb 08 12:54:21 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524563401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.524563401
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.1748336112
Short name T776
Test name
Test status
Simulation time 2470859452 ps
CPU time 22.45 seconds
Started Feb 08 12:54:19 PM UTC 25
Finished Feb 08 12:54:43 PM UTC 25
Peak memory 218516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748336112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1748336112
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.3826328029
Short name T733
Test name
Test status
Simulation time 75298025 ps
CPU time 2.5 seconds
Started Feb 08 12:54:15 PM UTC 25
Finished Feb 08 12:54:19 PM UTC 25
Peak memory 218592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826328029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 37.keymgr_smoke.3826328029
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.1899238749
Short name T908
Test name
Test status
Simulation time 3871591786 ps
CPU time 91.73 seconds
Started Feb 08 12:54:20 PM UTC 25
Finished Feb 08 12:55:54 PM UTC 25
Peak memory 231884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899238749 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1899238749
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.4287486993
Short name T740
Test name
Test status
Simulation time 35941741 ps
CPU time 3.61 seconds
Started Feb 08 12:54:18 PM UTC 25
Finished Feb 08 12:54:23 PM UTC 25
Peak memory 218344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287486993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4287486993
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.959503125
Short name T741
Test name
Test status
Simulation time 53231792 ps
CPU time 2.74 seconds
Started Feb 08 12:54:20 PM UTC 25
Finished Feb 08 12:54:24 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959503125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_syn
c_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.959503125
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.2558191869
Short name T753
Test name
Test status
Simulation time 47297070 ps
CPU time 1.27 seconds
Started Feb 08 12:54:27 PM UTC 25
Finished Feb 08 12:54:30 PM UTC 25
Peak memory 214756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558191869 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2558191869
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.2321111893
Short name T344
Test name
Test status
Simulation time 66864244 ps
CPU time 3.78 seconds
Started Feb 08 12:54:25 PM UTC 25
Finished Feb 08 12:54:30 PM UTC 25
Peak memory 228836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321111893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 38.keymgr_custom_cm.2321111893
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.1745489333
Short name T757
Test name
Test status
Simulation time 117816020 ps
CPU time 5.19 seconds
Started Feb 08 12:54:25 PM UTC 25
Finished Feb 08 12:54:31 PM UTC 25
Peak memory 218344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745489333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1745489333
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.2661760517
Short name T749
Test name
Test status
Simulation time 31157902 ps
CPU time 1.96 seconds
Started Feb 08 12:54:25 PM UTC 25
Finished Feb 08 12:54:28 PM UTC 25
Peak memory 224008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661760517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2661760517
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.1537945435
Short name T751
Test name
Test status
Simulation time 69767922 ps
CPU time 3.04 seconds
Started Feb 08 12:54:25 PM UTC 25
Finished Feb 08 12:54:29 PM UTC 25
Peak memory 224340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537945435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1537945435
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.1620191156
Short name T750
Test name
Test status
Simulation time 64123577 ps
CPU time 2.8 seconds
Started Feb 08 12:54:25 PM UTC 25
Finished Feb 08 12:54:29 PM UTC 25
Peak memory 224344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620191156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 38.keymgr_lc_disable.1620191156
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_random.2049936261
Short name T802
Test name
Test status
Simulation time 856399008 ps
CPU time 29.45 seconds
Started Feb 08 12:54:24 PM UTC 25
Finished Feb 08 12:54:55 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049936261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.keymgr_random.2049936261
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.1054910408
Short name T747
Test name
Test status
Simulation time 57769450 ps
CPU time 4.19 seconds
Started Feb 08 12:54:22 PM UTC 25
Finished Feb 08 12:54:28 PM UTC 25
Peak memory 216156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054910408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.keymgr_sideload.1054910408
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.1323820408
Short name T752
Test name
Test status
Simulation time 580052778 ps
CPU time 4.94 seconds
Started Feb 08 12:54:23 PM UTC 25
Finished Feb 08 12:54:30 PM UTC 25
Peak memory 216116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323820408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1323820408
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.2791091969
Short name T745
Test name
Test status
Simulation time 154041023 ps
CPU time 3.31 seconds
Started Feb 08 12:54:22 PM UTC 25
Finished Feb 08 12:54:27 PM UTC 25
Peak memory 216148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791091969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2791091969
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.1439103843
Short name T748
Test name
Test status
Simulation time 57803129 ps
CPU time 3.18 seconds
Started Feb 08 12:54:24 PM UTC 25
Finished Feb 08 12:54:28 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439103843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1439103843
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.2705164667
Short name T754
Test name
Test status
Simulation time 129355481 ps
CPU time 2.25 seconds
Started Feb 08 12:54:26 PM UTC 25
Finished Feb 08 12:54:30 PM UTC 25
Peak memory 228600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705164667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2705164667
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.3137914684
Short name T743
Test name
Test status
Simulation time 137610261 ps
CPU time 1.9 seconds
Started Feb 08 12:54:22 PM UTC 25
Finished Feb 08 12:54:26 PM UTC 25
Peak memory 215836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137914684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.keymgr_smoke.3137914684
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.2434729063
Short name T801
Test name
Test status
Simulation time 514943311 ps
CPU time 26.69 seconds
Started Feb 08 12:54:26 PM UTC 25
Finished Feb 08 12:54:55 PM UTC 25
Peak memory 228568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434729063 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2434729063
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.3027194190
Short name T769
Test name
Test status
Simulation time 772408363 ps
CPU time 11.61 seconds
Started Feb 08 12:54:26 PM UTC 25
Finished Feb 08 12:54:40 PM UTC 25
Peak memory 232688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3027194190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand
_reset.3027194190
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.2279430960
Short name T758
Test name
Test status
Simulation time 605365925 ps
CPU time 5.58 seconds
Started Feb 08 12:54:25 PM UTC 25
Finished Feb 08 12:54:32 PM UTC 25
Peak memory 216436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279430960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2279430960
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.2036929355
Short name T755
Test name
Test status
Simulation time 352622084 ps
CPU time 2.96 seconds
Started Feb 08 12:54:26 PM UTC 25
Finished Feb 08 12:54:30 PM UTC 25
Peak memory 220360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036929355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2036929355
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.917848455
Short name T766
Test name
Test status
Simulation time 27354296 ps
CPU time 1.27 seconds
Started Feb 08 12:54:36 PM UTC 25
Finished Feb 08 12:54:39 PM UTC 25
Peak memory 214096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917848455 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.917848455
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.608305905
Short name T759
Test name
Test status
Simulation time 25088051 ps
CPU time 2.37 seconds
Started Feb 08 12:54:31 PM UTC 25
Finished Feb 08 12:54:35 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608305905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.608305905
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.2313765375
Short name T262
Test name
Test status
Simulation time 894145505 ps
CPU time 11.73 seconds
Started Feb 08 12:54:31 PM UTC 25
Finished Feb 08 12:54:44 PM UTC 25
Peak memory 224464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313765375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2313765375
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.1052750568
Short name T763
Test name
Test status
Simulation time 374670065 ps
CPU time 4.92 seconds
Started Feb 08 12:54:31 PM UTC 25
Finished Feb 08 12:54:37 PM UTC 25
Peak memory 224340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052750568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1052750568
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.2726952663
Short name T764
Test name
Test status
Simulation time 216294744 ps
CPU time 5.38 seconds
Started Feb 08 12:54:31 PM UTC 25
Finished Feb 08 12:54:38 PM UTC 25
Peak memory 218256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726952663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 39.keymgr_lc_disable.2726952663
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_random.1129374598
Short name T770
Test name
Test status
Simulation time 196199957 ps
CPU time 8.7 seconds
Started Feb 08 12:54:30 PM UTC 25
Finished Feb 08 12:54:40 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129374598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.keymgr_random.1129374598
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.3541462260
Short name T765
Test name
Test status
Simulation time 691240905 ps
CPU time 7.65 seconds
Started Feb 08 12:54:28 PM UTC 25
Finished Feb 08 12:54:38 PM UTC 25
Peak memory 218340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541462260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.keymgr_sideload.3541462260
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.70018348
Short name T746
Test name
Test status
Simulation time 1006968476 ps
CPU time 26.36 seconds
Started Feb 08 12:54:28 PM UTC 25
Finished Feb 08 12:54:57 PM UTC 25
Peak memory 216176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70018348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_T
EST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.70018348
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.934439464
Short name T768
Test name
Test status
Simulation time 1215227914 ps
CPU time 8.71 seconds
Started Feb 08 12:54:28 PM UTC 25
Finished Feb 08 12:54:39 PM UTC 25
Peak memory 218316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934439464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.934439464
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.4154731053
Short name T767
Test name
Test status
Simulation time 336537052 ps
CPU time 8.75 seconds
Started Feb 08 12:54:29 PM UTC 25
Finished Feb 08 12:54:39 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154731053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4154731053
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.1867572619
Short name T762
Test name
Test status
Simulation time 58729951 ps
CPU time 3.44 seconds
Started Feb 08 12:54:32 PM UTC 25
Finished Feb 08 12:54:37 PM UTC 25
Peak memory 223708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867572619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1867572619
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.2682173357
Short name T760
Test name
Test status
Simulation time 134671835 ps
CPU time 5.29 seconds
Started Feb 08 12:54:28 PM UTC 25
Finished Feb 08 12:54:35 PM UTC 25
Peak memory 218456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682173357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.keymgr_smoke.2682173357
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all_with_rand_reset.249575089
Short name T785
Test name
Test status
Simulation time 281756058 ps
CPU time 11.6 seconds
Started Feb 08 12:54:35 PM UTC 25
Finished Feb 08 12:54:48 PM UTC 25
Peak memory 232684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=249575089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_
reset.249575089
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.3104009175
Short name T818
Test name
Test status
Simulation time 1176139103 ps
CPU time 30.5 seconds
Started Feb 08 12:54:31 PM UTC 25
Finished Feb 08 12:55:03 PM UTC 25
Peak memory 226696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104009175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3104009175
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.99318064
Short name T761
Test name
Test status
Simulation time 65261743 ps
CPU time 2.6 seconds
Started Feb 08 12:54:32 PM UTC 25
Finished Feb 08 12:54:36 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99318064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync
_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.99318064
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.411027391
Short name T463
Test name
Test status
Simulation time 19625275 ps
CPU time 1 seconds
Started Feb 08 12:48:59 PM UTC 25
Finished Feb 08 12:49:02 PM UTC 25
Peak memory 214028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411027391 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.411027391
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.589481915
Short name T29
Test name
Test status
Simulation time 132834415 ps
CPU time 6.95 seconds
Started Feb 08 12:48:51 PM UTC 25
Finished Feb 08 12:48:59 PM UTC 25
Peak memory 232308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589481915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cus
tom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.keymgr_custom_cm.589481915
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.436996105
Short name T52
Test name
Test status
Simulation time 65498824 ps
CPU time 2.16 seconds
Started Feb 08 12:48:44 PM UTC 25
Finished Feb 08 12:48:48 PM UTC 25
Peak memory 224468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436996105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.436996105
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.428747147
Short name T93
Test name
Test status
Simulation time 518493179 ps
CPU time 6.84 seconds
Started Feb 08 12:48:47 PM UTC 25
Finished Feb 08 12:48:56 PM UTC 25
Peak memory 232880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428747147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hws
w_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.428747147
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.1554527815
Short name T274
Test name
Test status
Simulation time 116300866 ps
CPU time 2.94 seconds
Started Feb 08 12:48:49 PM UTC 25
Finished Feb 08 12:48:53 PM UTC 25
Peak memory 224488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554527815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1554527815
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.2615348643
Short name T146
Test name
Test status
Simulation time 244698069 ps
CPU time 5.95 seconds
Started Feb 08 12:48:47 PM UTC 25
Finished Feb 08 12:48:55 PM UTC 25
Peak memory 220116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615348643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 4.keymgr_lc_disable.2615348643
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_random.810957712
Short name T225
Test name
Test status
Simulation time 402926978 ps
CPU time 7.06 seconds
Started Feb 08 12:48:41 PM UTC 25
Finished Feb 08 12:48:50 PM UTC 25
Peak memory 224392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810957712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.keymgr_random.810957712
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.848582097
Short name T47
Test name
Test status
Simulation time 1131189144 ps
CPU time 12.38 seconds
Started Feb 08 12:48:58 PM UTC 25
Finished Feb 08 12:49:12 PM UTC 25
Peak memory 260444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848582097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.848582097
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.1472864839
Short name T280
Test name
Test status
Simulation time 1390814173 ps
CPU time 7.31 seconds
Started Feb 08 12:48:37 PM UTC 25
Finished Feb 08 12:48:46 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472864839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.keymgr_sideload.1472864839
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.1238725346
Short name T326
Test name
Test status
Simulation time 2403239973 ps
CPU time 26.54 seconds
Started Feb 08 12:48:38 PM UTC 25
Finished Feb 08 12:49:07 PM UTC 25
Peak memory 218576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238725346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1238725346
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.4036766609
Short name T86
Test name
Test status
Simulation time 1453647548 ps
CPU time 39.28 seconds
Started Feb 08 12:48:38 PM UTC 25
Finished Feb 08 12:49:20 PM UTC 25
Peak memory 216264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036766609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4036766609
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.1787759793
Short name T212
Test name
Test status
Simulation time 102416156 ps
CPU time 4.38 seconds
Started Feb 08 12:48:39 PM UTC 25
Finished Feb 08 12:48:46 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787759793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1787759793
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.1394030815
Short name T390
Test name
Test status
Simulation time 100589459 ps
CPU time 2.63 seconds
Started Feb 08 12:48:54 PM UTC 25
Finished Feb 08 12:48:58 PM UTC 25
Peak memory 216372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394030815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1394030815
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.2590416244
Short name T462
Test name
Test status
Simulation time 166303693 ps
CPU time 2.59 seconds
Started Feb 08 12:48:36 PM UTC 25
Finished Feb 08 12:48:40 PM UTC 25
Peak memory 216464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590416244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.keymgr_smoke.2590416244
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.2519386810
Short name T228
Test name
Test status
Simulation time 414889961 ps
CPU time 6.41 seconds
Started Feb 08 12:48:47 PM UTC 25
Finished Feb 08 12:48:55 PM UTC 25
Peak memory 230876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519386810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2519386810
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.4202196019
Short name T68
Test name
Test status
Simulation time 458581946 ps
CPU time 4.45 seconds
Started Feb 08 12:48:55 PM UTC 25
Finished Feb 08 12:49:01 PM UTC 25
Peak memory 220428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202196019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.4202196019
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.2843206014
Short name T784
Test name
Test status
Simulation time 57322929 ps
CPU time 1.38 seconds
Started Feb 08 12:54:43 PM UTC 25
Finished Feb 08 12:54:46 PM UTC 25
Peak memory 214148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843206014 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2843206014
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.1553292276
Short name T449
Test name
Test status
Simulation time 247668750 ps
CPU time 4.8 seconds
Started Feb 08 12:54:39 PM UTC 25
Finished Feb 08 12:54:45 PM UTC 25
Peak memory 232640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553292276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1553292276
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.124043485
Short name T775
Test name
Test status
Simulation time 57380344 ps
CPU time 2.75 seconds
Started Feb 08 12:54:39 PM UTC 25
Finished Feb 08 12:54:43 PM UTC 25
Peak memory 224464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124043485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.124043485
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.529076063
Short name T781
Test name
Test status
Simulation time 359332048 ps
CPU time 4.3 seconds
Started Feb 08 12:54:40 PM UTC 25
Finished Feb 08 12:54:46 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529076063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hws
w_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.529076063
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.1144680270
Short name T778
Test name
Test status
Simulation time 205984731 ps
CPU time 2.44 seconds
Started Feb 08 12:54:41 PM UTC 25
Finished Feb 08 12:54:45 PM UTC 25
Peak memory 226456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144680270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1144680270
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.277451735
Short name T779
Test name
Test status
Simulation time 386610075 ps
CPU time 3.89 seconds
Started Feb 08 12:54:40 PM UTC 25
Finished Feb 08 12:54:45 PM UTC 25
Peak memory 226448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277451735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 40.keymgr_lc_disable.277451735
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_random.2197834666
Short name T783
Test name
Test status
Simulation time 173764400 ps
CPU time 6.06 seconds
Started Feb 08 12:54:39 PM UTC 25
Finished Feb 08 12:54:46 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197834666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.keymgr_random.2197834666
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.1329398996
Short name T774
Test name
Test status
Simulation time 304355357 ps
CPU time 3.56 seconds
Started Feb 08 12:54:37 PM UTC 25
Finished Feb 08 12:54:42 PM UTC 25
Peak memory 218404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329398996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.keymgr_sideload.1329398996
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.2211758989
Short name T772
Test name
Test status
Simulation time 77781098 ps
CPU time 2.49 seconds
Started Feb 08 12:54:38 PM UTC 25
Finished Feb 08 12:54:41 PM UTC 25
Peak memory 216128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211758989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2211758989
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.2641993756
Short name T773
Test name
Test status
Simulation time 217082999 ps
CPU time 3.24 seconds
Started Feb 08 12:54:38 PM UTC 25
Finished Feb 08 12:54:42 PM UTC 25
Peak memory 218324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641993756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2641993756
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.770823038
Short name T777
Test name
Test status
Simulation time 139762109 ps
CPU time 4.64 seconds
Started Feb 08 12:54:38 PM UTC 25
Finished Feb 08 12:54:44 PM UTC 25
Peak memory 218316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770823038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.770823038
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.1076780255
Short name T782
Test name
Test status
Simulation time 16890342 ps
CPU time 2.25 seconds
Started Feb 08 12:54:42 PM UTC 25
Finished Feb 08 12:54:46 PM UTC 25
Peak memory 224468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076780255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1076780255
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.686357433
Short name T771
Test name
Test status
Simulation time 278446215 ps
CPU time 2.22 seconds
Started Feb 08 12:54:37 PM UTC 25
Finished Feb 08 12:54:41 PM UTC 25
Peak memory 218608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686357433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.keymgr_smoke.686357433
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.3063582631
Short name T346
Test name
Test status
Simulation time 4421299591 ps
CPU time 30.97 seconds
Started Feb 08 12:54:43 PM UTC 25
Finished Feb 08 12:55:16 PM UTC 25
Peak memory 232880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063582631 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3063582631
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.899180740
Short name T304
Test name
Test status
Simulation time 158713730 ps
CPU time 4.19 seconds
Started Feb 08 12:54:40 PM UTC 25
Finished Feb 08 12:54:46 PM UTC 25
Peak memory 218628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899180740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_
invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.899180740
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.1816599643
Short name T780
Test name
Test status
Simulation time 78753856 ps
CPU time 1.65 seconds
Started Feb 08 12:54:42 PM UTC 25
Finished Feb 08 12:54:45 PM UTC 25
Peak memory 218028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816599643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1816599643
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.548454078
Short name T796
Test name
Test status
Simulation time 53900863 ps
CPU time 1.19 seconds
Started Feb 08 12:54:50 PM UTC 25
Finished Feb 08 12:54:53 PM UTC 25
Peak memory 214144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548454078 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.548454078
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.313029312
Short name T345
Test name
Test status
Simulation time 67018705 ps
CPU time 3.3 seconds
Started Feb 08 12:54:46 PM UTC 25
Finished Feb 08 12:54:51 PM UTC 25
Peak memory 224508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313029312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.313029312
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.2370754298
Short name T75
Test name
Test status
Simulation time 258824802 ps
CPU time 7.4 seconds
Started Feb 08 12:54:47 PM UTC 25
Finished Feb 08 12:54:56 PM UTC 25
Peak memory 218528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370754298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 41.keymgr_custom_cm.2370754298
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.1261899465
Short name T789
Test name
Test status
Simulation time 259110674 ps
CPU time 2.98 seconds
Started Feb 08 12:54:46 PM UTC 25
Finished Feb 08 12:54:50 PM UTC 25
Peak memory 218244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261899465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1261899465
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.499035886
Short name T803
Test name
Test status
Simulation time 124890809 ps
CPU time 6.24 seconds
Started Feb 08 12:54:47 PM UTC 25
Finished Feb 08 12:54:55 PM UTC 25
Peak memory 226436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499035886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hws
w_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.499035886
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.144870393
Short name T794
Test name
Test status
Simulation time 105762904 ps
CPU time 3.7 seconds
Started Feb 08 12:54:47 PM UTC 25
Finished Feb 08 12:54:52 PM UTC 25
Peak memory 224412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144870393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.144870393
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.3464610848
Short name T795
Test name
Test status
Simulation time 405581525 ps
CPU time 4.1 seconds
Started Feb 08 12:54:47 PM UTC 25
Finished Feb 08 12:54:53 PM UTC 25
Peak memory 224400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464610848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 41.keymgr_lc_disable.3464610848
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_random.2669509341
Short name T799
Test name
Test status
Simulation time 4321058337 ps
CPU time 6.78 seconds
Started Feb 08 12:54:46 PM UTC 25
Finished Feb 08 12:54:54 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669509341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.keymgr_random.2669509341
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.3689534032
Short name T787
Test name
Test status
Simulation time 107601878 ps
CPU time 2.89 seconds
Started Feb 08 12:54:44 PM UTC 25
Finished Feb 08 12:54:49 PM UTC 25
Peak memory 218244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689534032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.keymgr_sideload.3689534032
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.726521291
Short name T792
Test name
Test status
Simulation time 705441864 ps
CPU time 4.44 seconds
Started Feb 08 12:54:46 PM UTC 25
Finished Feb 08 12:54:52 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726521291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.726521291
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.3650720895
Short name T798
Test name
Test status
Simulation time 422003378 ps
CPU time 6.91 seconds
Started Feb 08 12:54:45 PM UTC 25
Finished Feb 08 12:54:54 PM UTC 25
Peak memory 218268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650720895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3650720895
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.3344970964
Short name T788
Test name
Test status
Simulation time 39905404 ps
CPU time 2.31 seconds
Started Feb 08 12:54:46 PM UTC 25
Finished Feb 08 12:54:50 PM UTC 25
Peak memory 216288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344970964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3344970964
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.1015090444
Short name T797
Test name
Test status
Simulation time 285372087 ps
CPU time 4.63 seconds
Started Feb 08 12:54:47 PM UTC 25
Finished Feb 08 12:54:53 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015090444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1015090444
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.975077244
Short name T791
Test name
Test status
Simulation time 482108330 ps
CPU time 5.07 seconds
Started Feb 08 12:54:44 PM UTC 25
Finished Feb 08 12:54:52 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975077244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 41.keymgr_smoke.975077244
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.4075012745
Short name T255
Test name
Test status
Simulation time 10765259179 ps
CPU time 321.2 seconds
Started Feb 08 12:54:49 PM UTC 25
Finished Feb 08 01:00:15 PM UTC 25
Peak memory 230600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075012745 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4075012745
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.3394937210
Short name T793
Test name
Test status
Simulation time 180328483 ps
CPU time 3.4 seconds
Started Feb 08 12:54:47 PM UTC 25
Finished Feb 08 12:54:52 PM UTC 25
Peak memory 216460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394937210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3394937210
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.2433229507
Short name T790
Test name
Test status
Simulation time 84690524 ps
CPU time 2.42 seconds
Started Feb 08 12:54:47 PM UTC 25
Finished Feb 08 12:54:51 PM UTC 25
Peak memory 220512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433229507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2433229507
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.49804402
Short name T806
Test name
Test status
Simulation time 30708374 ps
CPU time 1.16 seconds
Started Feb 08 12:54:56 PM UTC 25
Finished Feb 08 12:54:59 PM UTC 25
Peak memory 214756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49804402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.49804402
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.1707593534
Short name T815
Test name
Test status
Simulation time 263195089 ps
CPU time 6.07 seconds
Started Feb 08 12:54:55 PM UTC 25
Finished Feb 08 12:55:02 PM UTC 25
Peak memory 224480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707593534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 42.keymgr_custom_cm.1707593534
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.4193172972
Short name T805
Test name
Test status
Simulation time 964883941 ps
CPU time 4.35 seconds
Started Feb 08 12:54:53 PM UTC 25
Finished Feb 08 12:54:59 PM UTC 25
Peak memory 218492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193172972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.4193172972
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.1460420001
Short name T261
Test name
Test status
Simulation time 84455929 ps
CPU time 3.66 seconds
Started Feb 08 12:54:54 PM UTC 25
Finished Feb 08 12:54:59 PM UTC 25
Peak memory 226520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460420001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1460420001
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.520564752
Short name T813
Test name
Test status
Simulation time 319372031 ps
CPU time 5.44 seconds
Started Feb 08 12:54:55 PM UTC 25
Finished Feb 08 12:55:02 PM UTC 25
Peak memory 232600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520564752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.520564752
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.315536384
Short name T244
Test name
Test status
Simulation time 136283202 ps
CPU time 4.44 seconds
Started Feb 08 12:54:54 PM UTC 25
Finished Feb 08 12:55:00 PM UTC 25
Peak memory 226524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315536384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 42.keymgr_lc_disable.315536384
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_random.1603864136
Short name T814
Test name
Test status
Simulation time 239423197 ps
CPU time 7.75 seconds
Started Feb 08 12:54:53 PM UTC 25
Finished Feb 08 12:55:02 PM UTC 25
Peak memory 218340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603864136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.keymgr_random.1603864136
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.2539280695
Short name T800
Test name
Test status
Simulation time 262526352 ps
CPU time 2.36 seconds
Started Feb 08 12:54:50 PM UTC 25
Finished Feb 08 12:54:54 PM UTC 25
Peak memory 216532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539280695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.keymgr_sideload.2539280695
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.3306209581
Short name T804
Test name
Test status
Simulation time 38020014 ps
CPU time 2.15 seconds
Started Feb 08 12:54:52 PM UTC 25
Finished Feb 08 12:54:55 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306209581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3306209581
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.4030428748
Short name T810
Test name
Test status
Simulation time 483211147 ps
CPU time 6.99 seconds
Started Feb 08 12:54:51 PM UTC 25
Finished Feb 08 12:55:00 PM UTC 25
Peak memory 218448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030428748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.4030428748
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.225750528
Short name T808
Test name
Test status
Simulation time 385223926 ps
CPU time 4.88 seconds
Started Feb 08 12:54:53 PM UTC 25
Finished Feb 08 12:54:59 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225750528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.225750528
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.2403951490
Short name T807
Test name
Test status
Simulation time 89269232 ps
CPU time 2.5 seconds
Started Feb 08 12:54:55 PM UTC 25
Finished Feb 08 12:54:59 PM UTC 25
Peak memory 216276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403951490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2403951490
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.2235489833
Short name T786
Test name
Test status
Simulation time 875779739 ps
CPU time 5.87 seconds
Started Feb 08 12:54:50 PM UTC 25
Finished Feb 08 12:54:58 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235489833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.keymgr_smoke.2235489833
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.889652473
Short name T821
Test name
Test status
Simulation time 172507600 ps
CPU time 8.36 seconds
Started Feb 08 12:54:54 PM UTC 25
Finished Feb 08 12:55:04 PM UTC 25
Peak memory 226532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889652473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_
invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.889652473
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.227638718
Short name T824
Test name
Test status
Simulation time 54496946 ps
CPU time 1.04 seconds
Started Feb 08 12:55:03 PM UTC 25
Finished Feb 08 12:55:06 PM UTC 25
Peak memory 213964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227638718 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.227638718
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.4034947105
Short name T425
Test name
Test status
Simulation time 176761070 ps
CPU time 4.29 seconds
Started Feb 08 12:55:00 PM UTC 25
Finished Feb 08 12:55:06 PM UTC 25
Peak memory 232680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034947105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4034947105
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.992381706
Short name T834
Test name
Test status
Simulation time 136999570 ps
CPU time 7.63 seconds
Started Feb 08 12:55:01 PM UTC 25
Finished Feb 08 12:55:11 PM UTC 25
Peak memory 218332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992381706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cus
tom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.keymgr_custom_cm.992381706
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.3400255405
Short name T822
Test name
Test status
Simulation time 199318821 ps
CPU time 2.94 seconds
Started Feb 08 12:55:00 PM UTC 25
Finished Feb 08 12:55:05 PM UTC 25
Peak memory 226440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400255405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3400255405
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.2158362370
Short name T823
Test name
Test status
Simulation time 118608402 ps
CPU time 2.26 seconds
Started Feb 08 12:55:01 PM UTC 25
Finished Feb 08 12:55:05 PM UTC 25
Peak memory 224392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158362370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2158362370
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.2405584540
Short name T378
Test name
Test status
Simulation time 140888926 ps
CPU time 3.36 seconds
Started Feb 08 12:55:01 PM UTC 25
Finished Feb 08 12:55:06 PM UTC 25
Peak memory 226456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405584540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2405584540
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.621699563
Short name T826
Test name
Test status
Simulation time 204633726 ps
CPU time 4.7 seconds
Started Feb 08 12:55:00 PM UTC 25
Finished Feb 08 12:55:07 PM UTC 25
Peak memory 218260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621699563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 43.keymgr_lc_disable.621699563
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_random.1902891578
Short name T831
Test name
Test status
Simulation time 128824420 ps
CPU time 6.63 seconds
Started Feb 08 12:55:00 PM UTC 25
Finished Feb 08 12:55:08 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902891578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.keymgr_random.1902891578
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.2523208911
Short name T817
Test name
Test status
Simulation time 319535138 ps
CPU time 3.13 seconds
Started Feb 08 12:54:57 PM UTC 25
Finished Feb 08 12:55:02 PM UTC 25
Peak memory 216468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523208911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.keymgr_sideload.2523208911
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.190780844
Short name T820
Test name
Test status
Simulation time 372249886 ps
CPU time 3.32 seconds
Started Feb 08 12:54:58 PM UTC 25
Finished Feb 08 12:55:04 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190780844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.190780844
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.3753480805
Short name T819
Test name
Test status
Simulation time 344154479 ps
CPU time 4.32 seconds
Started Feb 08 12:54:57 PM UTC 25
Finished Feb 08 12:55:04 PM UTC 25
Peak memory 218336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753480805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3753480805
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.909392136
Short name T825
Test name
Test status
Simulation time 122360598 ps
CPU time 4.75 seconds
Started Feb 08 12:55:00 PM UTC 25
Finished Feb 08 12:55:07 PM UTC 25
Peak memory 216500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909392136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.909392136
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.3272211569
Short name T827
Test name
Test status
Simulation time 695906111 ps
CPU time 3.18 seconds
Started Feb 08 12:55:02 PM UTC 25
Finished Feb 08 12:55:07 PM UTC 25
Peak memory 226516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272211569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3272211569
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.1292030330
Short name T811
Test name
Test status
Simulation time 63274673 ps
CPU time 2.88 seconds
Started Feb 08 12:54:56 PM UTC 25
Finished Feb 08 12:55:01 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292030330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.keymgr_smoke.1292030330
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.3682133549
Short name T853
Test name
Test status
Simulation time 430441251 ps
CPU time 15.15 seconds
Started Feb 08 12:55:03 PM UTC 25
Finished Feb 08 12:55:20 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682133549 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3682133549
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all_with_rand_reset.2147825576
Short name T253
Test name
Test status
Simulation time 1339015379 ps
CPU time 26.21 seconds
Started Feb 08 12:55:03 PM UTC 25
Finished Feb 08 12:55:31 PM UTC 25
Peak memory 232952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2147825576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand
_reset.2147825576
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.1556334953
Short name T830
Test name
Test status
Simulation time 136502029 ps
CPU time 6.03 seconds
Started Feb 08 12:55:00 PM UTC 25
Finished Feb 08 12:55:08 PM UTC 25
Peak memory 218348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556334953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1556334953
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.4243158623
Short name T828
Test name
Test status
Simulation time 366254464 ps
CPU time 2.56 seconds
Started Feb 08 12:55:03 PM UTC 25
Finished Feb 08 12:55:07 PM UTC 25
Peak memory 218692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243158623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.4243158623
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.1370136370
Short name T839
Test name
Test status
Simulation time 18182133 ps
CPU time 0.97 seconds
Started Feb 08 12:55:10 PM UTC 25
Finished Feb 08 12:55:13 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370136370 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1370136370
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.3564493489
Short name T836
Test name
Test status
Simulation time 69665200 ps
CPU time 2.88 seconds
Started Feb 08 12:55:07 PM UTC 25
Finished Feb 08 12:55:11 PM UTC 25
Peak memory 224464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564493489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3564493489
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.2067156223
Short name T838
Test name
Test status
Simulation time 132116433 ps
CPU time 3.93 seconds
Started Feb 08 12:55:07 PM UTC 25
Finished Feb 08 12:55:12 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067156223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2067156223
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.2828545323
Short name T843
Test name
Test status
Simulation time 157008909 ps
CPU time 4.06 seconds
Started Feb 08 12:55:08 PM UTC 25
Finished Feb 08 12:55:13 PM UTC 25
Peak memory 224208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828545323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2828545323
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.1982310039
Short name T840
Test name
Test status
Simulation time 410370446 ps
CPU time 3.21 seconds
Started Feb 08 12:55:08 PM UTC 25
Finished Feb 08 12:55:13 PM UTC 25
Peak memory 226372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982310039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1982310039
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.1118023434
Short name T841
Test name
Test status
Simulation time 146705580 ps
CPU time 3.44 seconds
Started Feb 08 12:55:08 PM UTC 25
Finished Feb 08 12:55:13 PM UTC 25
Peak memory 218032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118023434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 44.keymgr_lc_disable.1118023434
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_random.682320122
Short name T842
Test name
Test status
Simulation time 427309388 ps
CPU time 4.91 seconds
Started Feb 08 12:55:07 PM UTC 25
Finished Feb 08 12:55:13 PM UTC 25
Peak memory 230636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682320122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.keymgr_random.682320122
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.750414096
Short name T851
Test name
Test status
Simulation time 1971566438 ps
CPU time 13.31 seconds
Started Feb 08 12:55:04 PM UTC 25
Finished Feb 08 12:55:19 PM UTC 25
Peak memory 216204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750414096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 44.keymgr_sideload.750414096
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.2230548216
Short name T837
Test name
Test status
Simulation time 384659095 ps
CPU time 6.09 seconds
Started Feb 08 12:55:04 PM UTC 25
Finished Feb 08 12:55:12 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230548216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2230548216
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.558980256
Short name T829
Test name
Test status
Simulation time 22565247 ps
CPU time 1.91 seconds
Started Feb 08 12:55:04 PM UTC 25
Finished Feb 08 12:55:08 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558980256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.558980256
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.2630001515
Short name T835
Test name
Test status
Simulation time 77578616 ps
CPU time 3.85 seconds
Started Feb 08 12:55:05 PM UTC 25
Finished Feb 08 12:55:11 PM UTC 25
Peak memory 216196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630001515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2630001515
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.2203921624
Short name T844
Test name
Test status
Simulation time 227645782 ps
CPU time 3.42 seconds
Started Feb 08 12:55:09 PM UTC 25
Finished Feb 08 12:55:14 PM UTC 25
Peak memory 218252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203921624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2203921624
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.935749091
Short name T832
Test name
Test status
Simulation time 155687443 ps
CPU time 3.7 seconds
Started Feb 08 12:55:04 PM UTC 25
Finished Feb 08 12:55:10 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935749091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.keymgr_smoke.935749091
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.1032674740
Short name T845
Test name
Test status
Simulation time 141939905 ps
CPU time 5.55 seconds
Started Feb 08 12:55:09 PM UTC 25
Finished Feb 08 12:55:16 PM UTC 25
Peak memory 230536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032674740 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1032674740
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.4189334200
Short name T876
Test name
Test status
Simulation time 1132072693 ps
CPU time 23.88 seconds
Started Feb 08 12:55:08 PM UTC 25
Finished Feb 08 12:55:34 PM UTC 25
Peak memory 228568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189334200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.4189334200
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.2386601348
Short name T877
Test name
Test status
Simulation time 3999108799 ps
CPU time 23.25 seconds
Started Feb 08 12:55:09 PM UTC 25
Finished Feb 08 12:55:34 PM UTC 25
Peak memory 220424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386601348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2386601348
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.2457894633
Short name T856
Test name
Test status
Simulation time 66633574 ps
CPU time 1.24 seconds
Started Feb 08 12:55:18 PM UTC 25
Finished Feb 08 12:55:21 PM UTC 25
Peak memory 214756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457894633 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2457894633
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.1708627915
Short name T455
Test name
Test status
Simulation time 103716899 ps
CPU time 4.63 seconds
Started Feb 08 12:55:14 PM UTC 25
Finished Feb 08 12:55:20 PM UTC 25
Peak memory 224544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708627915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1708627915
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.2410509067
Short name T25
Test name
Test status
Simulation time 147682528 ps
CPU time 2.04 seconds
Started Feb 08 12:55:15 PM UTC 25
Finished Feb 08 12:55:18 PM UTC 25
Peak memory 216552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410509067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 45.keymgr_custom_cm.2410509067
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.548490360
Short name T848
Test name
Test status
Simulation time 22573404 ps
CPU time 2.23 seconds
Started Feb 08 12:55:14 PM UTC 25
Finished Feb 08 12:55:17 PM UTC 25
Peak memory 224456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548490360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_dir
ect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.548490360
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.1429635105
Short name T852
Test name
Test status
Simulation time 448742755 ps
CPU time 4.26 seconds
Started Feb 08 12:55:14 PM UTC 25
Finished Feb 08 12:55:19 PM UTC 25
Peak memory 218296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429635105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1429635105
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.2369242967
Short name T849
Test name
Test status
Simulation time 28612745 ps
CPU time 2.36 seconds
Started Feb 08 12:55:15 PM UTC 25
Finished Feb 08 12:55:19 PM UTC 25
Peak memory 224412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369242967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2369242967
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_random.492309561
Short name T906
Test name
Test status
Simulation time 1722363130 ps
CPU time 36.93 seconds
Started Feb 08 12:55:14 PM UTC 25
Finished Feb 08 12:55:52 PM UTC 25
Peak memory 218252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492309561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ran
dom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.keymgr_random.492309561
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.1371328228
Short name T854
Test name
Test status
Simulation time 754360815 ps
CPU time 7.76 seconds
Started Feb 08 12:55:11 PM UTC 25
Finished Feb 08 12:55:21 PM UTC 25
Peak memory 218516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371328228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.keymgr_sideload.1371328228
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.2307303980
Short name T847
Test name
Test status
Simulation time 387211337 ps
CPU time 4.28 seconds
Started Feb 08 12:55:11 PM UTC 25
Finished Feb 08 12:55:17 PM UTC 25
Peak memory 216264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307303980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2307303980
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.1744414540
Short name T850
Test name
Test status
Simulation time 2212941101 ps
CPU time 6.28 seconds
Started Feb 08 12:55:11 PM UTC 25
Finished Feb 08 12:55:19 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744414540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1744414540
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.3834585441
Short name T869
Test name
Test status
Simulation time 1896335593 ps
CPU time 13.42 seconds
Started Feb 08 12:55:12 PM UTC 25
Finished Feb 08 12:55:27 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834585441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3834585441
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.1869898412
Short name T858
Test name
Test status
Simulation time 458338966 ps
CPU time 5.14 seconds
Started Feb 08 12:55:15 PM UTC 25
Finished Feb 08 12:55:21 PM UTC 25
Peak memory 220372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869898412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1869898412
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.979191211
Short name T846
Test name
Test status
Simulation time 267328308 ps
CPU time 3.76 seconds
Started Feb 08 12:55:11 PM UTC 25
Finished Feb 08 12:55:17 PM UTC 25
Peak memory 218608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979191211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.keymgr_smoke.979191211
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.2486743558
Short name T861
Test name
Test status
Simulation time 146107814 ps
CPU time 5.87 seconds
Started Feb 08 12:55:17 PM UTC 25
Finished Feb 08 12:55:24 PM UTC 25
Peak memory 230920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486743558 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2486743558
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all_with_rand_reset.1056160124
Short name T833
Test name
Test status
Simulation time 144748287 ps
CPU time 9.77 seconds
Started Feb 08 12:55:17 PM UTC 25
Finished Feb 08 12:55:28 PM UTC 25
Peak memory 233052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1056160124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand
_reset.1056160124
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.1189946829
Short name T890
Test name
Test status
Simulation time 1013913978 ps
CPU time 27.42 seconds
Started Feb 08 12:55:14 PM UTC 25
Finished Feb 08 12:55:43 PM UTC 25
Peak memory 218496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189946829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1189946829
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.4044537087
Short name T857
Test name
Test status
Simulation time 45512168 ps
CPU time 2.92 seconds
Started Feb 08 12:55:17 PM UTC 25
Finished Feb 08 12:55:21 PM UTC 25
Peak memory 220400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044537087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4044537087
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.688263901
Short name T816
Test name
Test status
Simulation time 55329370 ps
CPU time 1.19 seconds
Started Feb 08 12:55:26 PM UTC 25
Finished Feb 08 12:55:29 PM UTC 25
Peak memory 214144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688263901 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.688263901
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.522212003
Short name T399
Test name
Test status
Simulation time 50460881 ps
CPU time 4.23 seconds
Started Feb 08 12:55:21 PM UTC 25
Finished Feb 08 12:55:27 PM UTC 25
Peak memory 226516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522212003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.522212003
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.2136811650
Short name T76
Test name
Test status
Simulation time 83027529 ps
CPU time 2.69 seconds
Started Feb 08 12:55:22 PM UTC 25
Finished Feb 08 12:55:26 PM UTC 25
Peak memory 232532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136811650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 46.keymgr_custom_cm.2136811650
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.4014985495
Short name T864
Test name
Test status
Simulation time 78006415 ps
CPU time 2.8 seconds
Started Feb 08 12:55:21 PM UTC 25
Finished Feb 08 12:55:25 PM UTC 25
Peak memory 216528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014985495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.4014985495
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.60782223
Short name T866
Test name
Test status
Simulation time 39716505 ps
CPU time 2.6 seconds
Started Feb 08 12:55:22 PM UTC 25
Finished Feb 08 12:55:26 PM UTC 25
Peak memory 226444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60782223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.60782223
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.2924047873
Short name T812
Test name
Test status
Simulation time 105822554 ps
CPU time 4.48 seconds
Started Feb 08 12:55:22 PM UTC 25
Finished Feb 08 12:55:28 PM UTC 25
Peak memory 231636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924047873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2924047873
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.556116610
Short name T863
Test name
Test status
Simulation time 338359863 ps
CPU time 2.76 seconds
Started Feb 08 12:55:21 PM UTC 25
Finished Feb 08 12:55:25 PM UTC 25
Peak memory 218332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556116610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 46.keymgr_lc_disable.556116610
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_random.4014092867
Short name T867
Test name
Test status
Simulation time 853155791 ps
CPU time 4.99 seconds
Started Feb 08 12:55:20 PM UTC 25
Finished Feb 08 12:55:26 PM UTC 25
Peak memory 216464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014092867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.keymgr_random.4014092867
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.1644891509
Short name T860
Test name
Test status
Simulation time 250645794 ps
CPU time 2.99 seconds
Started Feb 08 12:55:18 PM UTC 25
Finished Feb 08 12:55:23 PM UTC 25
Peak memory 218388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644891509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.keymgr_sideload.1644891509
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.3170375212
Short name T896
Test name
Test status
Simulation time 1013130581 ps
CPU time 25.37 seconds
Started Feb 08 12:55:20 PM UTC 25
Finished Feb 08 12:55:47 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170375212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3170375212
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.2501843830
Short name T862
Test name
Test status
Simulation time 114695854 ps
CPU time 3.62 seconds
Started Feb 08 12:55:20 PM UTC 25
Finished Feb 08 12:55:25 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501843830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2501843830
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.3960434662
Short name T868
Test name
Test status
Simulation time 747080838 ps
CPU time 5.22 seconds
Started Feb 08 12:55:20 PM UTC 25
Finished Feb 08 12:55:26 PM UTC 25
Peak memory 216196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960434662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3960434662
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.1536736073
Short name T855
Test name
Test status
Simulation time 404538641 ps
CPU time 4.69 seconds
Started Feb 08 12:55:22 PM UTC 25
Finished Feb 08 12:55:28 PM UTC 25
Peak memory 228680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536736073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1536736073
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.4118131621
Short name T859
Test name
Test status
Simulation time 34524785 ps
CPU time 2.58 seconds
Started Feb 08 12:55:18 PM UTC 25
Finished Feb 08 12:55:22 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118131621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.keymgr_smoke.4118131621
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.1327940634
Short name T416
Test name
Test status
Simulation time 774582973 ps
CPU time 31.37 seconds
Started Feb 08 12:55:23 PM UTC 25
Finished Feb 08 12:55:56 PM UTC 25
Peak memory 226704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327940634 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1327940634
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all_with_rand_reset.1960550150
Short name T891
Test name
Test status
Simulation time 950077995 ps
CPU time 16.8 seconds
Started Feb 08 12:55:24 PM UTC 25
Finished Feb 08 12:55:43 PM UTC 25
Peak memory 232788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1960550150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand
_reset.1960550150
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.1985627838
Short name T870
Test name
Test status
Simulation time 1157002185 ps
CPU time 7.6 seconds
Started Feb 08 12:55:21 PM UTC 25
Finished Feb 08 12:55:30 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985627838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1985627838
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.3844653238
Short name T158
Test name
Test status
Simulation time 1418053464 ps
CPU time 14.9 seconds
Started Feb 08 12:55:22 PM UTC 25
Finished Feb 08 12:55:39 PM UTC 25
Peak memory 220624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844653238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3844653238
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.1446018793
Short name T879
Test name
Test status
Simulation time 45873804 ps
CPU time 1.09 seconds
Started Feb 08 12:55:32 PM UTC 25
Finished Feb 08 12:55:34 PM UTC 25
Peak memory 214756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446018793 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1446018793
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.332093397
Short name T188
Test name
Test status
Simulation time 430119488 ps
CPU time 3.89 seconds
Started Feb 08 12:55:29 PM UTC 25
Finished Feb 08 12:55:35 PM UTC 25
Peak memory 233100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332093397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cus
tom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.keymgr_custom_cm.332093397
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.3299616887
Short name T875
Test name
Test status
Simulation time 51098984 ps
CPU time 3.03 seconds
Started Feb 08 12:55:28 PM UTC 25
Finished Feb 08 12:55:33 PM UTC 25
Peak memory 218164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299616887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3299616887
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.2085416180
Short name T880
Test name
Test status
Simulation time 292094687 ps
CPU time 4.69 seconds
Started Feb 08 12:55:28 PM UTC 25
Finished Feb 08 12:55:35 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085416180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2085416180
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.1944921871
Short name T878
Test name
Test status
Simulation time 57202856 ps
CPU time 2.69 seconds
Started Feb 08 12:55:29 PM UTC 25
Finished Feb 08 12:55:34 PM UTC 25
Peak memory 231412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944921871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1944921871
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.2745596298
Short name T873
Test name
Test status
Simulation time 144603095 ps
CPU time 2.24 seconds
Started Feb 08 12:55:28 PM UTC 25
Finished Feb 08 12:55:32 PM UTC 25
Peak memory 213872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745596298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 47.keymgr_lc_disable.2745596298
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_random.1430413555
Short name T874
Test name
Test status
Simulation time 166800339 ps
CPU time 3.43 seconds
Started Feb 08 12:55:27 PM UTC 25
Finished Feb 08 12:55:32 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430413555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 47.keymgr_random.1430413555
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.562399949
Short name T901
Test name
Test status
Simulation time 5314528857 ps
CPU time 20.16 seconds
Started Feb 08 12:55:26 PM UTC 25
Finished Feb 08 12:55:48 PM UTC 25
Peak memory 218388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562399949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sid
eload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 47.keymgr_sideload.562399949
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.1198124015
Short name T910
Test name
Test status
Simulation time 3579724948 ps
CPU time 27.39 seconds
Started Feb 08 12:55:27 PM UTC 25
Finished Feb 08 12:55:56 PM UTC 25
Peak memory 218556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198124015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1198124015
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.553256501
Short name T871
Test name
Test status
Simulation time 121705873 ps
CPU time 3.76 seconds
Started Feb 08 12:55:26 PM UTC 25
Finished Feb 08 12:55:31 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553256501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.553256501
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.2999898003
Short name T872
Test name
Test status
Simulation time 32475454 ps
CPU time 3.05 seconds
Started Feb 08 12:55:27 PM UTC 25
Finished Feb 08 12:55:32 PM UTC 25
Peak memory 214148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999898003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2999898003
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.3957113756
Short name T899
Test name
Test status
Simulation time 956374885 ps
CPU time 15.55 seconds
Started Feb 08 12:55:29 PM UTC 25
Finished Feb 08 12:55:47 PM UTC 25
Peak memory 218324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957113756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3957113756
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.440042794
Short name T809
Test name
Test status
Simulation time 61307330 ps
CPU time 3.01 seconds
Started Feb 08 12:55:26 PM UTC 25
Finished Feb 08 12:55:30 PM UTC 25
Peak memory 216316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440042794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.keymgr_smoke.440042794
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.399199590
Short name T335
Test name
Test status
Simulation time 1042751871 ps
CPU time 37.06 seconds
Started Feb 08 12:55:32 PM UTC 25
Finished Feb 08 12:56:11 PM UTC 25
Peak memory 226512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399199590 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.399199590
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.3862333554
Short name T881
Test name
Test status
Simulation time 86715023 ps
CPU time 4.94 seconds
Started Feb 08 12:55:28 PM UTC 25
Finished Feb 08 12:55:35 PM UTC 25
Peak memory 226464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862333554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3862333554
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.2078042824
Short name T221
Test name
Test status
Simulation time 303887694 ps
CPU time 5.09 seconds
Started Feb 08 12:55:29 PM UTC 25
Finished Feb 08 12:55:37 PM UTC 25
Peak memory 220532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078042824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2078042824
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.2680783666
Short name T889
Test name
Test status
Simulation time 9913867 ps
CPU time 1.08 seconds
Started Feb 08 12:55:40 PM UTC 25
Finished Feb 08 12:55:42 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680783666 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2680783666
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.3810073886
Short name T456
Test name
Test status
Simulation time 2427698626 ps
CPU time 20.87 seconds
Started Feb 08 12:55:35 PM UTC 25
Finished Feb 08 12:55:57 PM UTC 25
Peak memory 226764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810073886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3810073886
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.2647080345
Short name T898
Test name
Test status
Simulation time 343706357 ps
CPU time 9.33 seconds
Started Feb 08 12:55:36 PM UTC 25
Finished Feb 08 12:55:47 PM UTC 25
Peak memory 224740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647080345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 48.keymgr_custom_cm.2647080345
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.2228716134
Short name T892
Test name
Test status
Simulation time 483076930 ps
CPU time 6.67 seconds
Started Feb 08 12:55:35 PM UTC 25
Finished Feb 08 12:55:43 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228716134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2228716134
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.1444630600
Short name T886
Test name
Test status
Simulation time 55181766 ps
CPU time 2.69 seconds
Started Feb 08 12:55:36 PM UTC 25
Finished Feb 08 12:55:40 PM UTC 25
Peak memory 224640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444630600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1444630600
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.650650086
Short name T884
Test name
Test status
Simulation time 117605776 ps
CPU time 2.41 seconds
Started Feb 08 12:55:35 PM UTC 25
Finished Feb 08 12:55:39 PM UTC 25
Peak memory 226452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650650086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_
disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 48.keymgr_lc_disable.650650086
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_random.1784482306
Short name T885
Test name
Test status
Simulation time 180528825 ps
CPU time 5.03 seconds
Started Feb 08 12:55:34 PM UTC 25
Finished Feb 08 12:55:40 PM UTC 25
Peak memory 218212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784482306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.keymgr_random.1784482306
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.3602353974
Short name T888
Test name
Test status
Simulation time 533317225 ps
CPU time 7.7 seconds
Started Feb 08 12:55:33 PM UTC 25
Finished Feb 08 12:55:42 PM UTC 25
Peak memory 216204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602353974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.keymgr_sideload.3602353974
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.3672960443
Short name T894
Test name
Test status
Simulation time 709240827 ps
CPU time 10.58 seconds
Started Feb 08 12:55:33 PM UTC 25
Finished Feb 08 12:55:45 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672960443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3672960443
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.3051099072
Short name T916
Test name
Test status
Simulation time 1818077540 ps
CPU time 47.83 seconds
Started Feb 08 12:55:33 PM UTC 25
Finished Feb 08 12:56:23 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051099072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3051099072
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.3489663339
Short name T883
Test name
Test status
Simulation time 170215552 ps
CPU time 2.76 seconds
Started Feb 08 12:55:34 PM UTC 25
Finished Feb 08 12:55:38 PM UTC 25
Peak memory 216156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489663339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3489663339
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.2287792998
Short name T895
Test name
Test status
Simulation time 1258899567 ps
CPU time 7.06 seconds
Started Feb 08 12:55:37 PM UTC 25
Finished Feb 08 12:55:46 PM UTC 25
Peak memory 220372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287792998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2287792998
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.2959710419
Short name T882
Test name
Test status
Simulation time 41461854 ps
CPU time 2.33 seconds
Started Feb 08 12:55:33 PM UTC 25
Finished Feb 08 12:55:37 PM UTC 25
Peak memory 216204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959710419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.keymgr_smoke.2959710419
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.1909493299
Short name T919
Test name
Test status
Simulation time 3415412650 ps
CPU time 66.12 seconds
Started Feb 08 12:55:39 PM UTC 25
Finished Feb 08 12:56:47 PM UTC 25
Peak memory 226832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909493299 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1909493299
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.2541766435
Short name T417
Test name
Test status
Simulation time 381500278 ps
CPU time 24.02 seconds
Started Feb 08 12:55:40 PM UTC 25
Finished Feb 08 12:56:05 PM UTC 25
Peak memory 232800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2541766435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand
_reset.2541766435
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.73200783
Short name T915
Test name
Test status
Simulation time 4780274326 ps
CPU time 37.31 seconds
Started Feb 08 12:55:35 PM UTC 25
Finished Feb 08 12:56:14 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73200783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_i
nvalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.73200783
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.3915982973
Short name T887
Test name
Test status
Simulation time 280620812 ps
CPU time 2.88 seconds
Started Feb 08 12:55:37 PM UTC 25
Finished Feb 08 12:55:42 PM UTC 25
Peak memory 218640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915982973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3915982973
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.1579917781
Short name T905
Test name
Test status
Simulation time 47455832 ps
CPU time 0.94 seconds
Started Feb 08 12:55:49 PM UTC 25
Finished Feb 08 12:55:51 PM UTC 25
Peak memory 214088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579917781 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1579917781
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.3276549423
Short name T900
Test name
Test status
Simulation time 32747936 ps
CPU time 3.15 seconds
Started Feb 08 12:55:43 PM UTC 25
Finished Feb 08 12:55:48 PM UTC 25
Peak memory 226416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276549423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3276549423
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.2067763482
Short name T914
Test name
Test status
Simulation time 3547280554 ps
CPU time 21.42 seconds
Started Feb 08 12:55:47 PM UTC 25
Finished Feb 08 12:56:09 PM UTC 25
Peak memory 232368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067763482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 49.keymgr_custom_cm.2067763482
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.3738748028
Short name T902
Test name
Test status
Simulation time 66357765 ps
CPU time 3.6 seconds
Started Feb 08 12:55:44 PM UTC 25
Finished Feb 08 12:55:49 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738748028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3738748028
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.2617044179
Short name T909
Test name
Test status
Simulation time 251306243 ps
CPU time 9.33 seconds
Started Feb 08 12:55:45 PM UTC 25
Finished Feb 08 12:55:56 PM UTC 25
Peak memory 218364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617044179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2617044179
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.3420768686
Short name T903
Test name
Test status
Simulation time 40886717 ps
CPU time 3.01 seconds
Started Feb 08 12:55:45 PM UTC 25
Finished Feb 08 12:55:50 PM UTC 25
Peak memory 224336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420768686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3420768686
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.1790516397
Short name T251
Test name
Test status
Simulation time 99528904 ps
CPU time 3.91 seconds
Started Feb 08 12:55:44 PM UTC 25
Finished Feb 08 12:55:50 PM UTC 25
Peak memory 226468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790516397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 49.keymgr_lc_disable.1790516397
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_random.1941019299
Short name T342
Test name
Test status
Simulation time 446817209 ps
CPU time 7.98 seconds
Started Feb 08 12:55:43 PM UTC 25
Finished Feb 08 12:55:53 PM UTC 25
Peak memory 218240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941019299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.keymgr_random.1941019299
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.2223051505
Short name T897
Test name
Test status
Simulation time 91491925 ps
CPU time 4.51 seconds
Started Feb 08 12:55:41 PM UTC 25
Finished Feb 08 12:55:47 PM UTC 25
Peak memory 216204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223051505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.keymgr_sideload.2223051505
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.3663635587
Short name T911
Test name
Test status
Simulation time 415414694 ps
CPU time 12.39 seconds
Started Feb 08 12:55:43 PM UTC 25
Finished Feb 08 12:55:57 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663635587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3663635587
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.3842910981
Short name T893
Test name
Test status
Simulation time 80471105 ps
CPU time 1.91 seconds
Started Feb 08 12:55:41 PM UTC 25
Finished Feb 08 12:55:44 PM UTC 25
Peak memory 216104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842910981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3842910981
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.365140717
Short name T912
Test name
Test status
Simulation time 1380854782 ps
CPU time 15.72 seconds
Started Feb 08 12:55:43 PM UTC 25
Finished Feb 08 12:56:00 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365140717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.365140717
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.1985152472
Short name T907
Test name
Test status
Simulation time 75679607 ps
CPU time 4.99 seconds
Started Feb 08 12:55:48 PM UTC 25
Finished Feb 08 12:55:54 PM UTC 25
Peak memory 224596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985152472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1985152472
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.3562871232
Short name T917
Test name
Test status
Simulation time 5781925654 ps
CPU time 52.65 seconds
Started Feb 08 12:55:40 PM UTC 25
Finished Feb 08 12:56:34 PM UTC 25
Peak memory 218576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562871232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.keymgr_smoke.3562871232
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.3447530349
Short name T913
Test name
Test status
Simulation time 1265553198 ps
CPU time 19.7 seconds
Started Feb 08 12:55:48 PM UTC 25
Finished Feb 08 12:56:09 PM UTC 25
Peak memory 231604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447530349 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3447530349
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.3745541379
Short name T408
Test name
Test status
Simulation time 76348213 ps
CPU time 4.01 seconds
Started Feb 08 12:55:44 PM UTC 25
Finished Feb 08 12:55:50 PM UTC 25
Peak memory 218572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745541379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3745541379
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.38189339
Short name T904
Test name
Test status
Simulation time 384849071 ps
CPU time 2.1 seconds
Started Feb 08 12:55:48 PM UTC 25
Finished Feb 08 12:55:51 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38189339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync
_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.38189339
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.180388504
Short name T88
Test name
Test status
Simulation time 15987049 ps
CPU time 1.25 seconds
Started Feb 08 12:49:20 PM UTC 25
Finished Feb 08 12:49:22 PM UTC 25
Peak memory 214756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180388504 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.180388504
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.2037995518
Short name T9
Test name
Test status
Simulation time 145197304 ps
CPU time 2.86 seconds
Started Feb 08 12:49:14 PM UTC 25
Finished Feb 08 12:49:19 PM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037995518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 5.keymgr_custom_cm.2037995518
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.3856221117
Short name T298
Test name
Test status
Simulation time 34054973 ps
CPU time 2.19 seconds
Started Feb 08 12:49:10 PM UTC 25
Finished Feb 08 12:49:14 PM UTC 25
Peak memory 216460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856221117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3856221117
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.1207044893
Short name T84
Test name
Test status
Simulation time 43932900 ps
CPU time 2.32 seconds
Started Feb 08 12:49:14 PM UTC 25
Finished Feb 08 12:49:18 PM UTC 25
Peak memory 224492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207044893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1207044893
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.588002139
Short name T85
Test name
Test status
Simulation time 39223682 ps
CPU time 3.14 seconds
Started Feb 08 12:49:14 PM UTC 25
Finished Feb 08 12:49:19 PM UTC 25
Peak memory 224408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588002139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.588002139
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.12919965
Short name T64
Test name
Test status
Simulation time 88494365 ps
CPU time 3.6 seconds
Started Feb 08 12:49:11 PM UTC 25
Finished Feb 08 12:49:16 PM UTC 25
Peak memory 226516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12919965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_d
isable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.keymgr_lc_disable.12919965
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_random.25242940
Short name T217
Test name
Test status
Simulation time 981070228 ps
CPU time 32.79 seconds
Started Feb 08 12:49:08 PM UTC 25
Finished Feb 08 12:49:42 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25242940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_rand
om_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.keymgr_random.25242940
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.3323335304
Short name T267
Test name
Test status
Simulation time 164554138 ps
CPU time 4.92 seconds
Started Feb 08 12:49:02 PM UTC 25
Finished Feb 08 12:49:08 PM UTC 25
Peak memory 218512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323335304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.keymgr_sideload.3323335304
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.355800487
Short name T410
Test name
Test status
Simulation time 78637540 ps
CPU time 2.56 seconds
Started Feb 08 12:49:05 PM UTC 25
Finished Feb 08 12:49:09 PM UTC 25
Peak memory 216208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355800487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.355800487
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.3314108056
Short name T311
Test name
Test status
Simulation time 909106850 ps
CPU time 8.98 seconds
Started Feb 08 12:49:03 PM UTC 25
Finished Feb 08 12:49:13 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314108056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3314108056
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.1391946656
Short name T286
Test name
Test status
Simulation time 230990809 ps
CPU time 3.68 seconds
Started Feb 08 12:49:08 PM UTC 25
Finished Feb 08 12:49:13 PM UTC 25
Peak memory 216456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391946656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1391946656
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.1744878256
Short name T87
Test name
Test status
Simulation time 54043148 ps
CPU time 3.09 seconds
Started Feb 08 12:49:18 PM UTC 25
Finished Feb 08 12:49:22 PM UTC 25
Peak memory 218692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744878256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1744878256
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.1136735812
Short name T464
Test name
Test status
Simulation time 507183029 ps
CPU time 5.14 seconds
Started Feb 08 12:49:00 PM UTC 25
Finished Feb 08 12:49:07 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136735812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.keymgr_smoke.1136735812
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.498085409
Short name T89
Test name
Test status
Simulation time 196664635 ps
CPU time 8.12 seconds
Started Feb 08 12:49:13 PM UTC 25
Finished Feb 08 12:49:23 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498085409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_
invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.498085409
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.2110814234
Short name T90
Test name
Test status
Simulation time 302715928 ps
CPU time 3.32 seconds
Started Feb 08 12:49:19 PM UTC 25
Finished Feb 08 12:49:23 PM UTC 25
Peak memory 218608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110814234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2110814234
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.3302897170
Short name T467
Test name
Test status
Simulation time 75224678 ps
CPU time 0.92 seconds
Started Feb 08 12:49:33 PM UTC 25
Finished Feb 08 12:49:36 PM UTC 25
Peak memory 214760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302897170 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3302897170
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.3140582835
Short name T137
Test name
Test status
Simulation time 1290479382 ps
CPU time 18.04 seconds
Started Feb 08 12:49:24 PM UTC 25
Finished Feb 08 12:49:44 PM UTC 25
Peak memory 232552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140582835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3140582835
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.2414356243
Short name T306
Test name
Test status
Simulation time 228479047 ps
CPU time 3.76 seconds
Started Feb 08 12:49:25 PM UTC 25
Finished Feb 08 12:49:31 PM UTC 25
Peak memory 216460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414356243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2414356243
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.1390230516
Short name T317
Test name
Test status
Simulation time 48543823 ps
CPU time 3.18 seconds
Started Feb 08 12:49:28 PM UTC 25
Finished Feb 08 12:49:32 PM UTC 25
Peak memory 224412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390230516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1390230516
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.858420433
Short name T108
Test name
Test status
Simulation time 53563108 ps
CPU time 4.58 seconds
Started Feb 08 12:49:29 PM UTC 25
Finished Feb 08 12:49:35 PM UTC 25
Peak memory 232824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858420433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kma
c_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.858420433
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.1660565714
Short name T60
Test name
Test status
Simulation time 368716469 ps
CPU time 4.49 seconds
Started Feb 08 12:49:25 PM UTC 25
Finished Feb 08 12:49:31 PM UTC 25
Peak memory 224472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660565714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 6.keymgr_lc_disable.1660565714
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_random.2872373938
Short name T327
Test name
Test status
Simulation time 1570483430 ps
CPU time 6.5 seconds
Started Feb 08 12:49:24 PM UTC 25
Finished Feb 08 12:49:32 PM UTC 25
Peak memory 218576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872373938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.keymgr_random.2872373938
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.1152098782
Short name T266
Test name
Test status
Simulation time 113095511 ps
CPU time 5.23 seconds
Started Feb 08 12:49:21 PM UTC 25
Finished Feb 08 12:49:28 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152098782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.keymgr_sideload.1152098782
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.2985584488
Short name T299
Test name
Test status
Simulation time 117629069 ps
CPU time 4.05 seconds
Started Feb 08 12:49:23 PM UTC 25
Finished Feb 08 12:49:28 PM UTC 25
Peak memory 218584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985584488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2985584488
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.144051310
Short name T466
Test name
Test status
Simulation time 95380929 ps
CPU time 2.18 seconds
Started Feb 08 12:49:23 PM UTC 25
Finished Feb 08 12:49:27 PM UTC 25
Peak memory 216196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144051310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.144051310
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.1655265021
Short name T365
Test name
Test status
Simulation time 895203038 ps
CPU time 8.27 seconds
Started Feb 08 12:49:23 PM UTC 25
Finished Feb 08 12:49:33 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655265021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1655265021
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.1199068136
Short name T215
Test name
Test status
Simulation time 80365362 ps
CPU time 4.3 seconds
Started Feb 08 12:49:32 PM UTC 25
Finished Feb 08 12:49:38 PM UTC 25
Peak memory 224408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199068136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1199068136
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.568015583
Short name T465
Test name
Test status
Simulation time 130343613 ps
CPU time 3.36 seconds
Started Feb 08 12:49:20 PM UTC 25
Finished Feb 08 12:49:25 PM UTC 25
Peak memory 218248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568015583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.keymgr_smoke.568015583
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.2644408355
Short name T302
Test name
Test status
Simulation time 237024140 ps
CPU time 3.47 seconds
Started Feb 08 12:49:28 PM UTC 25
Finished Feb 08 12:49:32 PM UTC 25
Peak memory 224652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644408355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2644408355
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.1943942183
Short name T214
Test name
Test status
Simulation time 475982796 ps
CPU time 3.78 seconds
Started Feb 08 12:49:32 PM UTC 25
Finished Feb 08 12:49:37 PM UTC 25
Peak memory 218304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943942183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1943942183
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.967748934
Short name T194
Test name
Test status
Simulation time 18278120 ps
CPU time 1.25 seconds
Started Feb 08 12:49:49 PM UTC 25
Finished Feb 08 12:49:51 PM UTC 25
Peak memory 214148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967748934 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.967748934
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.854597626
Short name T138
Test name
Test status
Simulation time 359807977 ps
CPU time 6.93 seconds
Started Feb 08 12:49:39 PM UTC 25
Finished Feb 08 12:49:47 PM UTC 25
Peak memory 226436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854597626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.854597626
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.2953374478
Short name T42
Test name
Test status
Simulation time 289987534 ps
CPU time 5.11 seconds
Started Feb 08 12:49:44 PM UTC 25
Finished Feb 08 12:49:51 PM UTC 25
Peak memory 224768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953374478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 7.keymgr_custom_cm.2953374478
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.2983859943
Short name T58
Test name
Test status
Simulation time 155443933 ps
CPU time 3.82 seconds
Started Feb 08 12:49:40 PM UTC 25
Finished Feb 08 12:49:45 PM UTC 25
Peak memory 232520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983859943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2983859943
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.2547485176
Short name T20
Test name
Test status
Simulation time 152655409 ps
CPU time 5.42 seconds
Started Feb 08 12:49:44 PM UTC 25
Finished Feb 08 12:49:51 PM UTC 25
Peak memory 232068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547485176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2547485176
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.2007505010
Short name T65
Test name
Test status
Simulation time 81264378 ps
CPU time 2.39 seconds
Started Feb 08 12:49:43 PM UTC 25
Finished Feb 08 12:49:47 PM UTC 25
Peak memory 214232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007505010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 7.keymgr_lc_disable.2007505010
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_random.2370304564
Short name T432
Test name
Test status
Simulation time 418449889 ps
CPU time 9.85 seconds
Started Feb 08 12:49:39 PM UTC 25
Finished Feb 08 12:49:50 PM UTC 25
Peak memory 228752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370304564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.keymgr_random.2370304564
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.4139519437
Short name T468
Test name
Test status
Simulation time 3172390256 ps
CPU time 27.3 seconds
Started Feb 08 12:49:34 PM UTC 25
Finished Feb 08 12:50:03 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139519437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.keymgr_sideload.4139519437
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.3499887349
Short name T439
Test name
Test status
Simulation time 1760363083 ps
CPU time 33.9 seconds
Started Feb 08 12:49:35 PM UTC 25
Finished Feb 08 12:50:11 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499887349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3499887349
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.2413086165
Short name T219
Test name
Test status
Simulation time 192310058 ps
CPU time 7.5 seconds
Started Feb 08 12:49:34 PM UTC 25
Finished Feb 08 12:49:44 PM UTC 25
Peak memory 216456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413086165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2413086165
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.1621570579
Short name T216
Test name
Test status
Simulation time 109348711 ps
CPU time 4.15 seconds
Started Feb 08 12:49:37 PM UTC 25
Finished Feb 08 12:49:42 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621570579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1621570579
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.1399646705
Short name T452
Test name
Test status
Simulation time 36514970 ps
CPU time 2.27 seconds
Started Feb 08 12:49:44 PM UTC 25
Finished Feb 08 12:49:48 PM UTC 25
Peak memory 224552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399646705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1399646705
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.2967474249
Short name T218
Test name
Test status
Simulation time 3568728016 ps
CPU time 8.11 seconds
Started Feb 08 12:49:33 PM UTC 25
Finished Feb 08 12:49:43 PM UTC 25
Peak memory 218292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967474249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.keymgr_smoke.2967474249
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.2642330271
Short name T281
Test name
Test status
Simulation time 105077743 ps
CPU time 5.19 seconds
Started Feb 08 12:49:43 PM UTC 25
Finished Feb 08 12:49:50 PM UTC 25
Peak memory 218316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642330271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2642330271
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.280612336
Short name T45
Test name
Test status
Simulation time 40239362 ps
CPU time 2.69 seconds
Started Feb 08 12:49:46 PM UTC 25
Finished Feb 08 12:49:50 PM UTC 25
Peak memory 218384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280612336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_syn
c_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.280612336
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.1722644963
Short name T470
Test name
Test status
Simulation time 37632355 ps
CPU time 1 seconds
Started Feb 08 12:50:04 PM UTC 25
Finished Feb 08 12:50:07 PM UTC 25
Peak memory 214760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722644963 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1722644963
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.2182700145
Short name T279
Test name
Test status
Simulation time 87848191 ps
CPU time 4.8 seconds
Started Feb 08 12:49:52 PM UTC 25
Finished Feb 08 12:49:59 PM UTC 25
Peak memory 226612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182700145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2182700145
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.3538518333
Short name T197
Test name
Test status
Simulation time 60950474 ps
CPU time 3.02 seconds
Started Feb 08 12:49:53 PM UTC 25
Finished Feb 08 12:49:58 PM UTC 25
Peak memory 218244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538518333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3538518333
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.2457799238
Short name T102
Test name
Test status
Simulation time 1755028319 ps
CPU time 18.96 seconds
Started Feb 08 12:49:58 PM UTC 25
Finished Feb 08 12:50:19 PM UTC 25
Peak memory 224652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457799238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hw
sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2457799238
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.3529371058
Short name T275
Test name
Test status
Simulation time 59970768 ps
CPU time 3.18 seconds
Started Feb 08 12:50:00 PM UTC 25
Finished Feb 08 12:50:04 PM UTC 25
Peak memory 224384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529371058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3529371058
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.3436054408
Short name T453
Test name
Test status
Simulation time 460494311 ps
CPU time 6.38 seconds
Started Feb 08 12:49:58 PM UTC 25
Finished Feb 08 12:50:06 PM UTC 25
Peak memory 228560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436054408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 8.keymgr_lc_disable.3436054408
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_random.2948849765
Short name T350
Test name
Test status
Simulation time 341437174 ps
CPU time 11.5 seconds
Started Feb 08 12:49:52 PM UTC 25
Finished Feb 08 12:50:05 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948849765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.keymgr_random.2948849765
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.2447434955
Short name T309
Test name
Test status
Simulation time 864428790 ps
CPU time 7.97 seconds
Started Feb 08 12:49:51 PM UTC 25
Finished Feb 08 12:50:00 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447434955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.keymgr_sideload.2447434955
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.604770205
Short name T199
Test name
Test status
Simulation time 180414379 ps
CPU time 4.58 seconds
Started Feb 08 12:49:52 PM UTC 25
Finished Feb 08 12:49:58 PM UTC 25
Peak memory 218320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604770205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.604770205
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.18581451
Short name T195
Test name
Test status
Simulation time 819646508 ps
CPU time 4.92 seconds
Started Feb 08 12:49:51 PM UTC 25
Finished Feb 08 12:49:57 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18581451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_
TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.18581451
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.2141502899
Short name T198
Test name
Test status
Simulation time 107046252 ps
CPU time 4.33 seconds
Started Feb 08 12:49:52 PM UTC 25
Finished Feb 08 12:49:58 PM UTC 25
Peak memory 216192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141502899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2141502899
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.1673349763
Short name T469
Test name
Test status
Simulation time 36943181 ps
CPU time 2.35 seconds
Started Feb 08 12:50:00 PM UTC 25
Finished Feb 08 12:50:04 PM UTC 25
Peak memory 216272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673349763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1673349763
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.1605478771
Short name T196
Test name
Test status
Simulation time 176831521 ps
CPU time 5.45 seconds
Started Feb 08 12:49:51 PM UTC 25
Finished Feb 08 12:49:58 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605478771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.keymgr_smoke.1605478771
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.280522454
Short name T204
Test name
Test status
Simulation time 15005432222 ps
CPU time 279.89 seconds
Started Feb 08 12:50:01 PM UTC 25
Finished Feb 08 12:54:45 PM UTC 25
Peak memory 228624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280522454 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.280522454
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.3374273294
Short name T310
Test name
Test status
Simulation time 125822901 ps
CPU time 4.39 seconds
Started Feb 08 12:49:58 PM UTC 25
Finished Feb 08 12:50:04 PM UTC 25
Peak memory 216268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374273294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw
_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3374273294
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.562845191
Short name T67
Test name
Test status
Simulation time 161295985 ps
CPU time 4.72 seconds
Started Feb 08 12:50:01 PM UTC 25
Finished Feb 08 12:50:07 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562845191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_syn
c_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.562845191
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.237510292
Short name T472
Test name
Test status
Simulation time 11224118 ps
CPU time 0.98 seconds
Started Feb 08 12:50:14 PM UTC 25
Finished Feb 08 12:50:16 PM UTC 25
Peak memory 214028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237510292 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.237510292
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.1367227433
Short name T391
Test name
Test status
Simulation time 57233862 ps
CPU time 4.45 seconds
Started Feb 08 12:50:08 PM UTC 25
Finished Feb 08 12:50:13 PM UTC 25
Peak memory 224652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367227433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1367227433
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.3297148400
Short name T21
Test name
Test status
Simulation time 227793200 ps
CPU time 5.26 seconds
Started Feb 08 12:50:12 PM UTC 25
Finished Feb 08 12:50:19 PM UTC 25
Peak memory 230896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297148400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cu
stom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 9.keymgr_custom_cm.3297148400
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.1904154650
Short name T55
Test name
Test status
Simulation time 888092562 ps
CPU time 5.43 seconds
Started Feb 08 12:50:08 PM UTC 25
Finished Feb 08 12:50:14 PM UTC 25
Peak memory 228672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904154650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_di
rect_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1904154650
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.3236867352
Short name T318
Test name
Test status
Simulation time 325629433 ps
CPU time 4.21 seconds
Started Feb 08 12:50:11 PM UTC 25
Finished Feb 08 12:50:16 PM UTC 25
Peak memory 224664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236867352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_km
ac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3236867352
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.2538497798
Short name T237
Test name
Test status
Simulation time 237515250 ps
CPU time 2.48 seconds
Started Feb 08 12:50:09 PM UTC 25
Finished Feb 08 12:50:12 PM UTC 25
Peak memory 218256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538497798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc
_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 9.keymgr_lc_disable.2538497798
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_random.1087899453
Short name T289
Test name
Test status
Simulation time 75145205 ps
CPU time 4.66 seconds
Started Feb 08 12:50:08 PM UTC 25
Finished Feb 08 12:50:14 PM UTC 25
Peak memory 216464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087899453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ra
ndom_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.keymgr_random.1087899453
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.2885463119
Short name T324
Test name
Test status
Simulation time 356122129 ps
CPU time 3.92 seconds
Started Feb 08 12:50:05 PM UTC 25
Finished Feb 08 12:50:11 PM UTC 25
Peak memory 218576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885463119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.keymgr_sideload.2885463119
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.3547446721
Short name T336
Test name
Test status
Simulation time 708379951 ps
CPU time 6.6 seconds
Started Feb 08 12:50:06 PM UTC 25
Finished Feb 08 12:50:14 PM UTC 25
Peak memory 218504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547446721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM
_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3547446721
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.2719722274
Short name T278
Test name
Test status
Simulation time 218697805 ps
CPU time 3.81 seconds
Started Feb 08 12:50:05 PM UTC 25
Finished Feb 08 12:50:11 PM UTC 25
Peak memory 218520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719722274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2719722274
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.3237612007
Short name T300
Test name
Test status
Simulation time 385549520 ps
CPU time 4.48 seconds
Started Feb 08 12:50:06 PM UTC 25
Finished Feb 08 12:50:12 PM UTC 25
Peak memory 218312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237612007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UV
M_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3237612007
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.1363357830
Short name T473
Test name
Test status
Simulation time 176804548 ps
CPU time 3.15 seconds
Started Feb 08 12:50:12 PM UTC 25
Finished Feb 08 12:50:16 PM UTC 25
Peak memory 220452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363357830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_si
deload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1363357830
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.643498259
Short name T471
Test name
Test status
Simulation time 504030355 ps
CPU time 2.75 seconds
Started Feb 08 12:50:04 PM UTC 25
Finished Feb 08 12:50:08 PM UTC 25
Peak memory 216200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643498259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.keymgr_smoke.643498259
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.1500804720
Short name T202
Test name
Test status
Simulation time 137759905 ps
CPU time 7.03 seconds
Started Feb 08 12:50:13 PM UTC 25
Finished Feb 08 12:50:22 PM UTC 25
Peak memory 218424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500804720 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1500804720
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all_with_rand_reset.4113732009
Short name T126
Test name
Test status
Simulation time 366673650 ps
CPU time 17.67 seconds
Started Feb 08 12:50:13 PM UTC 25
Finished Feb 08 12:50:32 PM UTC 25
Peak memory 233020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=4113732009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_
reset.4113732009
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.252010208
Short name T305
Test name
Test status
Simulation time 165384094 ps
CPU time 6.82 seconds
Started Feb 08 12:50:10 PM UTC 25
Finished Feb 08 12:50:18 PM UTC 25
Peak memory 224656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252010208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_
invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.252010208
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.3500048893
Short name T149
Test name
Test status
Simulation time 49700200 ps
CPU time 2.79 seconds
Started Feb 08 12:50:12 PM UTC 25
Finished Feb 08 12:50:16 PM UTC 25
Peak memory 218572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500048893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sy
nc_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3500048893
Directory /workspaces/repo/scratch/os_regression/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest
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