| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.76 | 99.03 | 98.11 | 98.40 | 100.00 | 99.01 | 98.63 | 91.14 |
| T1007 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.47824575 | Oct 15 01:10:25 AM UTC 24 | Oct 15 01:10:31 AM UTC 24 | 656390434 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3487473925 | Oct 15 01:10:28 AM UTC 24 | Oct 15 01:10:31 AM UTC 24 | 22200630 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3083925451 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:31 AM UTC 24 | 49353900 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.176477517 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:31 AM UTC 24 | 57912544 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.993343543 | Oct 15 01:10:19 AM UTC 24 | Oct 15 01:10:31 AM UTC 24 | 933350252 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.3410966114 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:31 AM UTC 24 | 10372509 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3016730488 | Oct 15 01:10:28 AM UTC 24 | Oct 15 01:10:31 AM UTC 24 | 121908383 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.3309977562 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:31 AM UTC 24 | 23045624 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3100495494 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:32 AM UTC 24 | 144428543 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.1020417211 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:32 AM UTC 24 | 58776690 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2371621996 | Oct 15 01:10:28 AM UTC 24 | Oct 15 01:10:32 AM UTC 24 | 274357247 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.2339995737 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:32 AM UTC 24 | 187599756 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2056808711 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:32 AM UTC 24 | 219679007 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.246947777 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:32 AM UTC 24 | 76705648 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3253729097 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:32 AM UTC 24 | 56729581 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3318455714 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:33 AM UTC 24 | 468125125 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.483524592 | Oct 15 01:10:26 AM UTC 24 | Oct 15 01:10:33 AM UTC 24 | 238896509 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1346594823 | Oct 15 01:10:25 AM UTC 24 | Oct 15 01:10:33 AM UTC 24 | 662247772 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.68469201 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:33 AM UTC 24 | 193030085 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3301933631 | Oct 15 01:10:20 AM UTC 24 | Oct 15 01:10:33 AM UTC 24 | 679013035 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.212720266 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:33 AM UTC 24 | 253725299 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1776586407 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:33 AM UTC 24 | 760349563 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1021635113 | Oct 15 01:10:28 AM UTC 24 | Oct 15 01:10:33 AM UTC 24 | 119013445 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.1236563323 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:33 AM UTC 24 | 207150219 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.2881916423 | Oct 15 01:10:20 AM UTC 24 | Oct 15 01:10:34 AM UTC 24 | 1114973041 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.4191080791 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:34 AM UTC 24 | 41972438 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.1796999067 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:34 AM UTC 24 | 399744726 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1947499188 | Oct 15 01:10:20 AM UTC 24 | Oct 15 01:10:34 AM UTC 24 | 1787901276 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2185869450 | Oct 15 01:10:26 AM UTC 24 | Oct 15 01:10:34 AM UTC 24 | 328128402 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4021959983 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:34 AM UTC 24 | 104918149 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.1198395207 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:34 AM UTC 24 | 40237319 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.834867050 | Oct 15 01:10:33 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 46650915 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.884993886 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 50192823 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.541430002 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 38496039 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.2119157043 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 15954046 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3928457900 | Oct 15 01:10:33 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 16441142 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1566033507 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 10700842 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.2987392308 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 121586731 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2363015844 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 73893527 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2975875611 | Oct 15 01:10:33 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 9826829 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.2913244657 | Oct 15 01:10:33 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 12969521 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1870014211 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 39794216 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.2292627759 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 136453918 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.2672058154 | Oct 15 01:10:33 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 10502384 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.3999093468 | Oct 15 01:10:33 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 80521665 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.1943608016 | Oct 15 01:10:33 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 9986911 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4275433564 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 46195691 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.708815477 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 89445153 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.2936168445 | Oct 15 01:10:33 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 11470077 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.2150997088 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 94404324 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2257868496 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 61813194 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.2647005091 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:35 AM UTC 24 | 186954117 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3793202524 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:36 AM UTC 24 | 51727568 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.3034254342 | Oct 15 01:10:25 AM UTC 24 | Oct 15 01:10:36 AM UTC 24 | 558523244 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.2902561342 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:36 AM UTC 24 | 85090229 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3214056665 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:36 AM UTC 24 | 536766525 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.31660936 | Oct 15 01:10:25 AM UTC 24 | Oct 15 01:10:36 AM UTC 24 | 1598672765 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.126410067 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:36 AM UTC 24 | 1078087931 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2840370687 | Oct 15 01:10:29 AM UTC 24 | Oct 15 01:10:37 AM UTC 24 | 598791695 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.1704108084 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:37 AM UTC 24 | 221850393 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2587262294 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:38 AM UTC 24 | 428956591 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2732330827 | Oct 15 01:10:19 AM UTC 24 | Oct 15 01:10:38 AM UTC 24 | 4070218609 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3264369198 | Oct 15 01:10:32 AM UTC 24 | Oct 15 01:10:40 AM UTC 24 | 1027057404 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1282224120 | Oct 15 01:10:28 AM UTC 24 | Oct 15 01:10:40 AM UTC 24 | 486817511 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4200528055 | Oct 15 01:10:26 AM UTC 24 | Oct 15 01:10:42 AM UTC 24 | 548649844 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3468322008 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:47 AM UTC 24 | 9882802 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.3618714557 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:47 AM UTC 24 | 11711394 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.2530358022 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:48 AM UTC 24 | 72122743 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.1611028526 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:48 AM UTC 24 | 9477959 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.2637010700 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:54 AM UTC 24 | 32868047 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.221337621 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 11232415 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2073797550 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 13652618 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.575283640 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 44792519 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.2923730711 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 13179115 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2430026813 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 14026737 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.1328837347 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 107027323 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.2917958580 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 10040552 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.3686212686 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 7879529 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.1262631958 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 17404131 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.3741954501 | Oct 15 01:10:36 AM UTC 24 | Oct 15 01:10:55 AM UTC 24 | 10447054 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.1246117931 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 137943149 ps |
| CPU time | 3.72 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:31 AM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246117931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1246117931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.2948875898 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 549834166 ps |
| CPU time | 25.43 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:53 AM UTC 24 |
| Peak memory | 231780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948875898 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2948875898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all_with_rand_reset.2915840454 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2261537003 ps |
| CPU time | 20.81 seconds |
| Started | Oct 15 12:30:13 AM UTC 24 |
| Finished | Oct 15 12:30:35 AM UTC 24 |
| Peak memory | 231988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2915840454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr _stress_all_with_rand_reset.2915840454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.2512216150 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 617841040 ps |
| CPU time | 10.87 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:38 AM UTC 24 |
| Peak memory | 253760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512216150 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2512216150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.1011894831 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 7030450268 ps |
| CPU time | 26.79 seconds |
| Started | Oct 15 12:29:47 AM UTC 24 |
| Finished | Oct 15 12:30:15 AM UTC 24 |
| Peak memory | 231796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011894831 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1011894831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1935686741 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1363820057 ps |
| CPU time | 2.95 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:55 AM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935686741 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.1935686741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.1053584863 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 372181785 ps |
| CPU time | 4.29 seconds |
| Started | Oct 15 12:30:51 AM UTC 24 |
| Finished | Oct 15 12:30:56 AM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053584863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1053584863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.525074728 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 127431378 ps |
| CPU time | 8.01 seconds |
| Started | Oct 15 12:29:32 AM UTC 24 |
| Finished | Oct 15 12:29:41 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525074728 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.525074728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.4135967520 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 180237226 ps |
| CPU time | 3.19 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:30 AM UTC 24 |
| Peak memory | 223744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135967520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.4135967520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.1612484914 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 908929680 ps |
| CPU time | 7.32 seconds |
| Started | Oct 15 12:29:24 AM UTC 24 |
| Finished | Oct 15 12:29:33 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612484914 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1612484914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.3338531144 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 6584066603 ps |
| CPU time | 44.07 seconds |
| Started | Oct 15 12:30:21 AM UTC 24 |
| Finished | Oct 15 12:31:07 AM UTC 24 |
| Peak memory | 232100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338531144 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3338531144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.3108759986 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 778939975 ps |
| CPU time | 13.63 seconds |
| Started | Oct 15 12:32:39 AM UTC 24 |
| Finished | Oct 15 12:32:54 AM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108759986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3108759986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.2190337972 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 5556802713 ps |
| CPU time | 69.38 seconds |
| Started | Oct 15 12:31:13 AM UTC 24 |
| Finished | Oct 15 12:32:24 AM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190337972 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2190337972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.3260056861 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7997285940 ps |
| CPU time | 23.97 seconds |
| Started | Oct 15 12:30:27 AM UTC 24 |
| Finished | Oct 15 12:30:52 AM UTC 24 |
| Peak memory | 223788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260056861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3260056861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3391167360 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 334444374 ps |
| CPU time | 4.13 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:56 AM UTC 24 |
| Peak memory | 226396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391167360 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.3391167360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.1701816370 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1886494266 ps |
| CPU time | 48.76 seconds |
| Started | Oct 15 12:33:38 AM UTC 24 |
| Finished | Oct 15 12:34:29 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701816370 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1701816370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.1389784870 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5784369380 ps |
| CPU time | 81.52 seconds |
| Started | Oct 15 12:29:54 AM UTC 24 |
| Finished | Oct 15 12:31:17 AM UTC 24 |
| Peak memory | 231760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389784870 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1389784870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.2897661059 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1136643522 ps |
| CPU time | 5.76 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:33 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897661059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2897661059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.656368924 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 388752441 ps |
| CPU time | 10.29 seconds |
| Started | Oct 15 12:30:01 AM UTC 24 |
| Finished | Oct 15 12:30:12 AM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656368924 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.656368924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.3970379312 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 111509664 ps |
| CPU time | 6.61 seconds |
| Started | Oct 15 12:30:48 AM UTC 24 |
| Finished | Oct 15 12:30:55 AM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970379312 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3970379312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all_with_rand_reset.2473888156 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 771221136 ps |
| CPU time | 14.93 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:47 AM UTC 24 |
| Peak memory | 231900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2473888156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymg r_stress_all_with_rand_reset.2473888156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.499823810 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 718129582 ps |
| CPU time | 7.41 seconds |
| Started | Oct 15 12:30:36 AM UTC 24 |
| Finished | Oct 15 12:30:44 AM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499823810 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.499823810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.1212537101 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 136197731 ps |
| CPU time | 7.3 seconds |
| Started | Oct 15 12:32:18 AM UTC 24 |
| Finished | Oct 15 12:32:26 AM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212537101 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1212537101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.1246741914 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 138357021 ps |
| CPU time | 5.38 seconds |
| Started | Oct 15 12:29:34 AM UTC 24 |
| Finished | Oct 15 12:29:40 AM UTC 24 |
| Peak memory | 217532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246741914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1246741914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.1761956974 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 351614071 ps |
| CPU time | 4.46 seconds |
| Started | Oct 15 12:29:53 AM UTC 24 |
| Finished | Oct 15 12:29:58 AM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761956974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1761956974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.1975191448 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1631531009 ps |
| CPU time | 38.17 seconds |
| Started | Oct 15 12:30:12 AM UTC 24 |
| Finished | Oct 15 12:30:52 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975191448 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1975191448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.4096791501 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 357262354 ps |
| CPU time | 4.9 seconds |
| Started | Oct 15 12:32:19 AM UTC 24 |
| Finished | Oct 15 12:32:25 AM UTC 24 |
| Peak memory | 228108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096791501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.4096791501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.1753560369 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 67193312 ps |
| CPU time | 3.66 seconds |
| Started | Oct 15 12:32:18 AM UTC 24 |
| Finished | Oct 15 12:32:23 AM UTC 24 |
| Peak memory | 223924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753560369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1753560369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.249430856 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2014543879 ps |
| CPU time | 24.34 seconds |
| Started | Oct 15 12:29:25 AM UTC 24 |
| Finished | Oct 15 12:29:51 AM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249430856 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.249430856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.3845583679 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 438172926 ps |
| CPU time | 7.54 seconds |
| Started | Oct 15 12:34:02 AM UTC 24 |
| Finished | Oct 15 12:34:11 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845583679 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3845583679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.1749101107 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 305735141 ps |
| CPU time | 4.55 seconds |
| Started | Oct 15 12:31:54 AM UTC 24 |
| Finished | Oct 15 12:31:59 AM UTC 24 |
| Peak memory | 223932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749101107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1749101107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.3196486503 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 275591374 ps |
| CPU time | 3.24 seconds |
| Started | Oct 15 12:29:34 AM UTC 24 |
| Finished | Oct 15 12:29:38 AM UTC 24 |
| Peak memory | 230968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196486503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3196486503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.3088965247 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 267839332 ps |
| CPU time | 5.84 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:57 AM UTC 24 |
| Peak memory | 215816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088965247 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.3088965247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.2121730460 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 7784349834 ps |
| CPU time | 63.98 seconds |
| Started | Oct 15 12:31:49 AM UTC 24 |
| Finished | Oct 15 12:32:54 AM UTC 24 |
| Peak memory | 231752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121730460 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2121730460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.2970472672 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 237808000 ps |
| CPU time | 9.02 seconds |
| Started | Oct 15 12:33:07 AM UTC 24 |
| Finished | Oct 15 12:33:17 AM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970472672 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2970472672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.1621463936 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 165482667 ps |
| CPU time | 7.48 seconds |
| Started | Oct 15 12:30:11 AM UTC 24 |
| Finished | Oct 15 12:30:19 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621463936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1621463936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.4026198904 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 13646057 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:28 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026198904 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.4026198904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.432745485 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 171140321 ps |
| CPU time | 3.31 seconds |
| Started | Oct 15 12:29:36 AM UTC 24 |
| Finished | Oct 15 12:29:40 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432745485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.432745485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.3791441774 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1146686523 ps |
| CPU time | 25.37 seconds |
| Started | Oct 15 12:31:02 AM UTC 24 |
| Finished | Oct 15 12:31:28 AM UTC 24 |
| Peak memory | 230768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791441774 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3791441774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.3159470141 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 7216447036 ps |
| CPU time | 30.86 seconds |
| Started | Oct 15 12:34:25 AM UTC 24 |
| Finished | Oct 15 12:34:58 AM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159470141 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3159470141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.155006512 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2057883729 ps |
| CPU time | 9.92 seconds |
| Started | Oct 15 12:30:11 AM UTC 24 |
| Finished | Oct 15 12:30:22 AM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155006512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.155006512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.383435411 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 194594818 ps |
| CPU time | 1.51 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:10:01 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383435411 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.383435411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.3691983425 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 50681752 ps |
| CPU time | 2.79 seconds |
| Started | Oct 15 12:29:53 AM UTC 24 |
| Finished | Oct 15 12:29:56 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691983425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3691983425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.1630409672 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2978089335 ps |
| CPU time | 50.12 seconds |
| Started | Oct 15 12:34:33 AM UTC 24 |
| Finished | Oct 15 12:35:25 AM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630409672 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1630409672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.1613877280 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 519097382 ps |
| CPU time | 6.31 seconds |
| Started | Oct 15 12:35:32 AM UTC 24 |
| Finished | Oct 15 12:35:39 AM UTC 24 |
| Peak memory | 223920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613877280 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1613877280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_random.697510755 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 444222331 ps |
| CPU time | 5.64 seconds |
| Started | Oct 15 12:30:08 AM UTC 24 |
| Finished | Oct 15 12:30:15 AM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697510755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.697510755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.3034254342 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 558523244 ps |
| CPU time | 9.19 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:36 AM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034254342 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.3034254342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.3635360391 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 380173813 ps |
| CPU time | 3.95 seconds |
| Started | Oct 15 12:35:02 AM UTC 24 |
| Finished | Oct 15 12:35:07 AM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635360391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3635360391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.713641507 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 186721234 ps |
| CPU time | 4.41 seconds |
| Started | Oct 15 12:32:57 AM UTC 24 |
| Finished | Oct 15 12:33:02 AM UTC 24 |
| Peak memory | 223884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713641507 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.713641507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.3764398258 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4263297380 ps |
| CPU time | 45.04 seconds |
| Started | Oct 15 12:30:33 AM UTC 24 |
| Finished | Oct 15 12:31:20 AM UTC 24 |
| Peak memory | 232064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764398258 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3764398258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.1395197178 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 523066470 ps |
| CPU time | 3.67 seconds |
| Started | Oct 15 01:10:18 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395197178 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.1395197178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.3507270955 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 146136560 ps |
| CPU time | 3.86 seconds |
| Started | Oct 15 12:34:05 AM UTC 24 |
| Finished | Oct 15 12:34:10 AM UTC 24 |
| Peak memory | 231852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507270955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3507270955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.3283325626 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 30386646 ps |
| CPU time | 3.41 seconds |
| Started | Oct 15 12:30:29 AM UTC 24 |
| Finished | Oct 15 12:30:34 AM UTC 24 |
| Peak memory | 231928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283325626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3283325626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.2923520890 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 3793237138 ps |
| CPU time | 126.67 seconds |
| Started | Oct 15 12:31:18 AM UTC 24 |
| Finished | Oct 15 12:33:27 AM UTC 24 |
| Peak memory | 231808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923520890 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2923520890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.1461094225 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 95987508 ps |
| CPU time | 3.29 seconds |
| Started | Oct 15 12:29:32 AM UTC 24 |
| Finished | Oct 15 12:29:36 AM UTC 24 |
| Peak memory | 215664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461094225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1461094225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.2285559394 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 81268805 ps |
| CPU time | 3.68 seconds |
| Started | Oct 15 12:31:16 AM UTC 24 |
| Finished | Oct 15 12:31:21 AM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285559394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2285559394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.2855886773 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5798508743 ps |
| CPU time | 11.91 seconds |
| Started | Oct 15 12:33:16 AM UTC 24 |
| Finished | Oct 15 12:33:29 AM UTC 24 |
| Peak memory | 223788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855886773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2855886773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.2487941433 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 631945823 ps |
| CPU time | 11.03 seconds |
| Started | Oct 15 12:34:09 AM UTC 24 |
| Finished | Oct 15 12:34:22 AM UTC 24 |
| Peak memory | 225612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487941433 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2487941433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.158804312 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 158539028 ps |
| CPU time | 2.76 seconds |
| Started | Oct 15 12:30:06 AM UTC 24 |
| Finished | Oct 15 12:30:09 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158804312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.158804312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.1704108084 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 221850393 ps |
| CPU time | 3.76 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:37 AM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704108084 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.1704108084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.3384251027 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 259589984 ps |
| CPU time | 3.73 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:26 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384251027 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.3384251027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.1467766587 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 32242860 ps |
| CPU time | 2.77 seconds |
| Started | Oct 15 12:31:15 AM UTC 24 |
| Finished | Oct 15 12:31:19 AM UTC 24 |
| Peak memory | 223760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467766587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1467766587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.4219079018 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 49171855 ps |
| CPU time | 2.96 seconds |
| Started | Oct 15 12:31:39 AM UTC 24 |
| Finished | Oct 15 12:31:43 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219079018 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4219079018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all_with_rand_reset.255470737 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3792442125 ps |
| CPU time | 21.71 seconds |
| Started | Oct 15 12:33:52 AM UTC 24 |
| Finished | Oct 15 12:34:15 AM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=255470737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr _stress_all_with_rand_reset.255470737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.2242512297 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 63368394 ps |
| CPU time | 2.53 seconds |
| Started | Oct 15 12:30:01 AM UTC 24 |
| Finished | Oct 15 12:30:05 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242512297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2242512297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.2366665688 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 61892966 ps |
| CPU time | 5.59 seconds |
| Started | Oct 15 12:34:44 AM UTC 24 |
| Finished | Oct 15 12:34:51 AM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366665688 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2366665688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.3994913022 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 367887673 ps |
| CPU time | 4.32 seconds |
| Started | Oct 15 12:35:23 AM UTC 24 |
| Finished | Oct 15 12:35:29 AM UTC 24 |
| Peak memory | 231704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994913022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3994913022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.417065820 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 60278445 ps |
| CPU time | 4.02 seconds |
| Started | Oct 15 12:30:07 AM UTC 24 |
| Finished | Oct 15 12:30:12 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417065820 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.417065820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.758901848 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 145727534 ps |
| CPU time | 3.23 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:30 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758901848 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.758901848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.1451921452 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 324366332 ps |
| CPU time | 3.63 seconds |
| Started | Oct 15 12:34:37 AM UTC 24 |
| Finished | Oct 15 12:34:42 AM UTC 24 |
| Peak memory | 231888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451921452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1451921452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.68849198 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 377505446 ps |
| CPU time | 4.6 seconds |
| Started | Oct 15 12:29:31 AM UTC 24 |
| Finished | Oct 15 12:29:37 AM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68849198 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.68849198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.1575195076 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 639475302 ps |
| CPU time | 33.47 seconds |
| Started | Oct 15 12:31:04 AM UTC 24 |
| Finished | Oct 15 12:31:39 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575195076 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1575195076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.3379158856 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 108202607 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 12:31:51 AM UTC 24 |
| Finished | Oct 15 12:31:56 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379158856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3379158856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.845040391 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 876703937 ps |
| CPU time | 7.2 seconds |
| Started | Oct 15 12:32:25 AM UTC 24 |
| Finished | Oct 15 12:32:34 AM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845040391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.845040391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all_with_rand_reset.3730352602 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 708773211 ps |
| CPU time | 19.94 seconds |
| Started | Oct 15 12:32:47 AM UTC 24 |
| Finished | Oct 15 12:33:08 AM UTC 24 |
| Peak memory | 230216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3730352602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymg r_stress_all_with_rand_reset.3730352602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.3503050028 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 88890235 ps |
| CPU time | 3.68 seconds |
| Started | Oct 15 12:32:57 AM UTC 24 |
| Finished | Oct 15 12:33:02 AM UTC 24 |
| Peak memory | 223600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503050028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3503050028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.2260382510 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 153059307 ps |
| CPU time | 6.37 seconds |
| Started | Oct 15 12:33:38 AM UTC 24 |
| Finished | Oct 15 12:33:46 AM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260382510 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2260382510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.443422556 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 7586897405 ps |
| CPU time | 43.5 seconds |
| Started | Oct 15 12:34:38 AM UTC 24 |
| Finished | Oct 15 12:35:22 AM UTC 24 |
| Peak memory | 227896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443422556 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.443422556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.2894594104 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 956475240 ps |
| CPU time | 34.95 seconds |
| Started | Oct 15 12:34:53 AM UTC 24 |
| Finished | Oct 15 12:35:29 AM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894594104 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2894594104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.483524592 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 238896509 ps |
| CPU time | 5.76 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:33 AM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483524592 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.483524592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.2647005091 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 186954117 ps |
| CPU time | 2.33 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647005091 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.2647005091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.3449247616 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 185091516 ps |
| CPU time | 2.7 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:24 AM UTC 24 |
| Peak memory | 225748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449247616 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.3449247616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.1082272613 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3639076983 ps |
| CPU time | 27.13 seconds |
| Started | Oct 15 12:30:58 AM UTC 24 |
| Finished | Oct 15 12:31:27 AM UTC 24 |
| Peak memory | 223796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082272613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1082272613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.1741046445 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1039801743 ps |
| CPU time | 8.83 seconds |
| Started | Oct 15 12:29:47 AM UTC 24 |
| Finished | Oct 15 12:29:57 AM UTC 24 |
| Peak memory | 256376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741046445 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1741046445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.3268799793 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 54411062 ps |
| CPU time | 2.63 seconds |
| Started | Oct 15 12:29:25 AM UTC 24 |
| Finished | Oct 15 12:29:29 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268799793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3268799793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.1938728643 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 202712842 ps |
| CPU time | 8.78 seconds |
| Started | Oct 15 12:29:27 AM UTC 24 |
| Finished | Oct 15 12:29:37 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938728643 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1938728643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.1259635680 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 339056376 ps |
| CPU time | 14.97 seconds |
| Started | Oct 15 12:31:09 AM UTC 24 |
| Finished | Oct 15 12:31:25 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259635680 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1259635680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.1266111366 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 77279570 ps |
| CPU time | 3.38 seconds |
| Started | Oct 15 12:31:22 AM UTC 24 |
| Finished | Oct 15 12:31:27 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266111366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1266111366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.2145694260 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1182508036 ps |
| CPU time | 4.7 seconds |
| Started | Oct 15 12:31:58 AM UTC 24 |
| Finished | Oct 15 12:32:04 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145694260 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2145694260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.181955220 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 50901789 ps |
| CPU time | 4.17 seconds |
| Started | Oct 15 12:32:29 AM UTC 24 |
| Finished | Oct 15 12:32:34 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181955220 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.181955220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.3943068967 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 126275592 ps |
| CPU time | 5.12 seconds |
| Started | Oct 15 12:32:30 AM UTC 24 |
| Finished | Oct 15 12:32:37 AM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943068967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3943068967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.3742927129 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 4225499632 ps |
| CPU time | 101.38 seconds |
| Started | Oct 15 12:32:58 AM UTC 24 |
| Finished | Oct 15 12:34:42 AM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742927129 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3742927129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.1854074125 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 10483967017 ps |
| CPU time | 105.08 seconds |
| Started | Oct 15 12:33:10 AM UTC 24 |
| Finished | Oct 15 12:34:57 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854074125 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1854074125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.397787801 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 227000104 ps |
| CPU time | 5.1 seconds |
| Started | Oct 15 12:33:45 AM UTC 24 |
| Finished | Oct 15 12:33:51 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397787801 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.397787801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.4215392656 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 207251883 ps |
| CPU time | 3.2 seconds |
| Started | Oct 15 12:33:57 AM UTC 24 |
| Finished | Oct 15 12:34:02 AM UTC 24 |
| Peak memory | 223600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215392656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4215392656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.3011600890 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 96422842 ps |
| CPU time | 3.89 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:34:37 AM UTC 24 |
| Peak memory | 223848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011600890 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3011600890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.4278277127 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 64903782 ps |
| CPU time | 3.06 seconds |
| Started | Oct 15 12:34:33 AM UTC 24 |
| Finished | Oct 15 12:34:37 AM UTC 24 |
| Peak memory | 231552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278277127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.4278277127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_random.3223722465 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 378590131 ps |
| CPU time | 6.33 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:34:40 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223722465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3223722465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.2293852830 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 140402615 ps |
| CPU time | 2.4 seconds |
| Started | Oct 15 12:30:02 AM UTC 24 |
| Finished | Oct 15 12:30:06 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293852830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2293852830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.3283629585 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 495446897 ps |
| CPU time | 4.63 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:34:56 AM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283629585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3283629585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.419016264 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 484680306 ps |
| CPU time | 6.34 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:57 AM UTC 24 |
| Peak memory | 215652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419016264 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.419016264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3593851648 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 877293658 ps |
| CPU time | 21.29 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:10:13 AM UTC 24 |
| Peak memory | 215104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593851648 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3593851648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1207812956 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 36723369 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:52 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207812956 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1207812956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.117905136 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 218824541 ps |
| CPU time | 1.46 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:53 AM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=117905136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_wi th_rand_reset.117905136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.829733531 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 10227185 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:52 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829733531 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.829733531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.2013509260 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 114861364 ps |
| CPU time | 0.74 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:52 AM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013509260 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2013509260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1345358748 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 322411819 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:53 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345358748 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.1345358748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3857880870 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 620145906 ps |
| CPU time | 2.99 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:10:02 AM UTC 24 |
| Peak memory | 230312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857880870 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.3857880870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.1744795938 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 54961331 ps |
| CPU time | 1.96 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:10:01 AM UTC 24 |
| Peak memory | 223980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744795938 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1744795938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.4057651544 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 171910870 ps |
| CPU time | 5.19 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:56 AM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057651544 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.4057651544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.362073264 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 253601315 ps |
| CPU time | 4.55 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:56 AM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362073264 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.362073264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1462085276 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 396854290 ps |
| CPU time | 9.93 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:10:02 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462085276 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1462085276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2209201986 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 29552628 ps |
| CPU time | 1.34 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:53 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209201986 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2209201986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2719038437 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 60972309 ps |
| CPU time | 1.74 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:53 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2719038437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w ith_rand_reset.2719038437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.64088261 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 48703355 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:53 AM UTC 24 |
| Peak memory | 213676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64088261 -assert nopostproc +UVM_TESTNAME=keymgr_ base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.64088261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.1850424326 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 37251429 ps |
| CPU time | 0.64 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:52 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850424326 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1850424326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1120811434 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 302433985 ps |
| CPU time | 1.64 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:53 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120811434 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.1120811434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3064352495 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 85125285 ps |
| CPU time | 2.12 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:53 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064352495 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.3064352495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4164080679 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 159641205 ps |
| CPU time | 5.66 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:57 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164080679 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.4164080679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.2474330342 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 274326790 ps |
| CPU time | 1.92 seconds |
| Started | Oct 15 01:09:50 AM UTC 24 |
| Finished | Oct 15 01:09:53 AM UTC 24 |
| Peak memory | 226028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474330342 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2474330342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1039903268 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 27613690 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:27 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1039903268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_ with_rand_reset.1039903268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.3686146166 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 19747710 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:27 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686146166 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3686146166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.2448957203 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 10076467 ps |
| CPU time | 0.88 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:27 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448957203 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2448957203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1835635128 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 124789637 ps |
| CPU time | 1.74 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835635128 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.1835635128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1374358112 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 303949251 ps |
| CPU time | 2.46 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374358112 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.1374358112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.47824575 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 656390434 ps |
| CPU time | 4.84 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:31 AM UTC 24 |
| Peak memory | 232328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47824575 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.47824575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.74335375 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 433693646 ps |
| CPU time | 4.21 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:30 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74335375 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.74335375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.1096002512 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 346600293 ps |
| CPU time | 3.92 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:30 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096002512 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.1096002512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.773140789 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 32008337 ps |
| CPU time | 1.6 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=773140789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_w ith_rand_reset.773140789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.2289248201 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 33887686 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289248201 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2289248201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.1475662952 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 83525840 ps |
| CPU time | 0.65 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:27 AM UTC 24 |
| Peak memory | 213440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475662952 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1475662952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2362377706 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 126958906 ps |
| CPU time | 1.75 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362377706 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.2362377706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3870458174 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 220940963 ps |
| CPU time | 1.38 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 224432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870458174 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.3870458174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1346594823 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 662247772 ps |
| CPU time | 6.45 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:33 AM UTC 24 |
| Peak memory | 226200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346594823 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.1346594823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.1837818393 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 455167420 ps |
| CPU time | 2.9 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:29 AM UTC 24 |
| Peak memory | 225952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837818393 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1837818393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.558180168 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 151343762 ps |
| CPU time | 1.99 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:29 AM UTC 24 |
| Peak memory | 223924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=558180168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_w ith_rand_reset.558180168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.1496919176 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 15010679 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496919176 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1496919176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.1935180273 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 10235674 ps |
| CPU time | 0.68 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:27 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935180273 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1935180273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.934766144 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 94705731 ps |
| CPU time | 2.13 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:29 AM UTC 24 |
| Peak memory | 215960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934766144 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.934766144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2065225478 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 76357104 ps |
| CPU time | 2.41 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:29 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065225478 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.2065225478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.31660936 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 1598672765 ps |
| CPU time | 9.6 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:36 AM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31660936 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.31660936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.2896597277 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 93661185 ps |
| CPU time | 2.58 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:29 AM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896597277 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2896597277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2934128395 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 29936166 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2934128395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_ with_rand_reset.2934128395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.3940556274 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 28228897 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940556274 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3940556274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.1084969489 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 20932667 ps |
| CPU time | 0.88 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084969489 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1084969489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2462355641 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 21754430 ps |
| CPU time | 1.53 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462355641 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.2462355641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1115008791 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 541263110 ps |
| CPU time | 3.26 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:30 AM UTC 24 |
| Peak memory | 226444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115008791 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.1115008791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4200528055 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 548649844 ps |
| CPU time | 14.92 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:42 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200528055 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.4200528055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.1801479924 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 32258268 ps |
| CPU time | 2.13 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:29 AM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801479924 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1801479924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2371621996 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 274357247 ps |
| CPU time | 2.22 seconds |
| Started | Oct 15 01:10:28 AM UTC 24 |
| Finished | Oct 15 01:10:32 AM UTC 24 |
| Peak memory | 226132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2371621996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_ with_rand_reset.2371621996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.3768766923 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 19823625 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 01:10:28 AM UTC 24 |
| Finished | Oct 15 01:10:30 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768766923 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3768766923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.3348087934 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 54940984 ps |
| CPU time | 0.87 seconds |
| Started | Oct 15 01:10:28 AM UTC 24 |
| Finished | Oct 15 01:10:30 AM UTC 24 |
| Peak memory | 214156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348087934 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3348087934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3487473925 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 22200630 ps |
| CPU time | 1.24 seconds |
| Started | Oct 15 01:10:28 AM UTC 24 |
| Finished | Oct 15 01:10:31 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487473925 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.3487473925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.277644511 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 159805979 ps |
| CPU time | 3.04 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:30 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277644511 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.277644511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2185869450 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 328128402 ps |
| CPU time | 7.01 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:34 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185869450 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.2185869450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.4082400399 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 1145425296 ps |
| CPU time | 3.24 seconds |
| Started | Oct 15 01:10:26 AM UTC 24 |
| Finished | Oct 15 01:10:30 AM UTC 24 |
| Peak memory | 225940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082400399 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.4082400399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1021635113 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 119013445 ps |
| CPU time | 3.66 seconds |
| Started | Oct 15 01:10:28 AM UTC 24 |
| Finished | Oct 15 01:10:33 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021635113 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.1021635113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.176477517 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 57912544 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:31 AM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=176477517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_w ith_rand_reset.176477517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.3855345202 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 59440217 ps |
| CPU time | 0.83 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:31 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855345202 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3855345202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.3546674533 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 34959604 ps |
| CPU time | 0.77 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:31 AM UTC 24 |
| Peak memory | 214140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546674533 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3546674533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3318455714 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 468125125 ps |
| CPU time | 2.57 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:33 AM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318455714 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.3318455714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3016730488 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 121908383 ps |
| CPU time | 1.6 seconds |
| Started | Oct 15 01:10:28 AM UTC 24 |
| Finished | Oct 15 01:10:31 AM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016730488 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.3016730488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1282224120 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 486817511 ps |
| CPU time | 10.55 seconds |
| Started | Oct 15 01:10:28 AM UTC 24 |
| Finished | Oct 15 01:10:40 AM UTC 24 |
| Peak memory | 226136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282224120 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.1282224120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.1020417211 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 58776690 ps |
| CPU time | 2 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:32 AM UTC 24 |
| Peak memory | 223920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020417211 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1020417211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.1796999067 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 399744726 ps |
| CPU time | 3.97 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:34 AM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796999067 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.1796999067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3100495494 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 144428543 ps |
| CPU time | 1.41 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:32 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3100495494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_ with_rand_reset.3100495494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.3309977562 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 23045624 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:31 AM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309977562 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3309977562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3083925451 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 49353900 ps |
| CPU time | 0.74 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:31 AM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083925451 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3083925451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3253729097 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 56729581 ps |
| CPU time | 2.11 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:32 AM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253729097 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.3253729097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2056808711 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 219679007 ps |
| CPU time | 1.81 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:32 AM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056808711 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.2056808711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2840370687 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 598791695 ps |
| CPU time | 6.88 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:37 AM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840370687 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.2840370687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.212720266 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 253725299 ps |
| CPU time | 2.69 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:33 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212720266 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.212720266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.126410067 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 1078087931 ps |
| CPU time | 6.2 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:36 AM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126410067 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.126410067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.246947777 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 76705648 ps |
| CPU time | 1.74 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:32 AM UTC 24 |
| Peak memory | 226468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=246947777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_w ith_rand_reset.246947777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.2339995737 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 187599756 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:32 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339995737 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2339995737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.3410966114 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 10372509 ps |
| CPU time | 0.75 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:31 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410966114 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3410966114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.68469201 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 193030085 ps |
| CPU time | 2.27 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:33 AM UTC 24 |
| Peak memory | 215584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68469201 -assert nopostproc +UV M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.68469201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1776586407 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 760349563 ps |
| CPU time | 2.63 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:33 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776586407 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.1776586407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4021959983 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 104918149 ps |
| CPU time | 3.79 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:34 AM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021959983 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.4021959983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.2987392308 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 121586731 ps |
| CPU time | 4.09 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 225748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987392308 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2987392308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.1236563323 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 207150219 ps |
| CPU time | 2.75 seconds |
| Started | Oct 15 01:10:29 AM UTC 24 |
| Finished | Oct 15 01:10:33 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236563323 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.1236563323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4275433564 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 46195691 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4275433564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_ with_rand_reset.4275433564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2583385668 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 17566525 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:34 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583385668 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2583385668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.4191080791 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 41972438 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:34 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191080791 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4191080791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1870014211 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 39794216 ps |
| CPU time | 1.59 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870014211 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.1870014211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2363015844 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 73893527 ps |
| CPU time | 1.64 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 224264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363015844 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.2363015844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3264369198 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 1027057404 ps |
| CPU time | 7.09 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:40 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264369198 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.3264369198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3214056665 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 536766525 ps |
| CPU time | 3.13 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:36 AM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214056665 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3214056665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3793202524 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 51727568 ps |
| CPU time | 1.98 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:36 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3793202524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_ with_rand_reset.3793202524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.2150997088 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 94404324 ps |
| CPU time | 1.46 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150997088 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2150997088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.2296699673 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 24100316 ps |
| CPU time | 0.68 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:34 AM UTC 24 |
| Peak memory | 213640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296699673 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2296699673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2257868496 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 61813194 ps |
| CPU time | 1.47 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257868496 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.2257868496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.708815477 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 89445153 ps |
| CPU time | 1.54 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 224428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708815477 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.708815477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2587262294 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 428956591 ps |
| CPU time | 4.38 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:38 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587262294 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.2587262294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.2902561342 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 85090229 ps |
| CPU time | 2.6 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:36 AM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902561342 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2902561342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.1266702635 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 358199432 ps |
| CPU time | 8.46 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:29 AM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266702635 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1266702635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.335736580 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 134122853 ps |
| CPU time | 6.4 seconds |
| Started | Oct 15 01:10:18 AM UTC 24 |
| Finished | Oct 15 01:10:26 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335736580 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.335736580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.53392497 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 21106987 ps |
| CPU time | 0.82 seconds |
| Started | Oct 15 01:10:18 AM UTC 24 |
| Finished | Oct 15 01:10:20 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53392497 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.53392497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.605225919 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 42521965 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:21 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=605225919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_wi th_rand_reset.605225919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.2610881214 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 20080983 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 01:10:18 AM UTC 24 |
| Finished | Oct 15 01:10:20 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610881214 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2610881214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.1584641157 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 12526436 ps |
| CPU time | 0.65 seconds |
| Started | Oct 15 01:10:18 AM UTC 24 |
| Finished | Oct 15 01:10:20 AM UTC 24 |
| Peak memory | 213740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584641157 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1584641157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2770518451 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 46440872 ps |
| CPU time | 1.38 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:22 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770518451 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.2770518451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.488118115 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 116927075 ps |
| CPU time | 1.75 seconds |
| Started | Oct 15 01:10:18 AM UTC 24 |
| Finished | Oct 15 01:10:21 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488118115 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.488118115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.3346334377 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 8615254 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:34 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346334377 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3346334377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.1198395207 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 40237319 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:34 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198395207 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1198395207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.884993886 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 50192823 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884993886 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.884993886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.2119157043 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 15954046 ps |
| CPU time | 0.79 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119157043 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2119157043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1566033507 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 10700842 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566033507 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1566033507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.2292627759 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 136453918 ps |
| CPU time | 0.76 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292627759 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2292627759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.541430002 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 38496039 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 01:10:32 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541430002 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.541430002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.3999093468 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 80521665 ps |
| CPU time | 0.76 seconds |
| Started | Oct 15 01:10:33 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999093468 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3999093468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2975875611 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 9826829 ps |
| CPU time | 0.65 seconds |
| Started | Oct 15 01:10:33 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975875611 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2975875611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3928457900 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 16441142 ps |
| CPU time | 0.63 seconds |
| Started | Oct 15 01:10:33 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928457900 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3928457900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.993343543 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 933350252 ps |
| CPU time | 10.48 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:31 AM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993343543 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.993343543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2732330827 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 4070218609 ps |
| CPU time | 17.13 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:38 AM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732330827 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2732330827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3916867008 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 206499730 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:22 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916867008 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3916867008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.290049248 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 80429012 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:22 AM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=290049248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_wi th_rand_reset.290049248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.1647114231 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 408101739 ps |
| CPU time | 1.24 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:22 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647114231 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1647114231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.316433343 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 118874136 ps |
| CPU time | 0.72 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:21 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316433343 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.316433343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.852368059 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 269212988 ps |
| CPU time | 1.75 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:22 AM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852368059 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.852368059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3786121822 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 532754276 ps |
| CPU time | 1.76 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:22 AM UTC 24 |
| Peak memory | 224432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786121822 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.3786121822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3503412733 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 912077158 ps |
| CPU time | 8.67 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:29 AM UTC 24 |
| Peak memory | 226176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503412733 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.3503412733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.100911279 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 485743360 ps |
| CPU time | 2.64 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100911279 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.100911279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.622835988 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 337246333 ps |
| CPU time | 4.86 seconds |
| Started | Oct 15 01:10:19 AM UTC 24 |
| Finished | Oct 15 01:10:25 AM UTC 24 |
| Peak memory | 226216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622835988 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.622835988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.2913244657 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 12969521 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 01:10:33 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913244657 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2913244657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.2672058154 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 10502384 ps |
| CPU time | 0.77 seconds |
| Started | Oct 15 01:10:33 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672058154 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2672058154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.834867050 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 46650915 ps |
| CPU time | 0.68 seconds |
| Started | Oct 15 01:10:33 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834867050 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.834867050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.1943608016 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 9986911 ps |
| CPU time | 0.65 seconds |
| Started | Oct 15 01:10:33 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943608016 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1943608016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.2936168445 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 11470077 ps |
| CPU time | 0.81 seconds |
| Started | Oct 15 01:10:33 AM UTC 24 |
| Finished | Oct 15 01:10:35 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936168445 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2936168445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.2923730711 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 13179115 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923730711 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2923730711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.2637010700 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 32868047 ps |
| CPU time | 0.65 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:54 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637010700 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2637010700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3468322008 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 9882802 ps |
| CPU time | 0.72 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:47 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468322008 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3468322008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.221337621 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 11232415 ps |
| CPU time | 0.73 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221337621 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.221337621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2430026813 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 14026737 ps |
| CPU time | 0.81 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430026813 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2430026813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.2881916423 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 1114973041 ps |
| CPU time | 12.51 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:34 AM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881916423 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2881916423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1947499188 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 1787901276 ps |
| CPU time | 12.94 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:34 AM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947499188 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1947499188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1292040723 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 15851498 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:22 AM UTC 24 |
| Peak memory | 213268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292040723 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1292040723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1059997355 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 118209325 ps |
| CPU time | 1.58 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1059997355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_w ith_rand_reset.1059997355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.3182499733 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 37535693 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:22 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182499733 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3182499733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.2344817863 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 10413313 ps |
| CPU time | 0.82 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:22 AM UTC 24 |
| Peak memory | 213164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344817863 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2344817863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1970042360 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 110572206 ps |
| CPU time | 2.82 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:24 AM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970042360 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.1970042360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1887312779 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 131757395 ps |
| CPU time | 2.23 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 226308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887312779 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.1887312779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3188761247 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 162255725 ps |
| CPU time | 3.91 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:25 AM UTC 24 |
| Peak memory | 226176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188761247 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.3188761247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.3872498080 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 38350492 ps |
| CPU time | 2.38 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872498080 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3872498080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.3758117970 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 124580199 ps |
| CPU time | 3.01 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:24 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758117970 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.3758117970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2073797550 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 13652618 ps |
| CPU time | 0.66 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073797550 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2073797550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.1328837347 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 107027323 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328837347 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1328837347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.3618714557 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 11711394 ps |
| CPU time | 0.75 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:47 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618714557 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3618714557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.2530358022 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 72122743 ps |
| CPU time | 0.75 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:48 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530358022 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2530358022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.1262631958 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 17404131 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262631958 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1262631958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.575283640 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 44792519 ps |
| CPU time | 0.63 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575283640 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.575283640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.2917958580 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 10040552 ps |
| CPU time | 0.66 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917958580 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2917958580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.1611028526 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 9477959 ps |
| CPU time | 0.72 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:48 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611028526 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1611028526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.3686212686 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 7879529 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686212686 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3686212686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.3741954501 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 10447054 ps |
| CPU time | 0.66 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741954501 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3741954501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.881760233 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 57136603 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=881760233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_wi th_rand_reset.881760233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.1793867234 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 24513912 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793867234 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1793867234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.2309932177 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 9227025 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:22 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309932177 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2309932177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.833323236 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 42447453 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 213744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833323236 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.833323236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3830846921 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 158849842 ps |
| CPU time | 2.12 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 226224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830846921 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.3830846921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3246946615 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 87311652 ps |
| CPU time | 3.39 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:25 AM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246946615 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.3246946615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.2093371955 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 251451506 ps |
| CPU time | 2.26 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 227896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093371955 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2093371955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.1848741345 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 360229737 ps |
| CPU time | 4.64 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:26 AM UTC 24 |
| Peak memory | 226064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848741345 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.1848741345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.127598138 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 172201702 ps |
| CPU time | 2.06 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:24 AM UTC 24 |
| Peak memory | 225992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=127598138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_wi th_rand_reset.127598138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.3889857280 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 53997616 ps |
| CPU time | 1.21 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889857280 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3889857280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.987945087 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 29926131 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987945087 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.987945087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.140752861 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 142418958 ps |
| CPU time | 1.83 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 214188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140752861 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.140752861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.734884846 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 180913778 ps |
| CPU time | 3.3 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:25 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734884846 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.734884846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3294029431 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 253127454 ps |
| CPU time | 5.15 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:27 AM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294029431 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.3294029431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.1107788904 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 43671707 ps |
| CPU time | 2.49 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:24 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107788904 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1107788904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.182674277 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 30985227 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=182674277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_wi th_rand_reset.182674277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.2383109348 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 12501289 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383109348 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2383109348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.2319460776 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 31166929 ps |
| CPU time | 0.79 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 213740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319460776 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2319460776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1139822923 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 80890275 ps |
| CPU time | 2.16 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:24 AM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139822923 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.1139822923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2454969883 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 347835137 ps |
| CPU time | 2.01 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:24 AM UTC 24 |
| Peak memory | 226364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454969883 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.2454969883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3301933631 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 679013035 ps |
| CPU time | 11.08 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:33 AM UTC 24 |
| Peak memory | 226276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301933631 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.3301933631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.3299270475 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 96123550 ps |
| CPU time | 1.61 seconds |
| Started | Oct 15 01:10:20 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299270475 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3299270475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.582516082 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 188043541 ps |
| CPU time | 4.86 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:27 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582516082 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.582516082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2737976688 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 46591258 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 01:10:22 AM UTC 24 |
| Finished | Oct 15 01:10:24 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2737976688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_w ith_rand_reset.2737976688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.501496859 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 117902665 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501496859 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.501496859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.591350187 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 32672947 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:23 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591350187 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.591350187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.4092236898 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 245350192 ps |
| CPU time | 3.9 seconds |
| Started | Oct 15 01:10:22 AM UTC 24 |
| Finished | Oct 15 01:10:27 AM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092236898 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.4092236898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.776240370 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 688685955 ps |
| CPU time | 3.94 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:26 AM UTC 24 |
| Peak memory | 226448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776240370 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.776240370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4163523458 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 297730518 ps |
| CPU time | 3.34 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:25 AM UTC 24 |
| Peak memory | 226276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163523458 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.4163523458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.1093709585 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 39539107 ps |
| CPU time | 2.1 seconds |
| Started | Oct 15 01:10:21 AM UTC 24 |
| Finished | Oct 15 01:10:24 AM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093709585 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1093709585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1939651279 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 338704031 ps |
| CPU time | 1.43 seconds |
| Started | Oct 15 01:10:25 AM UTC 24 |
| Finished | Oct 15 01:10:27 AM UTC 24 |
| Peak memory | 228016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1939651279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_w ith_rand_reset.1939651279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.2219205363 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 239785466 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 01:10:22 AM UTC 24 |
| Finished | Oct 15 01:10:25 AM UTC 24 |
| Peak memory | 213236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219205363 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2219205363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.3550425853 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 19322621 ps |
| CPU time | 0.75 seconds |
| Started | Oct 15 01:10:22 AM UTC 24 |
| Finished | Oct 15 01:10:24 AM UTC 24 |
| Peak memory | 213800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550425853 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3550425853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2260151960 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 207429453 ps |
| CPU time | 2.11 seconds |
| Started | Oct 15 01:10:22 AM UTC 24 |
| Finished | Oct 15 01:10:25 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260151960 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.2260151960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1993908969 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 444279309 ps |
| CPU time | 2.75 seconds |
| Started | Oct 15 01:10:22 AM UTC 24 |
| Finished | Oct 15 01:10:26 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993908969 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.1993908969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1558531733 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 243793603 ps |
| CPU time | 3.41 seconds |
| Started | Oct 15 01:10:22 AM UTC 24 |
| Finished | Oct 15 01:10:27 AM UTC 24 |
| Peak memory | 226060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558531733 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.1558531733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.3903473925 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 45604263 ps |
| CPU time | 1.45 seconds |
| Started | Oct 15 01:10:22 AM UTC 24 |
| Finished | Oct 15 01:10:25 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903473925 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3903473925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.2035729915 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 130673846 ps |
| CPU time | 4.55 seconds |
| Started | Oct 15 01:10:22 AM UTC 24 |
| Finished | Oct 15 01:10:28 AM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035729915 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.2035729915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.1428580523 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1901605732 ps |
| CPU time | 51.06 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:30:18 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428580523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1428580523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.3002318345 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 592643354 ps |
| CPU time | 7.05 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:34 AM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002318345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3002318345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_random.1546415248 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 125830599 ps |
| CPU time | 4.96 seconds |
| Started | Oct 15 12:29:25 AM UTC 24 |
| Finished | Oct 15 12:29:31 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546415248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1546415248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.3740401221 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 218327253 ps |
| CPU time | 2.88 seconds |
| Started | Oct 15 12:29:18 AM UTC 24 |
| Finished | Oct 15 12:29:21 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740401221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3740401221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.798268147 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 5313205060 ps |
| CPU time | 36.36 seconds |
| Started | Oct 15 12:29:24 AM UTC 24 |
| Finished | Oct 15 12:30:02 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798268147 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.798268147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.1275498321 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2130868172 ps |
| CPU time | 5.84 seconds |
| Started | Oct 15 12:29:18 AM UTC 24 |
| Finished | Oct 15 12:29:25 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275498321 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1275498321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.1685471378 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 199776630 ps |
| CPU time | 4 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:31 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685471378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1685471378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.830675091 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 622759926 ps |
| CPU time | 4.38 seconds |
| Started | Oct 15 12:29:18 AM UTC 24 |
| Finished | Oct 15 12:29:23 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830675091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.830675091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.3365473515 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 283506514 ps |
| CPU time | 7.9 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:35 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365473515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3365473515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.1831828979 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 47657524 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 12:29:38 AM UTC 24 |
| Finished | Oct 15 12:29:40 AM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831828979 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1831828979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.3120901192 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 128762964 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 12:29:34 AM UTC 24 |
| Finished | Oct 15 12:29:39 AM UTC 24 |
| Peak memory | 223500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120901192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3120901192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.559012637 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1785204205 ps |
| CPU time | 6.19 seconds |
| Started | Oct 15 12:29:32 AM UTC 24 |
| Finished | Oct 15 12:29:39 AM UTC 24 |
| Peak memory | 223756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559012637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.559012637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_random.372145141 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 129172268 ps |
| CPU time | 8.2 seconds |
| Started | Oct 15 12:29:31 AM UTC 24 |
| Finished | Oct 15 12:29:41 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372145141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.372145141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.3805622950 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1013518411 ps |
| CPU time | 24.24 seconds |
| Started | Oct 15 12:29:38 AM UTC 24 |
| Finished | Oct 15 12:30:04 AM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805622950 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3805622950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.3419837502 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 132329609 ps |
| CPU time | 4.5 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:32 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419837502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3419837502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.2899523357 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 177187298 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 12:29:29 AM UTC 24 |
| Finished | Oct 15 12:29:35 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899523357 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2899523357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.3868386818 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 91182720 ps |
| CPU time | 5.13 seconds |
| Started | Oct 15 12:29:36 AM UTC 24 |
| Finished | Oct 15 12:29:42 AM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868386818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3868386818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.3142903490 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 193323204 ps |
| CPU time | 3.58 seconds |
| Started | Oct 15 12:29:26 AM UTC 24 |
| Finished | Oct 15 12:29:31 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142903490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3142903490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all_with_rand_reset.3001525941 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 678009875 ps |
| CPU time | 14.21 seconds |
| Started | Oct 15 12:29:36 AM UTC 24 |
| Finished | Oct 15 12:29:52 AM UTC 24 |
| Peak memory | 230000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3001525941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr _stress_all_with_rand_reset.3001525941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.1287445862 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 497718341 ps |
| CPU time | 5.94 seconds |
| Started | Oct 15 12:29:34 AM UTC 24 |
| Finished | Oct 15 12:29:41 AM UTC 24 |
| Peak memory | 215500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287445862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1287445862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.4050256497 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 63840563 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 12:31:03 AM UTC 24 |
| Finished | Oct 15 12:31:05 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050256497 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4050256497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.557804458 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 28709700 ps |
| CPU time | 3.6 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:31:02 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557804458 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.557804458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.579962409 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 178537419 ps |
| CPU time | 5.04 seconds |
| Started | Oct 15 12:31:00 AM UTC 24 |
| Finished | Oct 15 12:31:07 AM UTC 24 |
| Peak memory | 227780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579962409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.579962409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.3049952124 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 105117645 ps |
| CPU time | 3.64 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:31:02 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049952124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3049952124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.4084860041 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 129512184 ps |
| CPU time | 8.76 seconds |
| Started | Oct 15 12:31:00 AM UTC 24 |
| Finished | Oct 15 12:31:10 AM UTC 24 |
| Peak memory | 225672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084860041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4084860041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.930607808 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 43071706 ps |
| CPU time | 2.68 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:31:01 AM UTC 24 |
| Peak memory | 223188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930607808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.930607808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_random.3289464515 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 173364675 ps |
| CPU time | 4.46 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:31:02 AM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289464515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3289464515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.358082202 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 67405451 ps |
| CPU time | 3.57 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:31:01 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358082202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.358082202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.2014956397 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 137406212 ps |
| CPU time | 3.76 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:31:02 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014956397 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2014956397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.2824665386 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 4382000583 ps |
| CPU time | 66.91 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:32:05 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824665386 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2824665386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.3590404717 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 650453064 ps |
| CPU time | 4.16 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:31:02 AM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590404717 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3590404717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.2324439510 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 61557468 ps |
| CPU time | 2.07 seconds |
| Started | Oct 15 12:31:00 AM UTC 24 |
| Finished | Oct 15 12:31:04 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324439510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2324439510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.2806434340 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 629951191 ps |
| CPU time | 13.26 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:31:11 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806434340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2806434340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all_with_rand_reset.2166034211 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2814080262 ps |
| CPU time | 17.21 seconds |
| Started | Oct 15 12:31:02 AM UTC 24 |
| Finished | Oct 15 12:31:20 AM UTC 24 |
| Peak memory | 230772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2166034211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymg r_stress_all_with_rand_reset.2166034211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.2820840504 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 210420641 ps |
| CPU time | 5.91 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:31:04 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820840504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2820840504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.1478336208 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 88773648 ps |
| CPU time | 2.02 seconds |
| Started | Oct 15 12:31:01 AM UTC 24 |
| Finished | Oct 15 12:31:04 AM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478336208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1478336208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.2713370739 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 48449736 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 12:31:10 AM UTC 24 |
| Finished | Oct 15 12:31:12 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713370739 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2713370739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.1170697803 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 95379945 ps |
| CPU time | 5.54 seconds |
| Started | Oct 15 12:31:08 AM UTC 24 |
| Finished | Oct 15 12:31:14 AM UTC 24 |
| Peak memory | 230956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170697803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1170697803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.841549079 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 433646198 ps |
| CPU time | 5.46 seconds |
| Started | Oct 15 12:31:04 AM UTC 24 |
| Finished | Oct 15 12:31:11 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841549079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.841549079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.1029613625 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 386072428 ps |
| CPU time | 4.66 seconds |
| Started | Oct 15 12:31:05 AM UTC 24 |
| Finished | Oct 15 12:31:11 AM UTC 24 |
| Peak memory | 225872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029613625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1029613625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.3133287645 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 98755550 ps |
| CPU time | 6.75 seconds |
| Started | Oct 15 12:31:08 AM UTC 24 |
| Finished | Oct 15 12:31:16 AM UTC 24 |
| Peak memory | 223600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133287645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3133287645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.2678160184 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 208636054 ps |
| CPU time | 4.71 seconds |
| Started | Oct 15 12:31:04 AM UTC 24 |
| Finished | Oct 15 12:31:10 AM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678160184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2678160184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_random.3284263049 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 109496279 ps |
| CPU time | 4.75 seconds |
| Started | Oct 15 12:31:03 AM UTC 24 |
| Finished | Oct 15 12:31:09 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284263049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3284263049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.1910738138 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1786932527 ps |
| CPU time | 22.7 seconds |
| Started | Oct 15 12:31:03 AM UTC 24 |
| Finished | Oct 15 12:31:27 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910738138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1910738138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.3559146038 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 75485829 ps |
| CPU time | 4.37 seconds |
| Started | Oct 15 12:31:03 AM UTC 24 |
| Finished | Oct 15 12:31:08 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559146038 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3559146038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.2376301260 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 63352394 ps |
| CPU time | 4.57 seconds |
| Started | Oct 15 12:31:03 AM UTC 24 |
| Finished | Oct 15 12:31:09 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376301260 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2376301260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.1819581668 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 262486719 ps |
| CPU time | 3.48 seconds |
| Started | Oct 15 12:31:03 AM UTC 24 |
| Finished | Oct 15 12:31:08 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819581668 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1819581668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.3791529366 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 625962096 ps |
| CPU time | 5.9 seconds |
| Started | Oct 15 12:31:08 AM UTC 24 |
| Finished | Oct 15 12:31:15 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791529366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3791529366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.928729615 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 248599793 ps |
| CPU time | 3.42 seconds |
| Started | Oct 15 12:31:03 AM UTC 24 |
| Finished | Oct 15 12:31:07 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928729615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.928729615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all_with_rand_reset.2712264428 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1574471815 ps |
| CPU time | 28.91 seconds |
| Started | Oct 15 12:31:09 AM UTC 24 |
| Finished | Oct 15 12:31:39 AM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2712264428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymg r_stress_all_with_rand_reset.2712264428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.3577355825 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 201352535 ps |
| CPU time | 7.78 seconds |
| Started | Oct 15 12:31:05 AM UTC 24 |
| Finished | Oct 15 12:31:14 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577355825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3577355825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.3071384309 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 48929285 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 12:31:18 AM UTC 24 |
| Finished | Oct 15 12:31:20 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071384309 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3071384309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.10625596 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 100447682 ps |
| CPU time | 5.13 seconds |
| Started | Oct 15 12:31:16 AM UTC 24 |
| Finished | Oct 15 12:31:22 AM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10625596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.10625596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.2108173799 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 100560205 ps |
| CPU time | 3.36 seconds |
| Started | Oct 15 12:31:14 AM UTC 24 |
| Finished | Oct 15 12:31:18 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108173799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2108173799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.3480129419 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 73409636 ps |
| CPU time | 4.04 seconds |
| Started | Oct 15 12:31:15 AM UTC 24 |
| Finished | Oct 15 12:31:20 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480129419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3480129419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_random.3149967606 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 188350432 ps |
| CPU time | 7.13 seconds |
| Started | Oct 15 12:31:12 AM UTC 24 |
| Finished | Oct 15 12:31:21 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149967606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3149967606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.3031435268 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 642347896 ps |
| CPU time | 3.57 seconds |
| Started | Oct 15 12:31:11 AM UTC 24 |
| Finished | Oct 15 12:31:16 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031435268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3031435268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.1689135903 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 339536809 ps |
| CPU time | 6.11 seconds |
| Started | Oct 15 12:31:11 AM UTC 24 |
| Finished | Oct 15 12:31:18 AM UTC 24 |
| Peak memory | 217680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689135903 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1689135903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.1878823284 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 180242333 ps |
| CPU time | 4.85 seconds |
| Started | Oct 15 12:31:11 AM UTC 24 |
| Finished | Oct 15 12:31:17 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878823284 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1878823284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.863676938 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 133341419 ps |
| CPU time | 3.58 seconds |
| Started | Oct 15 12:31:12 AM UTC 24 |
| Finished | Oct 15 12:31:17 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863676938 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.863676938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.1942472503 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 155122993 ps |
| CPU time | 2.6 seconds |
| Started | Oct 15 12:31:17 AM UTC 24 |
| Finished | Oct 15 12:31:21 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942472503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1942472503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.883394635 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 76361123 ps |
| CPU time | 4.54 seconds |
| Started | Oct 15 12:31:10 AM UTC 24 |
| Finished | Oct 15 12:31:16 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883394635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.883394635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all_with_rand_reset.2153286299 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 275488715 ps |
| CPU time | 15.94 seconds |
| Started | Oct 15 12:31:18 AM UTC 24 |
| Finished | Oct 15 12:31:35 AM UTC 24 |
| Peak memory | 231936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2153286299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymg r_stress_all_with_rand_reset.2153286299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.745921927 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 35536036 ps |
| CPU time | 3.44 seconds |
| Started | Oct 15 12:31:15 AM UTC 24 |
| Finished | Oct 15 12:31:19 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745921927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.745921927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.409056382 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 174530996 ps |
| CPU time | 2.65 seconds |
| Started | Oct 15 12:31:17 AM UTC 24 |
| Finished | Oct 15 12:31:21 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409056382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.409056382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.1401858926 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 15339906 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:33 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401858926 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1401858926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.1446621135 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 477707276 ps |
| CPU time | 2.36 seconds |
| Started | Oct 15 12:31:21 AM UTC 24 |
| Finished | Oct 15 12:31:24 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446621135 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1446621135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.3201272844 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 175227100 ps |
| CPU time | 2.87 seconds |
| Started | Oct 15 12:31:22 AM UTC 24 |
| Finished | Oct 15 12:31:26 AM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201272844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3201272844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.1378686773 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 125060877 ps |
| CPU time | 3.27 seconds |
| Started | Oct 15 12:31:21 AM UTC 24 |
| Finished | Oct 15 12:31:25 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378686773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1378686773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.3036820028 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 154052734 ps |
| CPU time | 3.39 seconds |
| Started | Oct 15 12:31:22 AM UTC 24 |
| Finished | Oct 15 12:31:27 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036820028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3036820028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.831136540 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 300398379 ps |
| CPU time | 4.66 seconds |
| Started | Oct 15 12:31:22 AM UTC 24 |
| Finished | Oct 15 12:31:28 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831136540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.831136540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_random.2000321356 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 206274074 ps |
| CPU time | 3.6 seconds |
| Started | Oct 15 12:31:21 AM UTC 24 |
| Finished | Oct 15 12:31:26 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000321356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2000321356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.3788390292 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 211664424 ps |
| CPU time | 6.76 seconds |
| Started | Oct 15 12:31:20 AM UTC 24 |
| Finished | Oct 15 12:31:28 AM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788390292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3788390292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.972863474 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 468871974 ps |
| CPU time | 2.33 seconds |
| Started | Oct 15 12:31:21 AM UTC 24 |
| Finished | Oct 15 12:31:24 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972863474 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.972863474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.704098606 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 153677832 ps |
| CPU time | 5.35 seconds |
| Started | Oct 15 12:31:20 AM UTC 24 |
| Finished | Oct 15 12:31:26 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704098606 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.704098606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.3683819667 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 6690635174 ps |
| CPU time | 50.48 seconds |
| Started | Oct 15 12:31:21 AM UTC 24 |
| Finished | Oct 15 12:32:13 AM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683819667 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3683819667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.2223552891 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 4147993171 ps |
| CPU time | 36.98 seconds |
| Started | Oct 15 12:31:23 AM UTC 24 |
| Finished | Oct 15 12:32:02 AM UTC 24 |
| Peak memory | 223800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223552891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2223552891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.1073720687 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 192864520 ps |
| CPU time | 3.39 seconds |
| Started | Oct 15 12:31:20 AM UTC 24 |
| Finished | Oct 15 12:31:24 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073720687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1073720687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.374607843 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 23351814518 ps |
| CPU time | 191.74 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:34:45 AM UTC 24 |
| Peak memory | 225936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374607843 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.374607843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.625600486 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 289985970 ps |
| CPU time | 4.24 seconds |
| Started | Oct 15 12:31:22 AM UTC 24 |
| Finished | Oct 15 12:31:28 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625600486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.625600486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.4151646637 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 150975675 ps |
| CPU time | 3.11 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:35 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151646637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4151646637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.2348858729 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 32431050 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 12:31:37 AM UTC 24 |
| Finished | Oct 15 12:31:39 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348858729 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2348858729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.3438065264 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 255859012 ps |
| CPU time | 5.78 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:38 AM UTC 24 |
| Peak memory | 223792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438065264 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3438065264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.362785685 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3648871984 ps |
| CPU time | 35.66 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:32:08 AM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362785685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.362785685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.504703512 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 669119458 ps |
| CPU time | 6.16 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:38 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504703512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.504703512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.1025277300 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 102884527 ps |
| CPU time | 7.45 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:40 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025277300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1025277300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.4032951465 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 87960107 ps |
| CPU time | 2.72 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:35 AM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032951465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4032951465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.3769251260 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1254297744 ps |
| CPU time | 7.4 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:40 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769251260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3769251260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_random.4213523355 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 393091038 ps |
| CPU time | 6.32 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:38 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213523355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4213523355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.74556394 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1403885626 ps |
| CPU time | 21.69 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:54 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74556394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.74556394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.2586637169 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1978642755 ps |
| CPU time | 9.5 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:41 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586637169 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2586637169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.1272838148 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 133371732 ps |
| CPU time | 3.62 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:36 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272838148 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1272838148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.2916985853 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 119008497 ps |
| CPU time | 5.75 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:38 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916985853 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2916985853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.3777766904 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 193833371 ps |
| CPU time | 4 seconds |
| Started | Oct 15 12:31:34 AM UTC 24 |
| Finished | Oct 15 12:31:39 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777766904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3777766904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.3117426458 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 345794855 ps |
| CPU time | 4.59 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:36 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117426458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3117426458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.3924687229 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 277245868 ps |
| CPU time | 11.05 seconds |
| Started | Oct 15 12:31:36 AM UTC 24 |
| Finished | Oct 15 12:31:48 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924687229 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3924687229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all_with_rand_reset.2521427894 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 591254441 ps |
| CPU time | 20.45 seconds |
| Started | Oct 15 12:31:37 AM UTC 24 |
| Finished | Oct 15 12:31:58 AM UTC 24 |
| Peak memory | 231852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2521427894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymg r_stress_all_with_rand_reset.2521427894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.3205534492 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 102737516 ps |
| CPU time | 3.33 seconds |
| Started | Oct 15 12:31:31 AM UTC 24 |
| Finished | Oct 15 12:31:36 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205534492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3205534492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.3575290001 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 149967951 ps |
| CPU time | 4.45 seconds |
| Started | Oct 15 12:31:36 AM UTC 24 |
| Finished | Oct 15 12:31:41 AM UTC 24 |
| Peak memory | 219628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575290001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3575290001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.868386896 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 8795233 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 12:31:50 AM UTC 24 |
| Finished | Oct 15 12:31:53 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868386896 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.868386896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.827645237 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 59802092 ps |
| CPU time | 4.18 seconds |
| Started | Oct 15 12:31:40 AM UTC 24 |
| Finished | Oct 15 12:31:46 AM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827645237 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.827645237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.823504834 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 186881167 ps |
| CPU time | 4.78 seconds |
| Started | Oct 15 12:31:42 AM UTC 24 |
| Finished | Oct 15 12:31:48 AM UTC 24 |
| Peak memory | 227908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823504834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.823504834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.2675099678 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 792593715 ps |
| CPU time | 4.71 seconds |
| Started | Oct 15 12:31:40 AM UTC 24 |
| Finished | Oct 15 12:31:46 AM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675099678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2675099678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.3232987497 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 51525365 ps |
| CPU time | 2.55 seconds |
| Started | Oct 15 12:31:41 AM UTC 24 |
| Finished | Oct 15 12:31:44 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232987497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3232987497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.2088542904 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 182771150 ps |
| CPU time | 3.17 seconds |
| Started | Oct 15 12:31:41 AM UTC 24 |
| Finished | Oct 15 12:31:45 AM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088542904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2088542904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.3313144522 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 143270725 ps |
| CPU time | 5.49 seconds |
| Started | Oct 15 12:31:40 AM UTC 24 |
| Finished | Oct 15 12:31:47 AM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313144522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3313144522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_random.229909089 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 153236166 ps |
| CPU time | 2.95 seconds |
| Started | Oct 15 12:31:39 AM UTC 24 |
| Finished | Oct 15 12:31:43 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229909089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.229909089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.64152544 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 368365079 ps |
| CPU time | 4.86 seconds |
| Started | Oct 15 12:31:38 AM UTC 24 |
| Finished | Oct 15 12:31:44 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64152544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.64152544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.3227991227 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 424058940 ps |
| CPU time | 4.84 seconds |
| Started | Oct 15 12:31:39 AM UTC 24 |
| Finished | Oct 15 12:31:45 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227991227 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3227991227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.4089889016 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 435426151 ps |
| CPU time | 6.37 seconds |
| Started | Oct 15 12:31:39 AM UTC 24 |
| Finished | Oct 15 12:31:46 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089889016 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4089889016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.474012100 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 909261225 ps |
| CPU time | 20.82 seconds |
| Started | Oct 15 12:31:42 AM UTC 24 |
| Finished | Oct 15 12:32:04 AM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474012100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.474012100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.2928432277 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 57475153 ps |
| CPU time | 2.91 seconds |
| Started | Oct 15 12:31:37 AM UTC 24 |
| Finished | Oct 15 12:31:41 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928432277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2928432277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.3240504628 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 3219920046 ps |
| CPU time | 29.73 seconds |
| Started | Oct 15 12:31:40 AM UTC 24 |
| Finished | Oct 15 12:32:12 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240504628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3240504628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.423610862 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 118955176 ps |
| CPU time | 1.98 seconds |
| Started | Oct 15 12:31:49 AM UTC 24 |
| Finished | Oct 15 12:31:52 AM UTC 24 |
| Peak memory | 217388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423610862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.423610862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.2338112228 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 55259408 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 12:31:57 AM UTC 24 |
| Finished | Oct 15 12:31:59 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338112228 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2338112228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.3954067053 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 197290951 ps |
| CPU time | 5.23 seconds |
| Started | Oct 15 12:31:50 AM UTC 24 |
| Finished | Oct 15 12:31:57 AM UTC 24 |
| Peak memory | 223568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954067053 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3954067053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.3322018889 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 352635439 ps |
| CPU time | 3.83 seconds |
| Started | Oct 15 12:31:50 AM UTC 24 |
| Finished | Oct 15 12:31:56 AM UTC 24 |
| Peak memory | 217536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322018889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3322018889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.2664944324 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 179248684 ps |
| CPU time | 5.13 seconds |
| Started | Oct 15 12:31:53 AM UTC 24 |
| Finished | Oct 15 12:31:59 AM UTC 24 |
| Peak memory | 231968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664944324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2664944324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.1600862780 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 30525299 ps |
| CPU time | 3.19 seconds |
| Started | Oct 15 12:31:50 AM UTC 24 |
| Finished | Oct 15 12:31:56 AM UTC 24 |
| Peak memory | 216936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600862780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1600862780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_random.2827892802 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 57780612 ps |
| CPU time | 4.39 seconds |
| Started | Oct 15 12:31:50 AM UTC 24 |
| Finished | Oct 15 12:31:56 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827892802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2827892802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.3655644411 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 233224526 ps |
| CPU time | 9.43 seconds |
| Started | Oct 15 12:31:50 AM UTC 24 |
| Finished | Oct 15 12:32:01 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655644411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3655644411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.904602037 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 3169317679 ps |
| CPU time | 31.54 seconds |
| Started | Oct 15 12:31:50 AM UTC 24 |
| Finished | Oct 15 12:32:24 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904602037 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.904602037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.97185221 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 53610690 ps |
| CPU time | 2.58 seconds |
| Started | Oct 15 12:31:50 AM UTC 24 |
| Finished | Oct 15 12:31:54 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97185221 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.97185221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.3142415734 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 104088522 ps |
| CPU time | 3.27 seconds |
| Started | Oct 15 12:31:50 AM UTC 24 |
| Finished | Oct 15 12:31:55 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142415734 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3142415734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.3047873649 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1025958820 ps |
| CPU time | 3.84 seconds |
| Started | Oct 15 12:31:55 AM UTC 24 |
| Finished | Oct 15 12:32:00 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047873649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3047873649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.2916048685 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 279210424 ps |
| CPU time | 3.91 seconds |
| Started | Oct 15 12:31:50 AM UTC 24 |
| Finished | Oct 15 12:31:55 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916048685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2916048685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.3242550734 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2057019556 ps |
| CPU time | 18.83 seconds |
| Started | Oct 15 12:31:56 AM UTC 24 |
| Finished | Oct 15 12:32:16 AM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242550734 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3242550734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.1210672881 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 115040173 ps |
| CPU time | 4.97 seconds |
| Started | Oct 15 12:31:51 AM UTC 24 |
| Finished | Oct 15 12:31:57 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210672881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1210672881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.1710790427 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 73619971 ps |
| CPU time | 3.1 seconds |
| Started | Oct 15 12:31:55 AM UTC 24 |
| Finished | Oct 15 12:31:59 AM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710790427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1710790427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.854071749 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 19435037 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 12:32:10 AM UTC 24 |
| Finished | Oct 15 12:32:13 AM UTC 24 |
| Peak memory | 213416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854071749 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.854071749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.1999533439 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 89628373 ps |
| CPU time | 4.36 seconds |
| Started | Oct 15 12:32:00 AM UTC 24 |
| Finished | Oct 15 12:32:05 AM UTC 24 |
| Peak memory | 223816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999533439 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1999533439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.2019328657 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 151836864 ps |
| CPU time | 4.18 seconds |
| Started | Oct 15 12:32:02 AM UTC 24 |
| Finished | Oct 15 12:32:07 AM UTC 24 |
| Peak memory | 231684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019328657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2019328657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.1629034155 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 177458517 ps |
| CPU time | 3.47 seconds |
| Started | Oct 15 12:32:00 AM UTC 24 |
| Finished | Oct 15 12:32:04 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629034155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1629034155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.1947831700 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 269404003 ps |
| CPU time | 4.52 seconds |
| Started | Oct 15 12:32:01 AM UTC 24 |
| Finished | Oct 15 12:32:07 AM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947831700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1947831700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.3440235795 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 88145663 ps |
| CPU time | 3.3 seconds |
| Started | Oct 15 12:32:02 AM UTC 24 |
| Finished | Oct 15 12:32:06 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440235795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3440235795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.647637701 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 354265903 ps |
| CPU time | 6.61 seconds |
| Started | Oct 15 12:32:00 AM UTC 24 |
| Finished | Oct 15 12:32:08 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647637701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.647637701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_random.1296485003 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 70025918 ps |
| CPU time | 4.2 seconds |
| Started | Oct 15 12:32:00 AM UTC 24 |
| Finished | Oct 15 12:32:05 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296485003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1296485003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.3727354168 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 325534400 ps |
| CPU time | 9.45 seconds |
| Started | Oct 15 12:31:57 AM UTC 24 |
| Finished | Oct 15 12:32:08 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727354168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3727354168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.4093372204 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 915431566 ps |
| CPU time | 35.26 seconds |
| Started | Oct 15 12:31:58 AM UTC 24 |
| Finished | Oct 15 12:32:35 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093372204 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.4093372204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.1132683691 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 77619190 ps |
| CPU time | 2.81 seconds |
| Started | Oct 15 12:31:57 AM UTC 24 |
| Finished | Oct 15 12:32:01 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132683691 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1132683691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.3171690452 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 17279104 ps |
| CPU time | 1.51 seconds |
| Started | Oct 15 12:32:02 AM UTC 24 |
| Finished | Oct 15 12:32:05 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171690452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3171690452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.2471509070 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 27186864 ps |
| CPU time | 2.75 seconds |
| Started | Oct 15 12:31:57 AM UTC 24 |
| Finished | Oct 15 12:32:01 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471509070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2471509070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.524398884 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 370809100 ps |
| CPU time | 5.25 seconds |
| Started | Oct 15 12:32:10 AM UTC 24 |
| Finished | Oct 15 12:32:17 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524398884 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.524398884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all_with_rand_reset.2121946508 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 130478357 ps |
| CPU time | 11.13 seconds |
| Started | Oct 15 12:32:10 AM UTC 24 |
| Finished | Oct 15 12:32:23 AM UTC 24 |
| Peak memory | 229956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2121946508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymg r_stress_all_with_rand_reset.2121946508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.3249587671 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 167304431 ps |
| CPU time | 7.04 seconds |
| Started | Oct 15 12:32:01 AM UTC 24 |
| Finished | Oct 15 12:32:09 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249587671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3249587671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.2594298048 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 528706539 ps |
| CPU time | 11.01 seconds |
| Started | Oct 15 12:32:03 AM UTC 24 |
| Finished | Oct 15 12:32:15 AM UTC 24 |
| Peak memory | 219704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594298048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2594298048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.1023646626 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 73129137 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 12:32:16 AM UTC 24 |
| Finished | Oct 15 12:32:19 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023646626 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1023646626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.1427356471 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 96805843 ps |
| CPU time | 5.33 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:18 AM UTC 24 |
| Peak memory | 222860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427356471 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1427356471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.4270686963 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 240124563 ps |
| CPU time | 8.46 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:22 AM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270686963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4270686963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.775324972 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 878882840 ps |
| CPU time | 7.96 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:21 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775324972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.775324972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.1496340632 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 103796452 ps |
| CPU time | 3.85 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:17 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496340632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1496340632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.3821918962 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 155348973 ps |
| CPU time | 2.85 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:16 AM UTC 24 |
| Peak memory | 219704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821918962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3821918962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.1384144787 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 62660002 ps |
| CPU time | 4.19 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:17 AM UTC 24 |
| Peak memory | 217636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384144787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1384144787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_random.3591792613 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 205270293 ps |
| CPU time | 10.8 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:24 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591792613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3591792613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.234102736 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 543520841 ps |
| CPU time | 13.57 seconds |
| Started | Oct 15 12:32:11 AM UTC 24 |
| Finished | Oct 15 12:32:26 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234102736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.234102736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.2412637529 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 267721082 ps |
| CPU time | 3.41 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:16 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412637529 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2412637529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.755075865 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 621657709 ps |
| CPU time | 4.89 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:17 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755075865 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.755075865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.4151831100 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 151141855 ps |
| CPU time | 3.41 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:16 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151831100 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.4151831100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.1024453386 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 313658797 ps |
| CPU time | 3.18 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:16 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024453386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1024453386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.1191038079 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1422918574 ps |
| CPU time | 4.45 seconds |
| Started | Oct 15 12:32:11 AM UTC 24 |
| Finished | Oct 15 12:32:17 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191038079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1191038079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.1937610165 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 137903906 ps |
| CPU time | 2.78 seconds |
| Started | Oct 15 12:32:13 AM UTC 24 |
| Finished | Oct 15 12:32:17 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937610165 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1937610165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.3246434749 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 356271230 ps |
| CPU time | 11.18 seconds |
| Started | Oct 15 12:32:12 AM UTC 24 |
| Finished | Oct 15 12:32:24 AM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246434749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3246434749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.2718942609 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 102721874 ps |
| CPU time | 3.46 seconds |
| Started | Oct 15 12:32:13 AM UTC 24 |
| Finished | Oct 15 12:32:18 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718942609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2718942609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.3682983496 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 41166535 ps |
| CPU time | 1.3 seconds |
| Started | Oct 15 12:32:22 AM UTC 24 |
| Finished | Oct 15 12:32:24 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682983496 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3682983496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.4085052100 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 35045778 ps |
| CPU time | 2.7 seconds |
| Started | Oct 15 12:32:18 AM UTC 24 |
| Finished | Oct 15 12:32:22 AM UTC 24 |
| Peak memory | 223756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085052100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4085052100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.2725100483 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 81333752 ps |
| CPU time | 2.19 seconds |
| Started | Oct 15 12:32:19 AM UTC 24 |
| Finished | Oct 15 12:32:22 AM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725100483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2725100483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.818141033 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 385543213 ps |
| CPU time | 13.7 seconds |
| Started | Oct 15 12:32:18 AM UTC 24 |
| Finished | Oct 15 12:32:33 AM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818141033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.818141033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_random.4196209104 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 268282883 ps |
| CPU time | 5.45 seconds |
| Started | Oct 15 12:32:18 AM UTC 24 |
| Finished | Oct 15 12:32:24 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196209104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4196209104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.3430621485 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 58938848 ps |
| CPU time | 2.92 seconds |
| Started | Oct 15 12:32:17 AM UTC 24 |
| Finished | Oct 15 12:32:21 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430621485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3430621485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.2412611258 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 682443718 ps |
| CPU time | 10.82 seconds |
| Started | Oct 15 12:32:17 AM UTC 24 |
| Finished | Oct 15 12:32:29 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412611258 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2412611258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.2759233551 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 244751382 ps |
| CPU time | 2.53 seconds |
| Started | Oct 15 12:32:17 AM UTC 24 |
| Finished | Oct 15 12:32:20 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759233551 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2759233551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.4286707755 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 231977190 ps |
| CPU time | 3.18 seconds |
| Started | Oct 15 12:32:18 AM UTC 24 |
| Finished | Oct 15 12:32:22 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286707755 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4286707755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.4049761723 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 31230180 ps |
| CPU time | 2.61 seconds |
| Started | Oct 15 12:32:19 AM UTC 24 |
| Finished | Oct 15 12:32:23 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049761723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4049761723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.3880284708 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 23439324 ps |
| CPU time | 2.16 seconds |
| Started | Oct 15 12:32:17 AM UTC 24 |
| Finished | Oct 15 12:32:20 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880284708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3880284708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.2761133047 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 645935913 ps |
| CPU time | 27.41 seconds |
| Started | Oct 15 12:32:20 AM UTC 24 |
| Finished | Oct 15 12:32:49 AM UTC 24 |
| Peak memory | 231380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761133047 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2761133047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.3678622783 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 228430478 ps |
| CPU time | 6.22 seconds |
| Started | Oct 15 12:32:18 AM UTC 24 |
| Finished | Oct 15 12:32:25 AM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678622783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3678622783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.3961043640 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 736461905 ps |
| CPU time | 5.55 seconds |
| Started | Oct 15 12:32:20 AM UTC 24 |
| Finished | Oct 15 12:32:27 AM UTC 24 |
| Peak memory | 219704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961043640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3961043640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.1471375718 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 29718327 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 12:29:49 AM UTC 24 |
| Finished | Oct 15 12:29:51 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471375718 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1471375718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.1750081351 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 56543686 ps |
| CPU time | 4.95 seconds |
| Started | Oct 15 12:29:43 AM UTC 24 |
| Finished | Oct 15 12:29:49 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750081351 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1750081351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.443702646 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1030265766 ps |
| CPU time | 4.59 seconds |
| Started | Oct 15 12:29:43 AM UTC 24 |
| Finished | Oct 15 12:29:49 AM UTC 24 |
| Peak memory | 229724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443702646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.443702646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.540996428 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 251065355 ps |
| CPU time | 3.64 seconds |
| Started | Oct 15 12:29:43 AM UTC 24 |
| Finished | Oct 15 12:29:48 AM UTC 24 |
| Peak memory | 228024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540996428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.540996428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.2632295351 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1375988662 ps |
| CPU time | 5.84 seconds |
| Started | Oct 15 12:29:43 AM UTC 24 |
| Finished | Oct 15 12:29:50 AM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632295351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2632295351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.3458619611 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 446446443 ps |
| CPU time | 3.04 seconds |
| Started | Oct 15 12:29:43 AM UTC 24 |
| Finished | Oct 15 12:29:47 AM UTC 24 |
| Peak memory | 230732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458619611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3458619611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.2257292066 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 160023684 ps |
| CPU time | 3.11 seconds |
| Started | Oct 15 12:29:43 AM UTC 24 |
| Finished | Oct 15 12:29:47 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257292066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2257292066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_random.3840125302 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 422660380 ps |
| CPU time | 10.08 seconds |
| Started | Oct 15 12:29:41 AM UTC 24 |
| Finished | Oct 15 12:29:52 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840125302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3840125302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.2551792051 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 55681487 ps |
| CPU time | 3.08 seconds |
| Started | Oct 15 12:29:41 AM UTC 24 |
| Finished | Oct 15 12:29:45 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551792051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2551792051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.193768929 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 646665335 ps |
| CPU time | 3.76 seconds |
| Started | Oct 15 12:29:41 AM UTC 24 |
| Finished | Oct 15 12:29:45 AM UTC 24 |
| Peak memory | 217548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193768929 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.193768929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.602869539 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 266272969 ps |
| CPU time | 5.41 seconds |
| Started | Oct 15 12:29:41 AM UTC 24 |
| Finished | Oct 15 12:29:47 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602869539 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.602869539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.1537478049 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 72601653 ps |
| CPU time | 4 seconds |
| Started | Oct 15 12:29:41 AM UTC 24 |
| Finished | Oct 15 12:29:46 AM UTC 24 |
| Peak memory | 217868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537478049 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1537478049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.886207403 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 464339867 ps |
| CPU time | 4.31 seconds |
| Started | Oct 15 12:29:43 AM UTC 24 |
| Finished | Oct 15 12:29:49 AM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886207403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.886207403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.333974594 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 74049577 ps |
| CPU time | 2.44 seconds |
| Started | Oct 15 12:29:38 AM UTC 24 |
| Finished | Oct 15 12:29:42 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333974594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.333974594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.2725170092 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1886363168 ps |
| CPU time | 51.05 seconds |
| Started | Oct 15 12:29:43 AM UTC 24 |
| Finished | Oct 15 12:30:36 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725170092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2725170092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.1296961358 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 413906963 ps |
| CPU time | 3.96 seconds |
| Started | Oct 15 12:29:43 AM UTC 24 |
| Finished | Oct 15 12:29:48 AM UTC 24 |
| Peak memory | 219860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296961358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1296961358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.2334851876 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 21398472 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 12:32:27 AM UTC 24 |
| Finished | Oct 15 12:32:29 AM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334851876 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2334851876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.3347933906 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 281231913 ps |
| CPU time | 4.73 seconds |
| Started | Oct 15 12:32:24 AM UTC 24 |
| Finished | Oct 15 12:32:30 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347933906 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3347933906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.521415802 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 111480394 ps |
| CPU time | 5.01 seconds |
| Started | Oct 15 12:32:25 AM UTC 24 |
| Finished | Oct 15 12:32:31 AM UTC 24 |
| Peak memory | 227868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521415802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.521415802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.3355809484 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 191285518 ps |
| CPU time | 3.96 seconds |
| Started | Oct 15 12:32:24 AM UTC 24 |
| Finished | Oct 15 12:32:29 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355809484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3355809484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.2005101927 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 214118416 ps |
| CPU time | 3.99 seconds |
| Started | Oct 15 12:32:25 AM UTC 24 |
| Finished | Oct 15 12:32:30 AM UTC 24 |
| Peak memory | 223676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005101927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2005101927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.3856034370 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 378398609 ps |
| CPU time | 4.45 seconds |
| Started | Oct 15 12:32:25 AM UTC 24 |
| Finished | Oct 15 12:32:31 AM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856034370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3856034370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.1307884948 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 543591347 ps |
| CPU time | 5.27 seconds |
| Started | Oct 15 12:32:24 AM UTC 24 |
| Finished | Oct 15 12:32:30 AM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307884948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1307884948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_random.2578928044 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 197838411 ps |
| CPU time | 7.42 seconds |
| Started | Oct 15 12:32:24 AM UTC 24 |
| Finished | Oct 15 12:32:32 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578928044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2578928044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.1078940511 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 180955560 ps |
| CPU time | 6.41 seconds |
| Started | Oct 15 12:32:23 AM UTC 24 |
| Finished | Oct 15 12:32:30 AM UTC 24 |
| Peak memory | 217368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078940511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1078940511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.4282706342 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 573469891 ps |
| CPU time | 5.2 seconds |
| Started | Oct 15 12:32:23 AM UTC 24 |
| Finished | Oct 15 12:32:29 AM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282706342 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4282706342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.1317367137 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 76022224 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 12:32:23 AM UTC 24 |
| Finished | Oct 15 12:32:27 AM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317367137 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1317367137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.96297066 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 23350459 ps |
| CPU time | 2.59 seconds |
| Started | Oct 15 12:32:23 AM UTC 24 |
| Finished | Oct 15 12:32:26 AM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96297066 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.96297066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.2253626721 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 234342941 ps |
| CPU time | 3.39 seconds |
| Started | Oct 15 12:32:22 AM UTC 24 |
| Finished | Oct 15 12:32:26 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253626721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2253626721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.2831701689 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1579832075 ps |
| CPU time | 16.11 seconds |
| Started | Oct 15 12:32:27 AM UTC 24 |
| Finished | Oct 15 12:32:44 AM UTC 24 |
| Peak memory | 229988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831701689 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2831701689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.3198232054 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 354595284 ps |
| CPU time | 15.42 seconds |
| Started | Oct 15 12:32:27 AM UTC 24 |
| Finished | Oct 15 12:32:43 AM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3198232054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymg r_stress_all_with_rand_reset.3198232054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.1592477722 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 153449806 ps |
| CPU time | 6.33 seconds |
| Started | Oct 15 12:32:25 AM UTC 24 |
| Finished | Oct 15 12:32:33 AM UTC 24 |
| Peak memory | 223696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592477722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1592477722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.2327128347 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 192324818 ps |
| CPU time | 2.9 seconds |
| Started | Oct 15 12:32:27 AM UTC 24 |
| Finished | Oct 15 12:32:30 AM UTC 24 |
| Peak memory | 217620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327128347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2327128347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.4132358244 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 29128639 ps |
| CPU time | 1 seconds |
| Started | Oct 15 12:32:33 AM UTC 24 |
| Finished | Oct 15 12:32:35 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132358244 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4132358244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.2519546181 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 146428641 ps |
| CPU time | 5.18 seconds |
| Started | Oct 15 12:32:32 AM UTC 24 |
| Finished | Oct 15 12:32:38 AM UTC 24 |
| Peak memory | 231196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519546181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2519546181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.141320972 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 196971280 ps |
| CPU time | 2.95 seconds |
| Started | Oct 15 12:32:30 AM UTC 24 |
| Finished | Oct 15 12:32:34 AM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141320972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.141320972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.4009783131 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 70012959 ps |
| CPU time | 3.9 seconds |
| Started | Oct 15 12:32:32 AM UTC 24 |
| Finished | Oct 15 12:32:37 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009783131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.4009783131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.1341288184 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 249403147 ps |
| CPU time | 2.92 seconds |
| Started | Oct 15 12:32:32 AM UTC 24 |
| Finished | Oct 15 12:32:36 AM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341288184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1341288184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_random.1124221353 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 136994398 ps |
| CPU time | 5.84 seconds |
| Started | Oct 15 12:32:29 AM UTC 24 |
| Finished | Oct 15 12:32:36 AM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124221353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1124221353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.2065416267 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 22583776 ps |
| CPU time | 2.33 seconds |
| Started | Oct 15 12:32:28 AM UTC 24 |
| Finished | Oct 15 12:32:31 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065416267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2065416267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.492287073 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 763363760 ps |
| CPU time | 4.5 seconds |
| Started | Oct 15 12:32:28 AM UTC 24 |
| Finished | Oct 15 12:32:34 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492287073 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.492287073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.3464082238 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 112140367 ps |
| CPU time | 2.92 seconds |
| Started | Oct 15 12:32:28 AM UTC 24 |
| Finished | Oct 15 12:32:32 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464082238 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3464082238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.3839342566 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1036663138 ps |
| CPU time | 8.77 seconds |
| Started | Oct 15 12:32:28 AM UTC 24 |
| Finished | Oct 15 12:32:38 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839342566 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3839342566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.3247121327 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 708576933 ps |
| CPU time | 5.42 seconds |
| Started | Oct 15 12:32:32 AM UTC 24 |
| Finished | Oct 15 12:32:38 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247121327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3247121327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.1281052563 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 34424455 ps |
| CPU time | 2.56 seconds |
| Started | Oct 15 12:32:28 AM UTC 24 |
| Finished | Oct 15 12:32:31 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281052563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1281052563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.1204461372 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1210550103 ps |
| CPU time | 7.95 seconds |
| Started | Oct 15 12:32:32 AM UTC 24 |
| Finished | Oct 15 12:32:41 AM UTC 24 |
| Peak memory | 231656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204461372 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1204461372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all_with_rand_reset.2881382419 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1981773516 ps |
| CPU time | 19.44 seconds |
| Started | Oct 15 12:32:33 AM UTC 24 |
| Finished | Oct 15 12:32:54 AM UTC 24 |
| Peak memory | 230132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2881382419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymg r_stress_all_with_rand_reset.2881382419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.2987681581 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 870016844 ps |
| CPU time | 11.55 seconds |
| Started | Oct 15 12:32:30 AM UTC 24 |
| Finished | Oct 15 12:32:43 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987681581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2987681581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.2297968519 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 82676908 ps |
| CPU time | 1.75 seconds |
| Started | Oct 15 12:32:32 AM UTC 24 |
| Finished | Oct 15 12:32:35 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297968519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2297968519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.4276816876 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 12947116 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 12:32:40 AM UTC 24 |
| Finished | Oct 15 12:32:41 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276816876 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.4276816876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.3811515955 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 133073342 ps |
| CPU time | 7.81 seconds |
| Started | Oct 15 12:32:39 AM UTC 24 |
| Finished | Oct 15 12:32:48 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811515955 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3811515955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.2596330241 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 493744397 ps |
| CPU time | 5.11 seconds |
| Started | Oct 15 12:32:39 AM UTC 24 |
| Finished | Oct 15 12:32:45 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596330241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2596330241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.943904059 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1109066190 ps |
| CPU time | 32.28 seconds |
| Started | Oct 15 12:32:39 AM UTC 24 |
| Finished | Oct 15 12:33:13 AM UTC 24 |
| Peak memory | 223756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943904059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.943904059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.3319800693 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 98207818 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 12:32:39 AM UTC 24 |
| Finished | Oct 15 12:32:43 AM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319800693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3319800693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.1958759941 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 123942694 ps |
| CPU time | 6.5 seconds |
| Started | Oct 15 12:32:39 AM UTC 24 |
| Finished | Oct 15 12:32:47 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958759941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1958759941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_random.378511042 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 110264239 ps |
| CPU time | 3.32 seconds |
| Started | Oct 15 12:32:34 AM UTC 24 |
| Finished | Oct 15 12:32:39 AM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378511042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.378511042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.3810784530 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 249427117 ps |
| CPU time | 3.5 seconds |
| Started | Oct 15 12:32:33 AM UTC 24 |
| Finished | Oct 15 12:32:38 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810784530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3810784530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.1056460200 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1730676901 ps |
| CPU time | 20.08 seconds |
| Started | Oct 15 12:32:34 AM UTC 24 |
| Finished | Oct 15 12:32:55 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056460200 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1056460200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.339657841 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 82036665 ps |
| CPU time | 1.86 seconds |
| Started | Oct 15 12:32:33 AM UTC 24 |
| Finished | Oct 15 12:32:36 AM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339657841 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.339657841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.3259822783 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 31396166 ps |
| CPU time | 2.87 seconds |
| Started | Oct 15 12:32:34 AM UTC 24 |
| Finished | Oct 15 12:32:38 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259822783 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3259822783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.2117024104 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 111929872 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 12:32:39 AM UTC 24 |
| Finished | Oct 15 12:32:44 AM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117024104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2117024104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.3599140343 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 130186606 ps |
| CPU time | 2.38 seconds |
| Started | Oct 15 12:32:33 AM UTC 24 |
| Finished | Oct 15 12:32:36 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599140343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3599140343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.3831117119 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 717951324 ps |
| CPU time | 5.89 seconds |
| Started | Oct 15 12:32:39 AM UTC 24 |
| Finished | Oct 15 12:32:46 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831117119 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3831117119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all_with_rand_reset.3824946425 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 485397476 ps |
| CPU time | 20.66 seconds |
| Started | Oct 15 12:32:40 AM UTC 24 |
| Finished | Oct 15 12:33:01 AM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3824946425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymg r_stress_all_with_rand_reset.3824946425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.1749490933 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 268921148 ps |
| CPU time | 5.98 seconds |
| Started | Oct 15 12:32:39 AM UTC 24 |
| Finished | Oct 15 12:32:46 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749490933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1749490933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.1126248336 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 368639372 ps |
| CPU time | 2.75 seconds |
| Started | Oct 15 12:32:39 AM UTC 24 |
| Finished | Oct 15 12:32:43 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126248336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1126248336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.1683348822 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 74601268 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 12:32:47 AM UTC 24 |
| Finished | Oct 15 12:32:49 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683348822 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1683348822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.4121902976 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 301589531 ps |
| CPU time | 14.23 seconds |
| Started | Oct 15 12:32:42 AM UTC 24 |
| Finished | Oct 15 12:32:57 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121902976 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4121902976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.1671743678 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 237514961 ps |
| CPU time | 4.67 seconds |
| Started | Oct 15 12:32:44 AM UTC 24 |
| Finished | Oct 15 12:32:50 AM UTC 24 |
| Peak memory | 217928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671743678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1671743678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.2473159990 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 321397611 ps |
| CPU time | 9.45 seconds |
| Started | Oct 15 12:32:42 AM UTC 24 |
| Finished | Oct 15 12:32:53 AM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473159990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2473159990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.2984385263 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 123320877 ps |
| CPU time | 5.74 seconds |
| Started | Oct 15 12:32:44 AM UTC 24 |
| Finished | Oct 15 12:32:51 AM UTC 24 |
| Peak memory | 223864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984385263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2984385263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.1910871723 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 165811853 ps |
| CPU time | 3.79 seconds |
| Started | Oct 15 12:32:44 AM UTC 24 |
| Finished | Oct 15 12:32:49 AM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910871723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1910871723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.3429516345 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 516348640 ps |
| CPU time | 5.7 seconds |
| Started | Oct 15 12:32:44 AM UTC 24 |
| Finished | Oct 15 12:32:51 AM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429516345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3429516345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_random.443977288 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2148988514 ps |
| CPU time | 12.01 seconds |
| Started | Oct 15 12:32:40 AM UTC 24 |
| Finished | Oct 15 12:32:53 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443977288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.443977288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.237691355 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 620684706 ps |
| CPU time | 6.53 seconds |
| Started | Oct 15 12:32:40 AM UTC 24 |
| Finished | Oct 15 12:32:47 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237691355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.237691355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.3857474317 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 275086211 ps |
| CPU time | 4.43 seconds |
| Started | Oct 15 12:32:40 AM UTC 24 |
| Finished | Oct 15 12:32:45 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857474317 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3857474317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.4208264389 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 940069123 ps |
| CPU time | 12.55 seconds |
| Started | Oct 15 12:32:40 AM UTC 24 |
| Finished | Oct 15 12:32:53 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208264389 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4208264389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.1529440652 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 685730057 ps |
| CPU time | 15.43 seconds |
| Started | Oct 15 12:32:40 AM UTC 24 |
| Finished | Oct 15 12:32:56 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529440652 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1529440652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.3301190920 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 153655328 ps |
| CPU time | 2.79 seconds |
| Started | Oct 15 12:32:44 AM UTC 24 |
| Finished | Oct 15 12:32:48 AM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301190920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3301190920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.613327737 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 180967776 ps |
| CPU time | 2.64 seconds |
| Started | Oct 15 12:32:40 AM UTC 24 |
| Finished | Oct 15 12:32:43 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613327737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.613327737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.2161960185 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 7926499245 ps |
| CPU time | 52.15 seconds |
| Started | Oct 15 12:32:46 AM UTC 24 |
| Finished | Oct 15 12:33:39 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161960185 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2161960185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.2738438351 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 218278264 ps |
| CPU time | 5.74 seconds |
| Started | Oct 15 12:32:44 AM UTC 24 |
| Finished | Oct 15 12:32:51 AM UTC 24 |
| Peak memory | 223788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738438351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2738438351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.4286895990 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 122016762 ps |
| CPU time | 4.39 seconds |
| Started | Oct 15 12:32:46 AM UTC 24 |
| Finished | Oct 15 12:32:51 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286895990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.4286895990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.4185391902 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 64507850 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 12:32:58 AM UTC 24 |
| Finished | Oct 15 12:33:00 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185391902 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.4185391902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.1755957702 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 100839135 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 12:32:57 AM UTC 24 |
| Finished | Oct 15 12:33:02 AM UTC 24 |
| Peak memory | 232112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755957702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1755957702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.2533863139 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 79954167 ps |
| CPU time | 5.16 seconds |
| Started | Oct 15 12:32:57 AM UTC 24 |
| Finished | Oct 15 12:33:03 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533863139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2533863139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.3502573605 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 94276765 ps |
| CPU time | 4.41 seconds |
| Started | Oct 15 12:32:57 AM UTC 24 |
| Finished | Oct 15 12:33:03 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502573605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3502573605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.3097421688 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 375311458 ps |
| CPU time | 3.07 seconds |
| Started | Oct 15 12:32:57 AM UTC 24 |
| Finished | Oct 15 12:33:01 AM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097421688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3097421688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_random.4278404881 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 42434152 ps |
| CPU time | 2.99 seconds |
| Started | Oct 15 12:32:56 AM UTC 24 |
| Finished | Oct 15 12:33:00 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278404881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.4278404881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.1518745095 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 524526901 ps |
| CPU time | 3.59 seconds |
| Started | Oct 15 12:32:48 AM UTC 24 |
| Finished | Oct 15 12:32:52 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518745095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1518745095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.1722243720 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 945822255 ps |
| CPU time | 5.26 seconds |
| Started | Oct 15 12:32:56 AM UTC 24 |
| Finished | Oct 15 12:33:02 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722243720 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1722243720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.802108904 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 31324887 ps |
| CPU time | 2.43 seconds |
| Started | Oct 15 12:32:48 AM UTC 24 |
| Finished | Oct 15 12:32:51 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802108904 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.802108904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.3055659960 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 7414824870 ps |
| CPU time | 49.14 seconds |
| Started | Oct 15 12:32:56 AM UTC 24 |
| Finished | Oct 15 12:33:46 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055659960 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3055659960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.2453141584 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 377237667 ps |
| CPU time | 13 seconds |
| Started | Oct 15 12:32:57 AM UTC 24 |
| Finished | Oct 15 12:33:12 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453141584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2453141584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.4105113389 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 397016802 ps |
| CPU time | 2.99 seconds |
| Started | Oct 15 12:32:48 AM UTC 24 |
| Finished | Oct 15 12:32:52 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105113389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.4105113389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.513492513 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 3656804227 ps |
| CPU time | 27.79 seconds |
| Started | Oct 15 12:32:57 AM UTC 24 |
| Finished | Oct 15 12:33:27 AM UTC 24 |
| Peak memory | 227724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513492513 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.513492513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.1183862818 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 422105221 ps |
| CPU time | 3.7 seconds |
| Started | Oct 15 12:32:57 AM UTC 24 |
| Finished | Oct 15 12:33:02 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183862818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1183862818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.3304680633 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 56546954 ps |
| CPU time | 3.18 seconds |
| Started | Oct 15 12:32:57 AM UTC 24 |
| Finished | Oct 15 12:33:02 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304680633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3304680633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.1756336102 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 14297334 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 12:33:04 AM UTC 24 |
| Finished | Oct 15 12:33:06 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756336102 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1756336102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.3374366262 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 124322621 ps |
| CPU time | 3.64 seconds |
| Started | Oct 15 12:33:02 AM UTC 24 |
| Finished | Oct 15 12:33:07 AM UTC 24 |
| Peak memory | 223936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374366262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3374366262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.3866566778 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 101306828 ps |
| CPU time | 2.45 seconds |
| Started | Oct 15 12:32:59 AM UTC 24 |
| Finished | Oct 15 12:33:02 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866566778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3866566778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.3443280435 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 122774738 ps |
| CPU time | 4.06 seconds |
| Started | Oct 15 12:33:02 AM UTC 24 |
| Finished | Oct 15 12:33:07 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443280435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3443280435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.2092538452 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 789159864 ps |
| CPU time | 6.83 seconds |
| Started | Oct 15 12:33:02 AM UTC 24 |
| Finished | Oct 15 12:33:10 AM UTC 24 |
| Peak memory | 225672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092538452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2092538452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.186250918 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 104738700 ps |
| CPU time | 4.1 seconds |
| Started | Oct 15 12:33:01 AM UTC 24 |
| Finished | Oct 15 12:33:06 AM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186250918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.186250918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_random.3105624765 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 770882324 ps |
| CPU time | 26.89 seconds |
| Started | Oct 15 12:32:58 AM UTC 24 |
| Finished | Oct 15 12:33:26 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105624765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3105624765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.849332750 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 6089056872 ps |
| CPU time | 25.51 seconds |
| Started | Oct 15 12:32:58 AM UTC 24 |
| Finished | Oct 15 12:33:25 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849332750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.849332750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.2642460481 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 157762394 ps |
| CPU time | 5.37 seconds |
| Started | Oct 15 12:32:58 AM UTC 24 |
| Finished | Oct 15 12:33:04 AM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642460481 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2642460481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.4191388923 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 844524164 ps |
| CPU time | 7.16 seconds |
| Started | Oct 15 12:32:58 AM UTC 24 |
| Finished | Oct 15 12:33:06 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191388923 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4191388923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.2066443007 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2284051058 ps |
| CPU time | 9.27 seconds |
| Started | Oct 15 12:32:58 AM UTC 24 |
| Finished | Oct 15 12:33:08 AM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066443007 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2066443007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.3246708513 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 108617927 ps |
| CPU time | 4.39 seconds |
| Started | Oct 15 12:33:02 AM UTC 24 |
| Finished | Oct 15 12:33:08 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246708513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3246708513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.3269617878 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 107021018 ps |
| CPU time | 3.21 seconds |
| Started | Oct 15 12:32:58 AM UTC 24 |
| Finished | Oct 15 12:33:02 AM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269617878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3269617878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.3832919865 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 915607951 ps |
| CPU time | 23.51 seconds |
| Started | Oct 15 12:33:03 AM UTC 24 |
| Finished | Oct 15 12:33:28 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832919865 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3832919865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all_with_rand_reset.3728784671 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 447402685 ps |
| CPU time | 14.44 seconds |
| Started | Oct 15 12:33:04 AM UTC 24 |
| Finished | Oct 15 12:33:19 AM UTC 24 |
| Peak memory | 230848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3728784671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymg r_stress_all_with_rand_reset.3728784671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.2464026965 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 7685002019 ps |
| CPU time | 35.31 seconds |
| Started | Oct 15 12:33:01 AM UTC 24 |
| Finished | Oct 15 12:33:38 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464026965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2464026965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.3911437342 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 37765265 ps |
| CPU time | 2.64 seconds |
| Started | Oct 15 12:33:03 AM UTC 24 |
| Finished | Oct 15 12:33:07 AM UTC 24 |
| Peak memory | 217672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911437342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3911437342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.4225240630 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 56411688 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 12:33:10 AM UTC 24 |
| Finished | Oct 15 12:33:12 AM UTC 24 |
| Peak memory | 213440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225240630 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.4225240630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.3934924269 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 799854426 ps |
| CPU time | 7.21 seconds |
| Started | Oct 15 12:33:09 AM UTC 24 |
| Finished | Oct 15 12:33:17 AM UTC 24 |
| Peak memory | 231020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934924269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3934924269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.2619859759 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 195807377 ps |
| CPU time | 5.76 seconds |
| Started | Oct 15 12:33:07 AM UTC 24 |
| Finished | Oct 15 12:33:14 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619859759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2619859759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.3469526421 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1583712447 ps |
| CPU time | 9.91 seconds |
| Started | Oct 15 12:33:08 AM UTC 24 |
| Finished | Oct 15 12:33:19 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469526421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3469526421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.307902824 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 37961670 ps |
| CPU time | 3.6 seconds |
| Started | Oct 15 12:33:08 AM UTC 24 |
| Finished | Oct 15 12:33:13 AM UTC 24 |
| Peak memory | 231820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307902824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.307902824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.23224916 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 322939302 ps |
| CPU time | 5.86 seconds |
| Started | Oct 15 12:33:07 AM UTC 24 |
| Finished | Oct 15 12:33:14 AM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23224916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.23224916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_random.529491540 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 476197073 ps |
| CPU time | 9.25 seconds |
| Started | Oct 15 12:33:06 AM UTC 24 |
| Finished | Oct 15 12:33:16 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529491540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.529491540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.2909996026 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 250694656 ps |
| CPU time | 7.95 seconds |
| Started | Oct 15 12:33:04 AM UTC 24 |
| Finished | Oct 15 12:33:13 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909996026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2909996026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.382169505 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 35835736 ps |
| CPU time | 3.21 seconds |
| Started | Oct 15 12:33:05 AM UTC 24 |
| Finished | Oct 15 12:33:09 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382169505 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.382169505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.3100932788 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 162333189 ps |
| CPU time | 5.21 seconds |
| Started | Oct 15 12:33:04 AM UTC 24 |
| Finished | Oct 15 12:33:10 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100932788 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3100932788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.3150069194 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 34474342 ps |
| CPU time | 2.98 seconds |
| Started | Oct 15 12:33:05 AM UTC 24 |
| Finished | Oct 15 12:33:09 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150069194 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3150069194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.229507573 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 82548324 ps |
| CPU time | 2.36 seconds |
| Started | Oct 15 12:33:09 AM UTC 24 |
| Finished | Oct 15 12:33:12 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229507573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.229507573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.4076394654 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 335666220 ps |
| CPU time | 3.26 seconds |
| Started | Oct 15 12:33:04 AM UTC 24 |
| Finished | Oct 15 12:33:08 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076394654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4076394654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all_with_rand_reset.1740525827 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 591342821 ps |
| CPU time | 12.87 seconds |
| Started | Oct 15 12:33:10 AM UTC 24 |
| Finished | Oct 15 12:33:24 AM UTC 24 |
| Peak memory | 230260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1740525827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymg r_stress_all_with_rand_reset.1740525827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.317133535 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 133443352 ps |
| CPU time | 7.36 seconds |
| Started | Oct 15 12:33:08 AM UTC 24 |
| Finished | Oct 15 12:33:17 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317133535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.317133535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.3146099113 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 399142530 ps |
| CPU time | 3.54 seconds |
| Started | Oct 15 12:33:09 AM UTC 24 |
| Finished | Oct 15 12:33:13 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146099113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3146099113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.2590743271 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 19371535 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 12:33:19 AM UTC 24 |
| Finished | Oct 15 12:33:21 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590743271 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2590743271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.413295540 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 146798179 ps |
| CPU time | 4.41 seconds |
| Started | Oct 15 12:33:16 AM UTC 24 |
| Finished | Oct 15 12:33:22 AM UTC 24 |
| Peak memory | 225836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413295540 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.413295540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.2000391121 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 82859521 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 12:33:17 AM UTC 24 |
| Finished | Oct 15 12:33:22 AM UTC 24 |
| Peak memory | 217620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000391121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2000391121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.170945270 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 156485431 ps |
| CPU time | 2.36 seconds |
| Started | Oct 15 12:33:16 AM UTC 24 |
| Finished | Oct 15 12:33:20 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170945270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.170945270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.1908835549 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 376335857 ps |
| CPU time | 8.12 seconds |
| Started | Oct 15 12:33:16 AM UTC 24 |
| Finished | Oct 15 12:33:26 AM UTC 24 |
| Peak memory | 231640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908835549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1908835549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.866989119 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 67240709 ps |
| CPU time | 4.79 seconds |
| Started | Oct 15 12:33:16 AM UTC 24 |
| Finished | Oct 15 12:33:22 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866989119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.866989119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_random.1189261887 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 148268945 ps |
| CPU time | 5.77 seconds |
| Started | Oct 15 12:33:16 AM UTC 24 |
| Finished | Oct 15 12:33:23 AM UTC 24 |
| Peak memory | 223796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189261887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1189261887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.3052821795 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 445558553 ps |
| CPU time | 5.52 seconds |
| Started | Oct 15 12:33:11 AM UTC 24 |
| Finished | Oct 15 12:33:18 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052821795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3052821795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.831897209 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1559534060 ps |
| CPU time | 18.14 seconds |
| Started | Oct 15 12:33:16 AM UTC 24 |
| Finished | Oct 15 12:33:36 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831897209 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.831897209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.2546756070 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 84811918 ps |
| CPU time | 2.6 seconds |
| Started | Oct 15 12:33:16 AM UTC 24 |
| Finished | Oct 15 12:33:20 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546756070 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2546756070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.3202554767 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 72215118 ps |
| CPU time | 2.68 seconds |
| Started | Oct 15 12:33:16 AM UTC 24 |
| Finished | Oct 15 12:33:20 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202554767 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3202554767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.490556497 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 662471305 ps |
| CPU time | 6.14 seconds |
| Started | Oct 15 12:33:17 AM UTC 24 |
| Finished | Oct 15 12:33:25 AM UTC 24 |
| Peak memory | 228024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490556497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.490556497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.2602211431 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 568488124 ps |
| CPU time | 5.42 seconds |
| Started | Oct 15 12:33:11 AM UTC 24 |
| Finished | Oct 15 12:33:17 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602211431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2602211431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.658099822 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 344126606 ps |
| CPU time | 15.4 seconds |
| Started | Oct 15 12:33:19 AM UTC 24 |
| Finished | Oct 15 12:33:36 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658099822 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.658099822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.3814919205 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 81738795 ps |
| CPU time | 3.83 seconds |
| Started | Oct 15 12:33:16 AM UTC 24 |
| Finished | Oct 15 12:33:21 AM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814919205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3814919205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.827134513 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 327144310 ps |
| CPU time | 2.95 seconds |
| Started | Oct 15 12:33:18 AM UTC 24 |
| Finished | Oct 15 12:33:22 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827134513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.827134513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.1121306162 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 19459389 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 12:33:26 AM UTC 24 |
| Finished | Oct 15 12:33:28 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121306162 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1121306162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.1549387775 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 112419686 ps |
| CPU time | 7.97 seconds |
| Started | Oct 15 12:33:22 AM UTC 24 |
| Finished | Oct 15 12:33:32 AM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549387775 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1549387775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.1595254462 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 50163859 ps |
| CPU time | 3.49 seconds |
| Started | Oct 15 12:33:24 AM UTC 24 |
| Finished | Oct 15 12:33:28 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595254462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1595254462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.217441514 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 184287567 ps |
| CPU time | 6.72 seconds |
| Started | Oct 15 12:33:22 AM UTC 24 |
| Finished | Oct 15 12:33:30 AM UTC 24 |
| Peak memory | 217700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217441514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.217441514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.195452652 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 271223185 ps |
| CPU time | 4.46 seconds |
| Started | Oct 15 12:33:24 AM UTC 24 |
| Finished | Oct 15 12:33:29 AM UTC 24 |
| Peak memory | 231756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195452652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.195452652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.426231125 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 304429448 ps |
| CPU time | 4.18 seconds |
| Started | Oct 15 12:33:24 AM UTC 24 |
| Finished | Oct 15 12:33:29 AM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426231125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.426231125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.2918899461 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 196147152 ps |
| CPU time | 3.68 seconds |
| Started | Oct 15 12:33:22 AM UTC 24 |
| Finished | Oct 15 12:33:27 AM UTC 24 |
| Peak memory | 217436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918899461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2918899461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_random.3589332117 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 620976418 ps |
| CPU time | 5.69 seconds |
| Started | Oct 15 12:33:22 AM UTC 24 |
| Finished | Oct 15 12:33:29 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589332117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3589332117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.3285359232 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 187292048 ps |
| CPU time | 2.98 seconds |
| Started | Oct 15 12:33:20 AM UTC 24 |
| Finished | Oct 15 12:33:24 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285359232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3285359232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.33536505 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 251934383 ps |
| CPU time | 4.72 seconds |
| Started | Oct 15 12:33:21 AM UTC 24 |
| Finished | Oct 15 12:33:27 AM UTC 24 |
| Peak memory | 217700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33536505 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.33536505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.3364032352 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 50907895 ps |
| CPU time | 2.86 seconds |
| Started | Oct 15 12:33:21 AM UTC 24 |
| Finished | Oct 15 12:33:25 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364032352 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3364032352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.2635264387 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 204204867 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 12:33:21 AM UTC 24 |
| Finished | Oct 15 12:33:25 AM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635264387 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2635264387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.709216191 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 276664249 ps |
| CPU time | 4.19 seconds |
| Started | Oct 15 12:33:25 AM UTC 24 |
| Finished | Oct 15 12:33:30 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709216191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.709216191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.3740877974 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2466939269 ps |
| CPU time | 9.2 seconds |
| Started | Oct 15 12:33:20 AM UTC 24 |
| Finished | Oct 15 12:33:31 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740877974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3740877974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.1454198007 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 729913987 ps |
| CPU time | 16.14 seconds |
| Started | Oct 15 12:33:26 AM UTC 24 |
| Finished | Oct 15 12:33:43 AM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454198007 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1454198007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.3036394301 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 765684997 ps |
| CPU time | 7.64 seconds |
| Started | Oct 15 12:33:24 AM UTC 24 |
| Finished | Oct 15 12:33:32 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036394301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3036394301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.3039331209 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 437018289 ps |
| CPU time | 3.21 seconds |
| Started | Oct 15 12:33:25 AM UTC 24 |
| Finished | Oct 15 12:33:29 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039331209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3039331209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.927670474 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 25162266 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 12:33:38 AM UTC 24 |
| Finished | Oct 15 12:33:41 AM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927670474 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.927670474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.1385249296 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 37905088 ps |
| CPU time | 2.82 seconds |
| Started | Oct 15 12:33:29 AM UTC 24 |
| Finished | Oct 15 12:33:33 AM UTC 24 |
| Peak memory | 223792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385249296 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1385249296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.370511790 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 9586830757 ps |
| CPU time | 15.66 seconds |
| Started | Oct 15 12:33:37 AM UTC 24 |
| Finished | Oct 15 12:33:54 AM UTC 24 |
| Peak memory | 217496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370511790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.370511790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.2968582339 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 288690618 ps |
| CPU time | 4.84 seconds |
| Started | Oct 15 12:33:37 AM UTC 24 |
| Finished | Oct 15 12:33:43 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968582339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2968582339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.534136990 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 50238761 ps |
| CPU time | 3.27 seconds |
| Started | Oct 15 12:33:37 AM UTC 24 |
| Finished | Oct 15 12:33:42 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534136990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.534136990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.834484729 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 125268592 ps |
| CPU time | 5.47 seconds |
| Started | Oct 15 12:33:37 AM UTC 24 |
| Finished | Oct 15 12:33:44 AM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834484729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.834484729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.2228943892 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 145063808 ps |
| CPU time | 3.3 seconds |
| Started | Oct 15 12:33:37 AM UTC 24 |
| Finished | Oct 15 12:33:42 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228943892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2228943892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_random.804575466 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 69968192 ps |
| CPU time | 4.29 seconds |
| Started | Oct 15 12:33:29 AM UTC 24 |
| Finished | Oct 15 12:33:34 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804575466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.804575466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.1656857537 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3148176478 ps |
| CPU time | 26.53 seconds |
| Started | Oct 15 12:33:26 AM UTC 24 |
| Finished | Oct 15 12:33:54 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656857537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1656857537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.4191419007 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 413213095 ps |
| CPU time | 6.19 seconds |
| Started | Oct 15 12:33:27 AM UTC 24 |
| Finished | Oct 15 12:33:35 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191419007 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.4191419007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.1392841863 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 54657898 ps |
| CPU time | 2.43 seconds |
| Started | Oct 15 12:33:27 AM UTC 24 |
| Finished | Oct 15 12:33:31 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392841863 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1392841863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.2305682531 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 860662899 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 12:33:29 AM UTC 24 |
| Finished | Oct 15 12:33:33 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305682531 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2305682531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.4157852363 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 46793992 ps |
| CPU time | 2.4 seconds |
| Started | Oct 15 12:33:37 AM UTC 24 |
| Finished | Oct 15 12:33:41 AM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157852363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4157852363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.3392377443 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 114999718 ps |
| CPU time | 4.64 seconds |
| Started | Oct 15 12:33:26 AM UTC 24 |
| Finished | Oct 15 12:33:32 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392377443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3392377443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.3427103277 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 891903117 ps |
| CPU time | 7.19 seconds |
| Started | Oct 15 12:33:37 AM UTC 24 |
| Finished | Oct 15 12:33:46 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427103277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3427103277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.1709589509 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 137006358 ps |
| CPU time | 3.56 seconds |
| Started | Oct 15 12:33:37 AM UTC 24 |
| Finished | Oct 15 12:33:42 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709589509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1709589509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.1717516252 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 24317185 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 12:30:01 AM UTC 24 |
| Finished | Oct 15 12:30:03 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717516252 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1717516252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.85655471 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 43514623 ps |
| CPU time | 3.95 seconds |
| Started | Oct 15 12:29:50 AM UTC 24 |
| Finished | Oct 15 12:29:55 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85655471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.85655471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.2703405409 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 5820744460 ps |
| CPU time | 49.04 seconds |
| Started | Oct 15 12:29:50 AM UTC 24 |
| Finished | Oct 15 12:30:41 AM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703405409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2703405409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.2503621852 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 116815787 ps |
| CPU time | 7.67 seconds |
| Started | Oct 15 12:29:53 AM UTC 24 |
| Finished | Oct 15 12:30:01 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503621852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2503621852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.3159473894 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 71069778 ps |
| CPU time | 3.8 seconds |
| Started | Oct 15 12:29:51 AM UTC 24 |
| Finished | Oct 15 12:29:56 AM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159473894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3159473894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_random.4195155624 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 728475140 ps |
| CPU time | 9.75 seconds |
| Started | Oct 15 12:29:50 AM UTC 24 |
| Finished | Oct 15 12:30:01 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195155624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.4195155624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.3066642230 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3068356519 ps |
| CPU time | 14.5 seconds |
| Started | Oct 15 12:29:55 AM UTC 24 |
| Finished | Oct 15 12:30:11 AM UTC 24 |
| Peak memory | 253556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066642230 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3066642230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.1585800005 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1180344195 ps |
| CPU time | 16.54 seconds |
| Started | Oct 15 12:29:49 AM UTC 24 |
| Finished | Oct 15 12:30:07 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585800005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1585800005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.1351671746 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 254693752 ps |
| CPU time | 4.59 seconds |
| Started | Oct 15 12:29:49 AM UTC 24 |
| Finished | Oct 15 12:29:55 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351671746 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1351671746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.2382472518 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 49379255 ps |
| CPU time | 2.95 seconds |
| Started | Oct 15 12:29:49 AM UTC 24 |
| Finished | Oct 15 12:29:53 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382472518 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2382472518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.3856440554 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 365885579 ps |
| CPU time | 6.36 seconds |
| Started | Oct 15 12:29:50 AM UTC 24 |
| Finished | Oct 15 12:29:58 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856440554 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3856440554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.207757800 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 318509708 ps |
| CPU time | 2.59 seconds |
| Started | Oct 15 12:29:54 AM UTC 24 |
| Finished | Oct 15 12:29:57 AM UTC 24 |
| Peak memory | 225972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207757800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.207757800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.286448358 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 88706253 ps |
| CPU time | 2.7 seconds |
| Started | Oct 15 12:29:49 AM UTC 24 |
| Finished | Oct 15 12:29:53 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286448358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.286448358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all_with_rand_reset.1984317528 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 333409161 ps |
| CPU time | 10.1 seconds |
| Started | Oct 15 12:29:55 AM UTC 24 |
| Finished | Oct 15 12:30:06 AM UTC 24 |
| Peak memory | 230128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1984317528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr _stress_all_with_rand_reset.1984317528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.686499758 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 98604057 ps |
| CPU time | 5.36 seconds |
| Started | Oct 15 12:29:51 AM UTC 24 |
| Finished | Oct 15 12:29:58 AM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686499758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.686499758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.4204675048 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 76718337 ps |
| CPU time | 3.38 seconds |
| Started | Oct 15 12:29:54 AM UTC 24 |
| Finished | Oct 15 12:29:58 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204675048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.4204675048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.3146926745 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 14135149 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 12:33:42 AM UTC 24 |
| Finished | Oct 15 12:33:44 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146926745 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3146926745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.2792968751 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 106581212 ps |
| CPU time | 3.08 seconds |
| Started | Oct 15 12:33:40 AM UTC 24 |
| Finished | Oct 15 12:33:44 AM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792968751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2792968751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.2694156875 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 2771706614 ps |
| CPU time | 27.74 seconds |
| Started | Oct 15 12:33:38 AM UTC 24 |
| Finished | Oct 15 12:34:08 AM UTC 24 |
| Peak memory | 223884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694156875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2694156875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.186647060 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 750023731 ps |
| CPU time | 8.09 seconds |
| Started | Oct 15 12:33:39 AM UTC 24 |
| Finished | Oct 15 12:33:48 AM UTC 24 |
| Peak memory | 223884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186647060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.186647060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.1485645393 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 263323033 ps |
| CPU time | 4.87 seconds |
| Started | Oct 15 12:33:39 AM UTC 24 |
| Finished | Oct 15 12:33:45 AM UTC 24 |
| Peak memory | 225648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485645393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1485645393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.229820254 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 211366769 ps |
| CPU time | 6.1 seconds |
| Started | Oct 15 12:33:39 AM UTC 24 |
| Finished | Oct 15 12:33:46 AM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229820254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.229820254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_random.3495854634 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 477064690 ps |
| CPU time | 4.83 seconds |
| Started | Oct 15 12:33:38 AM UTC 24 |
| Finished | Oct 15 12:33:45 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495854634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3495854634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.236454808 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 70060322 ps |
| CPU time | 2.23 seconds |
| Started | Oct 15 12:33:38 AM UTC 24 |
| Finished | Oct 15 12:33:42 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236454808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.236454808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.232996999 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 65618949 ps |
| CPU time | 4.28 seconds |
| Started | Oct 15 12:33:38 AM UTC 24 |
| Finished | Oct 15 12:33:44 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232996999 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.232996999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.500354162 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 56142082 ps |
| CPU time | 2.78 seconds |
| Started | Oct 15 12:33:38 AM UTC 24 |
| Finished | Oct 15 12:33:42 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500354162 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.500354162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.195395986 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 637026935 ps |
| CPU time | 5.38 seconds |
| Started | Oct 15 12:33:38 AM UTC 24 |
| Finished | Oct 15 12:33:45 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195395986 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.195395986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.3374270 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 70214336 ps |
| CPU time | 2.31 seconds |
| Started | Oct 15 12:33:40 AM UTC 24 |
| Finished | Oct 15 12:33:43 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k eymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3374270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.267397513 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 439681784 ps |
| CPU time | 6.49 seconds |
| Started | Oct 15 12:33:38 AM UTC 24 |
| Finished | Oct 15 12:33:46 AM UTC 24 |
| Peak memory | 215372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267397513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.267397513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.4039890800 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 74463002 ps |
| CPU time | 3.11 seconds |
| Started | Oct 15 12:33:42 AM UTC 24 |
| Finished | Oct 15 12:33:46 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039890800 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.4039890800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all_with_rand_reset.2006550744 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 560382867 ps |
| CPU time | 9.92 seconds |
| Started | Oct 15 12:33:42 AM UTC 24 |
| Finished | Oct 15 12:33:53 AM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2006550744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymg r_stress_all_with_rand_reset.2006550744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.1117846995 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 149967155 ps |
| CPU time | 5.16 seconds |
| Started | Oct 15 12:33:39 AM UTC 24 |
| Finished | Oct 15 12:33:45 AM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117846995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1117846995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.309653869 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 213336192 ps |
| CPU time | 4.78 seconds |
| Started | Oct 15 12:33:41 AM UTC 24 |
| Finished | Oct 15 12:33:47 AM UTC 24 |
| Peak memory | 219728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309653869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.309653869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.190292170 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 47770738 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 12:33:47 AM UTC 24 |
| Finished | Oct 15 12:33:50 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190292170 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.190292170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.2970430837 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 116410163 ps |
| CPU time | 3.64 seconds |
| Started | Oct 15 12:33:46 AM UTC 24 |
| Finished | Oct 15 12:33:51 AM UTC 24 |
| Peak memory | 227772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970430837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2970430837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.3782489240 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 85466507 ps |
| CPU time | 4.9 seconds |
| Started | Oct 15 12:33:45 AM UTC 24 |
| Finished | Oct 15 12:33:51 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782489240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3782489240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.2659933826 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 706008733 ps |
| CPU time | 3.22 seconds |
| Started | Oct 15 12:33:46 AM UTC 24 |
| Finished | Oct 15 12:33:50 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659933826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2659933826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.159250520 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 69678073 ps |
| CPU time | 2.65 seconds |
| Started | Oct 15 12:33:46 AM UTC 24 |
| Finished | Oct 15 12:33:50 AM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159250520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.159250520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.2581242634 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 112027844 ps |
| CPU time | 1.56 seconds |
| Started | Oct 15 12:33:45 AM UTC 24 |
| Finished | Oct 15 12:33:47 AM UTC 24 |
| Peak memory | 213324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581242634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2581242634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_random.3983835081 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 654128255 ps |
| CPU time | 11.84 seconds |
| Started | Oct 15 12:33:45 AM UTC 24 |
| Finished | Oct 15 12:33:58 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983835081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3983835081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.3720737652 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 39688573 ps |
| CPU time | 2.25 seconds |
| Started | Oct 15 12:33:43 AM UTC 24 |
| Finished | Oct 15 12:33:47 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720737652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3720737652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.1681596610 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 316310587 ps |
| CPU time | 5.99 seconds |
| Started | Oct 15 12:33:45 AM UTC 24 |
| Finished | Oct 15 12:33:52 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681596610 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1681596610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.2542567649 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 214959435 ps |
| CPU time | 2.8 seconds |
| Started | Oct 15 12:33:43 AM UTC 24 |
| Finished | Oct 15 12:33:47 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542567649 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2542567649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.139872821 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 208399965 ps |
| CPU time | 7.27 seconds |
| Started | Oct 15 12:33:45 AM UTC 24 |
| Finished | Oct 15 12:33:53 AM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139872821 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.139872821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.2231628265 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 273675485 ps |
| CPU time | 4.49 seconds |
| Started | Oct 15 12:33:46 AM UTC 24 |
| Finished | Oct 15 12:33:52 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231628265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2231628265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.227008863 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1111642188 ps |
| CPU time | 21.51 seconds |
| Started | Oct 15 12:33:42 AM UTC 24 |
| Finished | Oct 15 12:34:05 AM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227008863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.227008863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.2605507060 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 682210562 ps |
| CPU time | 26.18 seconds |
| Started | Oct 15 12:33:47 AM UTC 24 |
| Finished | Oct 15 12:34:15 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605507060 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2605507060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all_with_rand_reset.3314584045 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 336651875 ps |
| CPU time | 15.23 seconds |
| Started | Oct 15 12:33:47 AM UTC 24 |
| Finished | Oct 15 12:34:04 AM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3314584045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymg r_stress_all_with_rand_reset.3314584045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.3466201350 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 516830509 ps |
| CPU time | 12.65 seconds |
| Started | Oct 15 12:33:46 AM UTC 24 |
| Finished | Oct 15 12:34:00 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466201350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3466201350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.3396460357 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 42087505 ps |
| CPU time | 2.6 seconds |
| Started | Oct 15 12:33:47 AM UTC 24 |
| Finished | Oct 15 12:33:51 AM UTC 24 |
| Peak memory | 219768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396460357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3396460357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.280359112 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 57341351 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 12:33:53 AM UTC 24 |
| Finished | Oct 15 12:33:56 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280359112 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.280359112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.17441355 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1214307984 ps |
| CPU time | 14.07 seconds |
| Started | Oct 15 12:33:49 AM UTC 24 |
| Finished | Oct 15 12:34:04 AM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17441355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.17441355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.2419344342 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 87621866 ps |
| CPU time | 3.86 seconds |
| Started | Oct 15 12:33:52 AM UTC 24 |
| Finished | Oct 15 12:33:57 AM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419344342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2419344342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.4183609868 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 43135676 ps |
| CPU time | 2.72 seconds |
| Started | Oct 15 12:33:49 AM UTC 24 |
| Finished | Oct 15 12:33:53 AM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183609868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.4183609868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.1032246038 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 327649233 ps |
| CPU time | 5.78 seconds |
| Started | Oct 15 12:33:51 AM UTC 24 |
| Finished | Oct 15 12:33:58 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032246038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1032246038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.4154948570 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 162835346 ps |
| CPU time | 2.88 seconds |
| Started | Oct 15 12:33:52 AM UTC 24 |
| Finished | Oct 15 12:33:56 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154948570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.4154948570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.3236159444 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 249404785 ps |
| CPU time | 2.77 seconds |
| Started | Oct 15 12:33:50 AM UTC 24 |
| Finished | Oct 15 12:33:54 AM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236159444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3236159444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_random.3362827502 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 58599624 ps |
| CPU time | 3.8 seconds |
| Started | Oct 15 12:33:49 AM UTC 24 |
| Finished | Oct 15 12:33:54 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362827502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3362827502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.127811047 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 50482608 ps |
| CPU time | 3.2 seconds |
| Started | Oct 15 12:33:48 AM UTC 24 |
| Finished | Oct 15 12:33:52 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127811047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.127811047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.2935957591 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 925666078 ps |
| CPU time | 28.5 seconds |
| Started | Oct 15 12:33:48 AM UTC 24 |
| Finished | Oct 15 12:34:18 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935957591 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2935957591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.3869472613 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1894657966 ps |
| CPU time | 14.25 seconds |
| Started | Oct 15 12:33:48 AM UTC 24 |
| Finished | Oct 15 12:34:03 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869472613 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3869472613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.979930929 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 247203167 ps |
| CPU time | 3.68 seconds |
| Started | Oct 15 12:33:49 AM UTC 24 |
| Finished | Oct 15 12:33:53 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979930929 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.979930929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.4065717457 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 259395750 ps |
| CPU time | 3.18 seconds |
| Started | Oct 15 12:33:52 AM UTC 24 |
| Finished | Oct 15 12:33:56 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065717457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.4065717457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.1771617100 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 376522369 ps |
| CPU time | 4.18 seconds |
| Started | Oct 15 12:33:47 AM UTC 24 |
| Finished | Oct 15 12:33:53 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771617100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1771617100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.2646646158 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 49397150885 ps |
| CPU time | 218.19 seconds |
| Started | Oct 15 12:33:52 AM UTC 24 |
| Finished | Oct 15 12:37:34 AM UTC 24 |
| Peak memory | 231768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646646158 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2646646158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.2383132955 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 288768174 ps |
| CPU time | 5 seconds |
| Started | Oct 15 12:33:51 AM UTC 24 |
| Finished | Oct 15 12:33:57 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383132955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2383132955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.668827784 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 185902428 ps |
| CPU time | 3.61 seconds |
| Started | Oct 15 12:33:52 AM UTC 24 |
| Finished | Oct 15 12:33:57 AM UTC 24 |
| Peak memory | 219896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668827784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.668827784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.204845202 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 19953523 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 12:33:59 AM UTC 24 |
| Finished | Oct 15 12:34:01 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204845202 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.204845202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.830160900 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 48218100 ps |
| CPU time | 4.9 seconds |
| Started | Oct 15 12:33:55 AM UTC 24 |
| Finished | Oct 15 12:34:01 AM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830160900 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.830160900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.4178631304 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 30301525 ps |
| CPU time | 2.72 seconds |
| Started | Oct 15 12:33:57 AM UTC 24 |
| Finished | Oct 15 12:34:01 AM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178631304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.4178631304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.1226266144 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 66530403 ps |
| CPU time | 3.07 seconds |
| Started | Oct 15 12:33:55 AM UTC 24 |
| Finished | Oct 15 12:33:59 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226266144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1226266144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.1335395114 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 79294761 ps |
| CPU time | 2.68 seconds |
| Started | Oct 15 12:33:57 AM UTC 24 |
| Finished | Oct 15 12:34:01 AM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335395114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1335395114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.3041203438 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 82250413 ps |
| CPU time | 3.25 seconds |
| Started | Oct 15 12:33:55 AM UTC 24 |
| Finished | Oct 15 12:33:59 AM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041203438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3041203438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_random.3182371345 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 694133869 ps |
| CPU time | 5.99 seconds |
| Started | Oct 15 12:33:55 AM UTC 24 |
| Finished | Oct 15 12:34:02 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182371345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3182371345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.1400355788 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 1397811642 ps |
| CPU time | 25.17 seconds |
| Started | Oct 15 12:33:54 AM UTC 24 |
| Finished | Oct 15 12:34:20 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400355788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1400355788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.717138963 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3043658946 ps |
| CPU time | 11.07 seconds |
| Started | Oct 15 12:33:55 AM UTC 24 |
| Finished | Oct 15 12:34:07 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717138963 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.717138963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.2980148954 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 17158187265 ps |
| CPU time | 61.58 seconds |
| Started | Oct 15 12:33:54 AM UTC 24 |
| Finished | Oct 15 12:34:57 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980148954 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2980148954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.3695027494 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 64225668 ps |
| CPU time | 3.99 seconds |
| Started | Oct 15 12:33:55 AM UTC 24 |
| Finished | Oct 15 12:34:00 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695027494 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3695027494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.2985849242 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 160976005 ps |
| CPU time | 6.84 seconds |
| Started | Oct 15 12:33:57 AM UTC 24 |
| Finished | Oct 15 12:34:05 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985849242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2985849242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.1516110742 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 70179570 ps |
| CPU time | 2.29 seconds |
| Started | Oct 15 12:33:54 AM UTC 24 |
| Finished | Oct 15 12:33:57 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516110742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1516110742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.3445049727 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1241409649 ps |
| CPU time | 43.56 seconds |
| Started | Oct 15 12:33:59 AM UTC 24 |
| Finished | Oct 15 12:34:44 AM UTC 24 |
| Peak memory | 231140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445049727 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3445049727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.2456401446 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 918098668 ps |
| CPU time | 23.52 seconds |
| Started | Oct 15 12:33:56 AM UTC 24 |
| Finished | Oct 15 12:34:21 AM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456401446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2456401446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.2405161558 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 890581352 ps |
| CPU time | 3.68 seconds |
| Started | Oct 15 12:33:59 AM UTC 24 |
| Finished | Oct 15 12:34:03 AM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405161558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2405161558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.1115561850 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 22009935 ps |
| CPU time | 1.35 seconds |
| Started | Oct 15 12:34:06 AM UTC 24 |
| Finished | Oct 15 12:34:08 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115561850 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1115561850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.3450795609 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 621340745 ps |
| CPU time | 17.77 seconds |
| Started | Oct 15 12:34:02 AM UTC 24 |
| Finished | Oct 15 12:34:21 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450795609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3450795609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.1203716695 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1234842904 ps |
| CPU time | 11.37 seconds |
| Started | Oct 15 12:34:04 AM UTC 24 |
| Finished | Oct 15 12:34:16 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203716695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1203716695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.1693259720 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 41192515 ps |
| CPU time | 3.66 seconds |
| Started | Oct 15 12:34:04 AM UTC 24 |
| Finished | Oct 15 12:34:08 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693259720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1693259720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.1524442278 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4214347878 ps |
| CPU time | 10.83 seconds |
| Started | Oct 15 12:34:02 AM UTC 24 |
| Finished | Oct 15 12:34:14 AM UTC 24 |
| Peak memory | 231844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524442278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1524442278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_random.1647153997 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 59870037 ps |
| CPU time | 4.88 seconds |
| Started | Oct 15 12:34:02 AM UTC 24 |
| Finished | Oct 15 12:34:08 AM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647153997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1647153997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.4099154166 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 81629579 ps |
| CPU time | 3.59 seconds |
| Started | Oct 15 12:34:00 AM UTC 24 |
| Finished | Oct 15 12:34:04 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099154166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4099154166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.961164890 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 58548996 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 12:34:01 AM UTC 24 |
| Finished | Oct 15 12:34:04 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961164890 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.961164890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.1545475654 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 109863965 ps |
| CPU time | 5.23 seconds |
| Started | Oct 15 12:34:01 AM UTC 24 |
| Finished | Oct 15 12:34:07 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545475654 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1545475654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.4013722709 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 197393541 ps |
| CPU time | 2.66 seconds |
| Started | Oct 15 12:34:02 AM UTC 24 |
| Finished | Oct 15 12:34:06 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013722709 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.4013722709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.3379118667 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 68978487 ps |
| CPU time | 2.94 seconds |
| Started | Oct 15 12:34:05 AM UTC 24 |
| Finished | Oct 15 12:34:09 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379118667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3379118667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.2464276328 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 385599942 ps |
| CPU time | 11.7 seconds |
| Started | Oct 15 12:34:00 AM UTC 24 |
| Finished | Oct 15 12:34:13 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464276328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2464276328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.4155504593 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1718418887 ps |
| CPU time | 5.02 seconds |
| Started | Oct 15 12:34:05 AM UTC 24 |
| Finished | Oct 15 12:34:11 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155504593 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.4155504593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.2092862119 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 329562040 ps |
| CPU time | 14.57 seconds |
| Started | Oct 15 12:34:05 AM UTC 24 |
| Finished | Oct 15 12:34:21 AM UTC 24 |
| Peak memory | 231824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2092862119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymg r_stress_all_with_rand_reset.2092862119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.2559144444 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 703582525 ps |
| CPU time | 6.77 seconds |
| Started | Oct 15 12:34:03 AM UTC 24 |
| Finished | Oct 15 12:34:11 AM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559144444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2559144444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.1314999678 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 146361980 ps |
| CPU time | 2.85 seconds |
| Started | Oct 15 12:34:05 AM UTC 24 |
| Finished | Oct 15 12:34:09 AM UTC 24 |
| Peak memory | 219920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314999678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1314999678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.2070536279 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 50565831 ps |
| CPU time | 1.37 seconds |
| Started | Oct 15 12:34:13 AM UTC 24 |
| Finished | Oct 15 12:34:16 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070536279 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2070536279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.3089136764 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 203601112 ps |
| CPU time | 3.24 seconds |
| Started | Oct 15 12:34:10 AM UTC 24 |
| Finished | Oct 15 12:34:14 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089136764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3089136764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.3917423414 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 41035705 ps |
| CPU time | 2.71 seconds |
| Started | Oct 15 12:34:10 AM UTC 24 |
| Finished | Oct 15 12:34:13 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917423414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3917423414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.3320236756 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 108655674 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 12:34:11 AM UTC 24 |
| Finished | Oct 15 12:34:17 AM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320236756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3320236756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.2439907629 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 221908836 ps |
| CPU time | 4.9 seconds |
| Started | Oct 15 12:34:10 AM UTC 24 |
| Finished | Oct 15 12:34:16 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439907629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2439907629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_random.3975735070 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 7406526973 ps |
| CPU time | 60.67 seconds |
| Started | Oct 15 12:34:08 AM UTC 24 |
| Finished | Oct 15 12:35:11 AM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975735070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3975735070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.3172406213 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 101870207 ps |
| CPU time | 4.53 seconds |
| Started | Oct 15 12:34:06 AM UTC 24 |
| Finished | Oct 15 12:34:12 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172406213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3172406213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.1542656021 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 46143647 ps |
| CPU time | 3.23 seconds |
| Started | Oct 15 12:34:08 AM UTC 24 |
| Finished | Oct 15 12:34:13 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542656021 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1542656021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.2631737370 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 71270286 ps |
| CPU time | 5.09 seconds |
| Started | Oct 15 12:34:07 AM UTC 24 |
| Finished | Oct 15 12:34:13 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631737370 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2631737370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.2230745543 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 57289562 ps |
| CPU time | 4.14 seconds |
| Started | Oct 15 12:34:08 AM UTC 24 |
| Finished | Oct 15 12:34:13 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230745543 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2230745543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.1558934124 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 233205865 ps |
| CPU time | 7.75 seconds |
| Started | Oct 15 12:34:12 AM UTC 24 |
| Finished | Oct 15 12:34:21 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558934124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1558934124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.4282926230 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 943433323 ps |
| CPU time | 6.87 seconds |
| Started | Oct 15 12:34:06 AM UTC 24 |
| Finished | Oct 15 12:34:14 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282926230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.4282926230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.3761908930 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 852810595 ps |
| CPU time | 17.19 seconds |
| Started | Oct 15 12:34:13 AM UTC 24 |
| Finished | Oct 15 12:34:32 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761908930 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3761908930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.3073723398 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 109738002 ps |
| CPU time | 5.91 seconds |
| Started | Oct 15 12:34:10 AM UTC 24 |
| Finished | Oct 15 12:34:17 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073723398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3073723398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.4025033025 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 118145627 ps |
| CPU time | 1.7 seconds |
| Started | Oct 15 12:34:12 AM UTC 24 |
| Finished | Oct 15 12:34:15 AM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025033025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.4025033025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.2973837301 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 48305005 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 12:34:25 AM UTC 24 |
| Finished | Oct 15 12:34:27 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973837301 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2973837301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.1812608653 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 318700690 ps |
| CPU time | 6.25 seconds |
| Started | Oct 15 12:34:16 AM UTC 24 |
| Finished | Oct 15 12:34:23 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812608653 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1812608653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.4174789476 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 143309155 ps |
| CPU time | 4.18 seconds |
| Started | Oct 15 12:34:17 AM UTC 24 |
| Finished | Oct 15 12:34:22 AM UTC 24 |
| Peak memory | 230152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174789476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.4174789476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.60524789 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 132726622 ps |
| CPU time | 2.79 seconds |
| Started | Oct 15 12:34:16 AM UTC 24 |
| Finished | Oct 15 12:34:20 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60524789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.60524789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.182947147 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 100980891 ps |
| CPU time | 3.89 seconds |
| Started | Oct 15 12:34:17 AM UTC 24 |
| Finished | Oct 15 12:34:22 AM UTC 24 |
| Peak memory | 230736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182947147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.182947147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.3874212818 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 335741324 ps |
| CPU time | 3.49 seconds |
| Started | Oct 15 12:34:17 AM UTC 24 |
| Finished | Oct 15 12:34:22 AM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874212818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3874212818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.2849338825 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 151853082 ps |
| CPU time | 7.82 seconds |
| Started | Oct 15 12:34:16 AM UTC 24 |
| Finished | Oct 15 12:34:25 AM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849338825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2849338825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_random.2749876033 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1238872336 ps |
| CPU time | 4.9 seconds |
| Started | Oct 15 12:34:16 AM UTC 24 |
| Finished | Oct 15 12:34:22 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749876033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2749876033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.344893947 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 19756626 ps |
| CPU time | 1.85 seconds |
| Started | Oct 15 12:34:14 AM UTC 24 |
| Finished | Oct 15 12:34:17 AM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344893947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.344893947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.2403789708 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 90024112 ps |
| CPU time | 4.38 seconds |
| Started | Oct 15 12:34:15 AM UTC 24 |
| Finished | Oct 15 12:34:20 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403789708 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2403789708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.446166336 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 26386517 ps |
| CPU time | 2.86 seconds |
| Started | Oct 15 12:34:14 AM UTC 24 |
| Finished | Oct 15 12:34:18 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446166336 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.446166336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.867664131 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 79068511 ps |
| CPU time | 2.62 seconds |
| Started | Oct 15 12:34:15 AM UTC 24 |
| Finished | Oct 15 12:34:18 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867664131 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.867664131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.244557941 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 491228953 ps |
| CPU time | 2.84 seconds |
| Started | Oct 15 12:34:17 AM UTC 24 |
| Finished | Oct 15 12:34:21 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244557941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.244557941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.390813422 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1056474343 ps |
| CPU time | 6.81 seconds |
| Started | Oct 15 12:34:14 AM UTC 24 |
| Finished | Oct 15 12:34:22 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390813422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.390813422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.319126743 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 93164466 ps |
| CPU time | 5.65 seconds |
| Started | Oct 15 12:34:16 AM UTC 24 |
| Finished | Oct 15 12:34:23 AM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319126743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.319126743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.4250430921 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 57441103 ps |
| CPU time | 1.68 seconds |
| Started | Oct 15 12:34:25 AM UTC 24 |
| Finished | Oct 15 12:34:28 AM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250430921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4250430921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.892046225 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 116969635 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 12:34:33 AM UTC 24 |
| Finished | Oct 15 12:34:35 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892046225 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.892046225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.3312568591 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 52291376 ps |
| CPU time | 3.29 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:34:37 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312568591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3312568591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.1410328999 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 238622907 ps |
| CPU time | 7.49 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:34:41 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410328999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1410328999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.3573242722 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 293677684 ps |
| CPU time | 10.27 seconds |
| Started | Oct 15 12:34:33 AM UTC 24 |
| Finished | Oct 15 12:34:44 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573242722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3573242722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.2813704251 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 80482845 ps |
| CPU time | 3.44 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:34:37 AM UTC 24 |
| Peak memory | 230012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813704251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2813704251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.1988414630 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 589686321 ps |
| CPU time | 5.03 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:34:38 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988414630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1988414630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.555478974 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 92672511 ps |
| CPU time | 3.68 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:34:37 AM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555478974 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.555478974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.4192333433 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 89316815 ps |
| CPU time | 3.7 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:34:37 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192333433 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.4192333433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.822258717 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 463693303 ps |
| CPU time | 6.72 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:34:40 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822258717 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.822258717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.1396992875 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 69964181 ps |
| CPU time | 2.04 seconds |
| Started | Oct 15 12:34:33 AM UTC 24 |
| Finished | Oct 15 12:34:36 AM UTC 24 |
| Peak memory | 223864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396992875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1396992875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.24457382 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 103420418 ps |
| CPU time | 3.06 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:34:36 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24457382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.24457382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.448995487 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 8690106745 ps |
| CPU time | 74.07 seconds |
| Started | Oct 15 12:34:32 AM UTC 24 |
| Finished | Oct 15 12:35:48 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448995487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.448995487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.1382177591 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 368402414 ps |
| CPU time | 3.37 seconds |
| Started | Oct 15 12:34:33 AM UTC 24 |
| Finished | Oct 15 12:34:37 AM UTC 24 |
| Peak memory | 219920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382177591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1382177591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.2046728528 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 63704465 ps |
| CPU time | 1.43 seconds |
| Started | Oct 15 12:34:39 AM UTC 24 |
| Finished | Oct 15 12:34:41 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046728528 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2046728528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.3823196542 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 184447284 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 12:34:34 AM UTC 24 |
| Finished | Oct 15 12:34:38 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823196542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3823196542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.4067760954 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 88970518 ps |
| CPU time | 4.32 seconds |
| Started | Oct 15 12:34:37 AM UTC 24 |
| Finished | Oct 15 12:34:43 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067760954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4067760954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.2204997684 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 535971570 ps |
| CPU time | 3.6 seconds |
| Started | Oct 15 12:34:37 AM UTC 24 |
| Finished | Oct 15 12:34:42 AM UTC 24 |
| Peak memory | 223888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204997684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2204997684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.2714755215 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 273402130 ps |
| CPU time | 4.21 seconds |
| Started | Oct 15 12:34:34 AM UTC 24 |
| Finished | Oct 15 12:34:39 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714755215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2714755215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_random.3792562533 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 417361839 ps |
| CPU time | 4.83 seconds |
| Started | Oct 15 12:34:34 AM UTC 24 |
| Finished | Oct 15 12:34:40 AM UTC 24 |
| Peak memory | 223648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792562533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3792562533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.4276893341 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 721442862 ps |
| CPU time | 7.78 seconds |
| Started | Oct 15 12:34:33 AM UTC 24 |
| Finished | Oct 15 12:34:42 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276893341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.4276893341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.353267815 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 750575470 ps |
| CPU time | 6.95 seconds |
| Started | Oct 15 12:34:33 AM UTC 24 |
| Finished | Oct 15 12:34:41 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353267815 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.353267815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.1158022822 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 271581824 ps |
| CPU time | 6.54 seconds |
| Started | Oct 15 12:34:33 AM UTC 24 |
| Finished | Oct 15 12:34:41 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158022822 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1158022822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.146335550 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 278799731 ps |
| CPU time | 3.44 seconds |
| Started | Oct 15 12:34:34 AM UTC 24 |
| Finished | Oct 15 12:34:39 AM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146335550 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.146335550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.3367300289 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 90071189 ps |
| CPU time | 2.63 seconds |
| Started | Oct 15 12:34:37 AM UTC 24 |
| Finished | Oct 15 12:34:41 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367300289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3367300289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.3716553898 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 294263822 ps |
| CPU time | 2.85 seconds |
| Started | Oct 15 12:34:33 AM UTC 24 |
| Finished | Oct 15 12:34:37 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716553898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3716553898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.1691673296 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 93997944 ps |
| CPU time | 4.41 seconds |
| Started | Oct 15 12:34:37 AM UTC 24 |
| Finished | Oct 15 12:34:43 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691673296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1691673296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.3741191996 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 88421944 ps |
| CPU time | 2.48 seconds |
| Started | Oct 15 12:34:37 AM UTC 24 |
| Finished | Oct 15 12:34:41 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741191996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3741191996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.1350285237 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 11350547 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 12:34:43 AM UTC 24 |
| Finished | Oct 15 12:34:45 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350285237 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1350285237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.3835791672 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 406969152 ps |
| CPU time | 17.15 seconds |
| Started | Oct 15 12:34:40 AM UTC 24 |
| Finished | Oct 15 12:34:58 AM UTC 24 |
| Peak memory | 223944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835791672 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3835791672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.3071779014 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 344796316 ps |
| CPU time | 5.39 seconds |
| Started | Oct 15 12:34:41 AM UTC 24 |
| Finished | Oct 15 12:34:48 AM UTC 24 |
| Peak memory | 217548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071779014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3071779014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.2082627400 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 76914501 ps |
| CPU time | 2.79 seconds |
| Started | Oct 15 12:34:40 AM UTC 24 |
| Finished | Oct 15 12:34:44 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082627400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2082627400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.2852062990 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 750997033 ps |
| CPU time | 16.79 seconds |
| Started | Oct 15 12:34:41 AM UTC 24 |
| Finished | Oct 15 12:34:59 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852062990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2852062990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.3834744175 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 75029119 ps |
| CPU time | 4.64 seconds |
| Started | Oct 15 12:34:41 AM UTC 24 |
| Finished | Oct 15 12:34:47 AM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834744175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3834744175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.1060975224 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 62455938 ps |
| CPU time | 3.83 seconds |
| Started | Oct 15 12:34:41 AM UTC 24 |
| Finished | Oct 15 12:34:46 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060975224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1060975224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_random.3847751516 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 631197060 ps |
| CPU time | 6.99 seconds |
| Started | Oct 15 12:34:40 AM UTC 24 |
| Finished | Oct 15 12:34:48 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847751516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3847751516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.3900488478 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 52676959 ps |
| CPU time | 3.02 seconds |
| Started | Oct 15 12:34:39 AM UTC 24 |
| Finished | Oct 15 12:34:43 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900488478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3900488478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.4244179553 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 177930102 ps |
| CPU time | 3.91 seconds |
| Started | Oct 15 12:34:39 AM UTC 24 |
| Finished | Oct 15 12:34:44 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244179553 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.4244179553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.327826391 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 78670999 ps |
| CPU time | 3.55 seconds |
| Started | Oct 15 12:34:39 AM UTC 24 |
| Finished | Oct 15 12:34:43 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327826391 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.327826391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.2334842656 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 245362080 ps |
| CPU time | 1.74 seconds |
| Started | Oct 15 12:34:39 AM UTC 24 |
| Finished | Oct 15 12:34:42 AM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334842656 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2334842656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.791311303 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 337959634 ps |
| CPU time | 3.17 seconds |
| Started | Oct 15 12:34:43 AM UTC 24 |
| Finished | Oct 15 12:34:47 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791311303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.791311303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.2805541098 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 1202400212 ps |
| CPU time | 17.07 seconds |
| Started | Oct 15 12:34:39 AM UTC 24 |
| Finished | Oct 15 12:34:57 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805541098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2805541098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.409347188 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 1183746280 ps |
| CPU time | 16.24 seconds |
| Started | Oct 15 12:34:43 AM UTC 24 |
| Finished | Oct 15 12:35:00 AM UTC 24 |
| Peak memory | 231932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409347188 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.409347188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all_with_rand_reset.269104498 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 212048981 ps |
| CPU time | 12.71 seconds |
| Started | Oct 15 12:34:43 AM UTC 24 |
| Finished | Oct 15 12:34:57 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=269104498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr _stress_all_with_rand_reset.269104498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.3864716774 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2882509478 ps |
| CPU time | 34.9 seconds |
| Started | Oct 15 12:34:41 AM UTC 24 |
| Finished | Oct 15 12:35:17 AM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864716774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3864716774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.445894935 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 348011779 ps |
| CPU time | 3.97 seconds |
| Started | Oct 15 12:34:43 AM UTC 24 |
| Finished | Oct 15 12:34:48 AM UTC 24 |
| Peak memory | 217680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445894935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.445894935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.3363412219 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 33075567 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 12:30:06 AM UTC 24 |
| Finished | Oct 15 12:30:08 AM UTC 24 |
| Peak memory | 213424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363412219 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3363412219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.483372060 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 225805023 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 12:30:03 AM UTC 24 |
| Finished | Oct 15 12:30:07 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483372060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.483372060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.3199040103 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 288163811 ps |
| CPU time | 5.11 seconds |
| Started | Oct 15 12:30:03 AM UTC 24 |
| Finished | Oct 15 12:30:10 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199040103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3199040103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.2325571280 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 67597409 ps |
| CPU time | 4.7 seconds |
| Started | Oct 15 12:30:01 AM UTC 24 |
| Finished | Oct 15 12:30:07 AM UTC 24 |
| Peak memory | 219496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325571280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2325571280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_random.140236655 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 35608179 ps |
| CPU time | 3.33 seconds |
| Started | Oct 15 12:30:01 AM UTC 24 |
| Finished | Oct 15 12:30:05 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140236655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.140236655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.1061831549 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 993720935 ps |
| CPU time | 11.93 seconds |
| Started | Oct 15 12:30:06 AM UTC 24 |
| Finished | Oct 15 12:30:19 AM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061831549 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1061831549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.3558823797 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 31485088 ps |
| CPU time | 2.5 seconds |
| Started | Oct 15 12:30:01 AM UTC 24 |
| Finished | Oct 15 12:30:04 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558823797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3558823797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.2629150949 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 72993644 ps |
| CPU time | 2.62 seconds |
| Started | Oct 15 12:30:01 AM UTC 24 |
| Finished | Oct 15 12:30:04 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629150949 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2629150949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.4178209813 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 344712238 ps |
| CPU time | 3.02 seconds |
| Started | Oct 15 12:30:01 AM UTC 24 |
| Finished | Oct 15 12:30:05 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178209813 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4178209813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.113765478 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 523056590 ps |
| CPU time | 6.58 seconds |
| Started | Oct 15 12:30:01 AM UTC 24 |
| Finished | Oct 15 12:30:09 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113765478 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.113765478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.2875444874 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 383345476 ps |
| CPU time | 4.09 seconds |
| Started | Oct 15 12:30:05 AM UTC 24 |
| Finished | Oct 15 12:30:10 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875444874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2875444874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.3064809476 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 577813626 ps |
| CPU time | 2.97 seconds |
| Started | Oct 15 12:30:01 AM UTC 24 |
| Finished | Oct 15 12:30:05 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064809476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3064809476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.1890966556 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 111357738 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 12:30:06 AM UTC 24 |
| Finished | Oct 15 12:30:08 AM UTC 24 |
| Peak memory | 213300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890966556 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1890966556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.2555705322 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 410543485 ps |
| CPU time | 7.66 seconds |
| Started | Oct 15 12:30:02 AM UTC 24 |
| Finished | Oct 15 12:30:11 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555705322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2555705322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.407270897 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 38398346 ps |
| CPU time | 1.21 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:34:52 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407270897 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.407270897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.367533677 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 47567419 ps |
| CPU time | 2.33 seconds |
| Started | Oct 15 12:34:45 AM UTC 24 |
| Finished | Oct 15 12:34:48 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367533677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.367533677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.983343008 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 123005916 ps |
| CPU time | 5.92 seconds |
| Started | Oct 15 12:34:44 AM UTC 24 |
| Finished | Oct 15 12:34:52 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983343008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.983343008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.3401671381 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 104392336 ps |
| CPU time | 2.51 seconds |
| Started | Oct 15 12:34:45 AM UTC 24 |
| Finished | Oct 15 12:34:48 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401671381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3401671381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.874403773 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 230940801 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 12:34:45 AM UTC 24 |
| Finished | Oct 15 12:34:51 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874403773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.874403773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.1812468898 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 693782623 ps |
| CPU time | 3.71 seconds |
| Started | Oct 15 12:34:44 AM UTC 24 |
| Finished | Oct 15 12:34:50 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812468898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1812468898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_random.849455182 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 223623703 ps |
| CPU time | 6.6 seconds |
| Started | Oct 15 12:34:44 AM UTC 24 |
| Finished | Oct 15 12:34:52 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849455182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.849455182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.3859163852 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 64434986 ps |
| CPU time | 3.99 seconds |
| Started | Oct 15 12:34:43 AM UTC 24 |
| Finished | Oct 15 12:34:48 AM UTC 24 |
| Peak memory | 217616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859163852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3859163852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.2623330669 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 2316970018 ps |
| CPU time | 25.86 seconds |
| Started | Oct 15 12:34:43 AM UTC 24 |
| Finished | Oct 15 12:35:10 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623330669 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2623330669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.4278149638 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 904090154 ps |
| CPU time | 4.97 seconds |
| Started | Oct 15 12:34:43 AM UTC 24 |
| Finished | Oct 15 12:34:49 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278149638 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4278149638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.885656632 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 233015901 ps |
| CPU time | 2.77 seconds |
| Started | Oct 15 12:34:43 AM UTC 24 |
| Finished | Oct 15 12:34:47 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885656632 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.885656632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.4210171199 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 49395001 ps |
| CPU time | 3.37 seconds |
| Started | Oct 15 12:34:46 AM UTC 24 |
| Finished | Oct 15 12:34:50 AM UTC 24 |
| Peak memory | 228064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210171199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4210171199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.1356149490 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 169200863 ps |
| CPU time | 6.2 seconds |
| Started | Oct 15 12:34:43 AM UTC 24 |
| Finished | Oct 15 12:34:50 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356149490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1356149490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.579279627 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1262325697 ps |
| CPU time | 12.04 seconds |
| Started | Oct 15 12:34:47 AM UTC 24 |
| Finished | Oct 15 12:35:00 AM UTC 24 |
| Peak memory | 224692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579279627 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.579279627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all_with_rand_reset.1092240426 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2105295424 ps |
| CPU time | 21.44 seconds |
| Started | Oct 15 12:34:47 AM UTC 24 |
| Finished | Oct 15 12:35:10 AM UTC 24 |
| Peak memory | 230996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1092240426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymg r_stress_all_with_rand_reset.1092240426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.419032283 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 262061962 ps |
| CPU time | 4.04 seconds |
| Started | Oct 15 12:34:44 AM UTC 24 |
| Finished | Oct 15 12:34:50 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419032283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.419032283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.2042281783 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 52257525 ps |
| CPU time | 3.05 seconds |
| Started | Oct 15 12:34:46 AM UTC 24 |
| Finished | Oct 15 12:34:50 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042281783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2042281783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.3301119035 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 15724699 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 12:34:53 AM UTC 24 |
| Finished | Oct 15 12:34:55 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301119035 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3301119035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.2533804475 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1300339820 ps |
| CPU time | 35.08 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:35:27 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533804475 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2533804475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.3158055769 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 666787435 ps |
| CPU time | 6.51 seconds |
| Started | Oct 15 12:34:51 AM UTC 24 |
| Finished | Oct 15 12:34:59 AM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158055769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3158055769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.3813993611 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 72181827 ps |
| CPU time | 3.46 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:34:55 AM UTC 24 |
| Peak memory | 223684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813993611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3813993611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.286586463 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 648498461 ps |
| CPU time | 13.61 seconds |
| Started | Oct 15 12:34:51 AM UTC 24 |
| Finished | Oct 15 12:35:06 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286586463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.286586463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.3868168244 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 155621417 ps |
| CPU time | 4.85 seconds |
| Started | Oct 15 12:34:51 AM UTC 24 |
| Finished | Oct 15 12:34:58 AM UTC 24 |
| Peak memory | 223600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868168244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3868168244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_random.955806757 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 61416287 ps |
| CPU time | 4.08 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:34:55 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955806757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.955806757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.2500588875 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 41742006 ps |
| CPU time | 2.47 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:34:53 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500588875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2500588875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.41671979 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 739459817 ps |
| CPU time | 6.35 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:34:57 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41671979 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.41671979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.3822801655 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1493143588 ps |
| CPU time | 36.45 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:35:28 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822801655 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3822801655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.1185562183 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 518967035 ps |
| CPU time | 4.58 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:34:56 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185562183 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1185562183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.851181990 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2936010140 ps |
| CPU time | 18.82 seconds |
| Started | Oct 15 12:34:51 AM UTC 24 |
| Finished | Oct 15 12:35:12 AM UTC 24 |
| Peak memory | 223792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851181990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.851181990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.2114928352 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 335463302 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:34:54 AM UTC 24 |
| Peak memory | 217680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114928352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2114928352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all_with_rand_reset.638948 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 389985008 ps |
| CPU time | 7.5 seconds |
| Started | Oct 15 12:34:53 AM UTC 24 |
| Finished | Oct 15 12:35:01 AM UTC 24 |
| Peak memory | 227884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=638948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_st ress_all_with_rand_reset.638948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.904773430 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 83025388 ps |
| CPU time | 4.71 seconds |
| Started | Oct 15 12:34:50 AM UTC 24 |
| Finished | Oct 15 12:34:56 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904773430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.904773430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.2982021640 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 96553994 ps |
| CPU time | 2.27 seconds |
| Started | Oct 15 12:34:51 AM UTC 24 |
| Finished | Oct 15 12:34:55 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982021640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2982021640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.3093575724 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 40875061 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 12:34:59 AM UTC 24 |
| Finished | Oct 15 12:35:01 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093575724 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3093575724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.795017507 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 201903695 ps |
| CPU time | 3.91 seconds |
| Started | Oct 15 12:34:56 AM UTC 24 |
| Finished | Oct 15 12:35:01 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795017507 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.795017507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.2231928631 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 85318464 ps |
| CPU time | 4.17 seconds |
| Started | Oct 15 12:34:58 AM UTC 24 |
| Finished | Oct 15 12:35:03 AM UTC 24 |
| Peak memory | 218016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231928631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2231928631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.1425090560 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 384185712 ps |
| CPU time | 2.82 seconds |
| Started | Oct 15 12:34:56 AM UTC 24 |
| Finished | Oct 15 12:35:00 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425090560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1425090560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.1299905408 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 7535531909 ps |
| CPU time | 36.99 seconds |
| Started | Oct 15 12:34:58 AM UTC 24 |
| Finished | Oct 15 12:35:36 AM UTC 24 |
| Peak memory | 223800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299905408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1299905408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.977024319 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 172284812 ps |
| CPU time | 4.32 seconds |
| Started | Oct 15 12:34:58 AM UTC 24 |
| Finished | Oct 15 12:35:03 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977024319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.977024319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.3921126299 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 427849939 ps |
| CPU time | 6.5 seconds |
| Started | Oct 15 12:34:56 AM UTC 24 |
| Finished | Oct 15 12:35:04 AM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921126299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3921126299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_random.3628270411 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 93709750 ps |
| CPU time | 3.2 seconds |
| Started | Oct 15 12:34:56 AM UTC 24 |
| Finished | Oct 15 12:35:00 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628270411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3628270411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.3704003823 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 160707731 ps |
| CPU time | 2.49 seconds |
| Started | Oct 15 12:34:54 AM UTC 24 |
| Finished | Oct 15 12:34:58 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704003823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3704003823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.2235150963 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 83386247 ps |
| CPU time | 3.2 seconds |
| Started | Oct 15 12:34:55 AM UTC 24 |
| Finished | Oct 15 12:34:59 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235150963 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2235150963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.4050968710 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 26425949 ps |
| CPU time | 2.59 seconds |
| Started | Oct 15 12:34:55 AM UTC 24 |
| Finished | Oct 15 12:34:59 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050968710 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.4050968710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.1372851821 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 602509416 ps |
| CPU time | 14.22 seconds |
| Started | Oct 15 12:34:56 AM UTC 24 |
| Finished | Oct 15 12:35:12 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372851821 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1372851821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.4243416344 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 3897315084 ps |
| CPU time | 34.06 seconds |
| Started | Oct 15 12:34:58 AM UTC 24 |
| Finished | Oct 15 12:35:33 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243416344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4243416344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.801557698 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 116517035 ps |
| CPU time | 3.12 seconds |
| Started | Oct 15 12:34:54 AM UTC 24 |
| Finished | Oct 15 12:34:58 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801557698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.801557698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.940588352 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 3212193179 ps |
| CPU time | 20.81 seconds |
| Started | Oct 15 12:34:59 AM UTC 24 |
| Finished | Oct 15 12:35:21 AM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940588352 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.940588352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all_with_rand_reset.1137074129 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5464406140 ps |
| CPU time | 38.33 seconds |
| Started | Oct 15 12:34:59 AM UTC 24 |
| Finished | Oct 15 12:35:39 AM UTC 24 |
| Peak memory | 231892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1137074129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymg r_stress_all_with_rand_reset.1137074129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.2031517460 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 419304069 ps |
| CPU time | 5.13 seconds |
| Started | Oct 15 12:34:58 AM UTC 24 |
| Finished | Oct 15 12:35:04 AM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031517460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2031517460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.3720897676 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 97514580 ps |
| CPU time | 3.41 seconds |
| Started | Oct 15 12:34:58 AM UTC 24 |
| Finished | Oct 15 12:35:03 AM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720897676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3720897676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.2175429416 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 24041271 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 12:35:04 AM UTC 24 |
| Finished | Oct 15 12:35:07 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175429416 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2175429416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.1767500881 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 452676919 ps |
| CPU time | 5.2 seconds |
| Started | Oct 15 12:35:00 AM UTC 24 |
| Finished | Oct 15 12:35:07 AM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767500881 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1767500881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.524913453 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 1195933769 ps |
| CPU time | 3.63 seconds |
| Started | Oct 15 12:35:02 AM UTC 24 |
| Finished | Oct 15 12:35:06 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524913453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.524913453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.3739468616 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 25785460 ps |
| CPU time | 3.05 seconds |
| Started | Oct 15 12:35:02 AM UTC 24 |
| Finished | Oct 15 12:35:06 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739468616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3739468616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.2678175665 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1226240562 ps |
| CPU time | 5.01 seconds |
| Started | Oct 15 12:35:02 AM UTC 24 |
| Finished | Oct 15 12:35:08 AM UTC 24 |
| Peak memory | 231160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678175665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2678175665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.92277299 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 157502618 ps |
| CPU time | 8.82 seconds |
| Started | Oct 15 12:35:02 AM UTC 24 |
| Finished | Oct 15 12:35:11 AM UTC 24 |
| Peak memory | 231776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92277299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.92277299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_random.3432960234 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 1405690955 ps |
| CPU time | 10.27 seconds |
| Started | Oct 15 12:35:00 AM UTC 24 |
| Finished | Oct 15 12:35:12 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432960234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3432960234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.2462583255 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 148629248 ps |
| CPU time | 3.44 seconds |
| Started | Oct 15 12:34:59 AM UTC 24 |
| Finished | Oct 15 12:35:04 AM UTC 24 |
| Peak memory | 217684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462583255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2462583255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.2367227337 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 566616598 ps |
| CPU time | 5.01 seconds |
| Started | Oct 15 12:34:59 AM UTC 24 |
| Finished | Oct 15 12:35:05 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367227337 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2367227337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.2026937993 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 148532881 ps |
| CPU time | 4.26 seconds |
| Started | Oct 15 12:34:59 AM UTC 24 |
| Finished | Oct 15 12:35:05 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026937993 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2026937993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.3608699428 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 237785147 ps |
| CPU time | 4 seconds |
| Started | Oct 15 12:35:00 AM UTC 24 |
| Finished | Oct 15 12:35:06 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608699428 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3608699428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.3758369963 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 239558091 ps |
| CPU time | 3.73 seconds |
| Started | Oct 15 12:35:03 AM UTC 24 |
| Finished | Oct 15 12:35:08 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758369963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3758369963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.615314220 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 223003396 ps |
| CPU time | 3.04 seconds |
| Started | Oct 15 12:34:59 AM UTC 24 |
| Finished | Oct 15 12:35:03 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615314220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.615314220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all_with_rand_reset.515808486 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 1219439562 ps |
| CPU time | 21.8 seconds |
| Started | Oct 15 12:35:04 AM UTC 24 |
| Finished | Oct 15 12:35:28 AM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=515808486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr _stress_all_with_rand_reset.515808486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.3330574744 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 3892393545 ps |
| CPU time | 56.91 seconds |
| Started | Oct 15 12:35:02 AM UTC 24 |
| Finished | Oct 15 12:36:00 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330574744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3330574744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.2507768962 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 375247812 ps |
| CPU time | 3.81 seconds |
| Started | Oct 15 12:35:03 AM UTC 24 |
| Finished | Oct 15 12:35:08 AM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507768962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2507768962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.1394991698 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 34939990 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 12:35:12 AM UTC 24 |
| Finished | Oct 15 12:35:13 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394991698 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1394991698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.359376736 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 938454017 ps |
| CPU time | 12.19 seconds |
| Started | Oct 15 12:35:07 AM UTC 24 |
| Finished | Oct 15 12:35:20 AM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359376736 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.359376736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.456835020 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 381149724 ps |
| CPU time | 3.92 seconds |
| Started | Oct 15 12:35:09 AM UTC 24 |
| Finished | Oct 15 12:35:14 AM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456835020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.456835020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.504265373 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 47287133 ps |
| CPU time | 2.47 seconds |
| Started | Oct 15 12:35:08 AM UTC 24 |
| Finished | Oct 15 12:35:12 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504265373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.504265373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.3092662761 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 722108607 ps |
| CPU time | 4.87 seconds |
| Started | Oct 15 12:35:08 AM UTC 24 |
| Finished | Oct 15 12:35:14 AM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092662761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3092662761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.1692795262 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 77370644 ps |
| CPU time | 2.74 seconds |
| Started | Oct 15 12:35:08 AM UTC 24 |
| Finished | Oct 15 12:35:12 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692795262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1692795262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.698416144 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 222760063 ps |
| CPU time | 5.46 seconds |
| Started | Oct 15 12:35:08 AM UTC 24 |
| Finished | Oct 15 12:35:15 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698416144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.698416144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_random.3475402332 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 677862454 ps |
| CPU time | 6.95 seconds |
| Started | Oct 15 12:35:07 AM UTC 24 |
| Finished | Oct 15 12:35:15 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475402332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3475402332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.1146398840 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 71560487 ps |
| CPU time | 4.42 seconds |
| Started | Oct 15 12:35:05 AM UTC 24 |
| Finished | Oct 15 12:35:11 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146398840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1146398840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.2291748825 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 733963307 ps |
| CPU time | 21.22 seconds |
| Started | Oct 15 12:35:05 AM UTC 24 |
| Finished | Oct 15 12:35:28 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291748825 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2291748825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.520365571 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 3161639968 ps |
| CPU time | 45.2 seconds |
| Started | Oct 15 12:35:05 AM UTC 24 |
| Finished | Oct 15 12:35:52 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520365571 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.520365571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.1963517592 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 137368405 ps |
| CPU time | 3.74 seconds |
| Started | Oct 15 12:35:07 AM UTC 24 |
| Finished | Oct 15 12:35:12 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963517592 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1963517592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.79734337 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2592807191 ps |
| CPU time | 22.82 seconds |
| Started | Oct 15 12:35:09 AM UTC 24 |
| Finished | Oct 15 12:35:33 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79734337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.79734337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.183357768 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 435130400 ps |
| CPU time | 9.59 seconds |
| Started | Oct 15 12:35:04 AM UTC 24 |
| Finished | Oct 15 12:35:15 AM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183357768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.183357768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.1671331759 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1664604980 ps |
| CPU time | 9.98 seconds |
| Started | Oct 15 12:35:10 AM UTC 24 |
| Finished | Oct 15 12:35:21 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671331759 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1671331759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.1184844515 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 937745778 ps |
| CPU time | 7.19 seconds |
| Started | Oct 15 12:35:08 AM UTC 24 |
| Finished | Oct 15 12:35:16 AM UTC 24 |
| Peak memory | 228084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184844515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1184844515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.2046114166 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 52082725 ps |
| CPU time | 2.53 seconds |
| Started | Oct 15 12:35:09 AM UTC 24 |
| Finished | Oct 15 12:35:13 AM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046114166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2046114166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.1802795828 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 40486961 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:24 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802795828 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1802795828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.2240851563 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 37605730 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 12:35:13 AM UTC 24 |
| Finished | Oct 15 12:35:17 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240851563 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2240851563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.3087644921 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 342150085 ps |
| CPU time | 11.09 seconds |
| Started | Oct 15 12:35:21 AM UTC 24 |
| Finished | Oct 15 12:35:34 AM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087644921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3087644921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.84874586 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 302897999 ps |
| CPU time | 3.38 seconds |
| Started | Oct 15 12:35:13 AM UTC 24 |
| Finished | Oct 15 12:35:17 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84874586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.84874586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.185232747 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 80714037 ps |
| CPU time | 4.12 seconds |
| Started | Oct 15 12:35:20 AM UTC 24 |
| Finished | Oct 15 12:35:25 AM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185232747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.185232747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.800141497 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 325064667 ps |
| CPU time | 5.04 seconds |
| Started | Oct 15 12:35:21 AM UTC 24 |
| Finished | Oct 15 12:35:28 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800141497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.800141497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.3259848343 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 194579725 ps |
| CPU time | 6.06 seconds |
| Started | Oct 15 12:35:20 AM UTC 24 |
| Finished | Oct 15 12:35:27 AM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259848343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3259848343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_random.1313819380 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 427384320 ps |
| CPU time | 5.15 seconds |
| Started | Oct 15 12:35:13 AM UTC 24 |
| Finished | Oct 15 12:35:19 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313819380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1313819380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.3296199345 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 80748671 ps |
| CPU time | 3.46 seconds |
| Started | Oct 15 12:35:13 AM UTC 24 |
| Finished | Oct 15 12:35:17 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296199345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3296199345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.361218093 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 206062904 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 12:35:13 AM UTC 24 |
| Finished | Oct 15 12:35:18 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361218093 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.361218093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.3222827334 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 73841078 ps |
| CPU time | 2.81 seconds |
| Started | Oct 15 12:35:13 AM UTC 24 |
| Finished | Oct 15 12:35:17 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222827334 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3222827334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.3006500058 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 35789459 ps |
| CPU time | 2.74 seconds |
| Started | Oct 15 12:35:13 AM UTC 24 |
| Finished | Oct 15 12:35:17 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006500058 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3006500058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.3003739402 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 98104617 ps |
| CPU time | 2.58 seconds |
| Started | Oct 15 12:35:21 AM UTC 24 |
| Finished | Oct 15 12:35:25 AM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003739402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3003739402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.1397584291 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 59351642 ps |
| CPU time | 2.96 seconds |
| Started | Oct 15 12:35:12 AM UTC 24 |
| Finished | Oct 15 12:35:16 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397584291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1397584291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.2792683269 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 1243120915 ps |
| CPU time | 23.82 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:47 AM UTC 24 |
| Peak memory | 227336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792683269 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2792683269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all_with_rand_reset.1554230543 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 866633802 ps |
| CPU time | 17.91 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:41 AM UTC 24 |
| Peak memory | 230868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1554230543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymg r_stress_all_with_rand_reset.1554230543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.3834565670 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 111104793 ps |
| CPU time | 2.18 seconds |
| Started | Oct 15 12:35:20 AM UTC 24 |
| Finished | Oct 15 12:35:23 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834565670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3834565670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.3302759588 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 242993084 ps |
| CPU time | 3.48 seconds |
| Started | Oct 15 12:35:21 AM UTC 24 |
| Finished | Oct 15 12:35:26 AM UTC 24 |
| Peak memory | 219768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302759588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3302759588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.2550238050 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 57183963 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 12:35:26 AM UTC 24 |
| Finished | Oct 15 12:35:28 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550238050 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2550238050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.3594963918 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 209466381 ps |
| CPU time | 3.6 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:27 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594963918 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3594963918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.2478147686 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 59835348 ps |
| CPU time | 3.22 seconds |
| Started | Oct 15 12:35:23 AM UTC 24 |
| Finished | Oct 15 12:35:28 AM UTC 24 |
| Peak memory | 230968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478147686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2478147686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.4180385797 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 160249951 ps |
| CPU time | 2.67 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:26 AM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180385797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.4180385797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.1318040690 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 92274128 ps |
| CPU time | 5.62 seconds |
| Started | Oct 15 12:35:23 AM UTC 24 |
| Finished | Oct 15 12:35:30 AM UTC 24 |
| Peak memory | 223796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318040690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1318040690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.3576650504 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 673116245 ps |
| CPU time | 3.89 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:27 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576650504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3576650504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_random.2460087520 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 135876002 ps |
| CPU time | 1.79 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:25 AM UTC 24 |
| Peak memory | 214012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460087520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2460087520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.2579961941 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 599602175 ps |
| CPU time | 9.37 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:32 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579961941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2579961941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.3956710516 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 63398052 ps |
| CPU time | 2.26 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:25 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956710516 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3956710516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.856765622 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 164954362 ps |
| CPU time | 5.47 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:28 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856765622 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.856765622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.1263588765 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 107435275 ps |
| CPU time | 5.36 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:28 AM UTC 24 |
| Peak memory | 217236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263588765 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1263588765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.3361490646 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 118027139 ps |
| CPU time | 2.84 seconds |
| Started | Oct 15 12:35:24 AM UTC 24 |
| Finished | Oct 15 12:35:28 AM UTC 24 |
| Peak memory | 226000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361490646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3361490646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.1668089584 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 54551014 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:25 AM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668089584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1668089584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.1350004904 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1191393327 ps |
| CPU time | 8.5 seconds |
| Started | Oct 15 12:35:26 AM UTC 24 |
| Finished | Oct 15 12:35:35 AM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350004904 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1350004904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.1863275444 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 676534932 ps |
| CPU time | 4.32 seconds |
| Started | Oct 15 12:35:22 AM UTC 24 |
| Finished | Oct 15 12:35:28 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863275444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1863275444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.1093610251 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 559019403 ps |
| CPU time | 5.97 seconds |
| Started | Oct 15 12:35:25 AM UTC 24 |
| Finished | Oct 15 12:35:32 AM UTC 24 |
| Peak memory | 219704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093610251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1093610251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.1013368454 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 21484445 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 12:35:30 AM UTC 24 |
| Finished | Oct 15 12:35:32 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013368454 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1013368454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.459458092 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 161254525 ps |
| CPU time | 3.51 seconds |
| Started | Oct 15 12:35:27 AM UTC 24 |
| Finished | Oct 15 12:35:32 AM UTC 24 |
| Peak memory | 225812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459458092 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.459458092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.1620101028 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 721590796 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 12:35:29 AM UTC 24 |
| Finished | Oct 15 12:35:33 AM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620101028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1620101028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.962888202 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 719553281 ps |
| CPU time | 2.42 seconds |
| Started | Oct 15 12:35:29 AM UTC 24 |
| Finished | Oct 15 12:35:32 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962888202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.962888202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.2034923708 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 258323837 ps |
| CPU time | 5.51 seconds |
| Started | Oct 15 12:35:29 AM UTC 24 |
| Finished | Oct 15 12:35:35 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034923708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2034923708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.336043702 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 150355034 ps |
| CPU time | 3.41 seconds |
| Started | Oct 15 12:35:29 AM UTC 24 |
| Finished | Oct 15 12:35:33 AM UTC 24 |
| Peak memory | 223560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336043702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.336043702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.2041670397 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 213505211 ps |
| CPU time | 5.17 seconds |
| Started | Oct 15 12:35:29 AM UTC 24 |
| Finished | Oct 15 12:35:35 AM UTC 24 |
| Peak memory | 227964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041670397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2041670397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_random.3512572129 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 566006345 ps |
| CPU time | 7.17 seconds |
| Started | Oct 15 12:35:27 AM UTC 24 |
| Finished | Oct 15 12:35:36 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512572129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3512572129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.1594581332 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 56067887 ps |
| CPU time | 2.45 seconds |
| Started | Oct 15 12:35:26 AM UTC 24 |
| Finished | Oct 15 12:35:30 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594581332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1594581332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.1406105844 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 33306757 ps |
| CPU time | 2.34 seconds |
| Started | Oct 15 12:35:27 AM UTC 24 |
| Finished | Oct 15 12:35:31 AM UTC 24 |
| Peak memory | 215376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406105844 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1406105844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.1247534133 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 222758510 ps |
| CPU time | 3.67 seconds |
| Started | Oct 15 12:35:26 AM UTC 24 |
| Finished | Oct 15 12:35:31 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247534133 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1247534133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.758915728 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 42139307 ps |
| CPU time | 2.47 seconds |
| Started | Oct 15 12:35:27 AM UTC 24 |
| Finished | Oct 15 12:35:31 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758915728 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.758915728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.3752694898 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 490923725 ps |
| CPU time | 13.55 seconds |
| Started | Oct 15 12:35:29 AM UTC 24 |
| Finished | Oct 15 12:35:43 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752694898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3752694898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.3300013549 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 78527819 ps |
| CPU time | 2.9 seconds |
| Started | Oct 15 12:35:26 AM UTC 24 |
| Finished | Oct 15 12:35:30 AM UTC 24 |
| Peak memory | 217868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300013549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3300013549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.4145420868 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 30600557145 ps |
| CPU time | 502.73 seconds |
| Started | Oct 15 12:35:30 AM UTC 24 |
| Finished | Oct 15 12:43:59 AM UTC 24 |
| Peak memory | 231836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145420868 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.4145420868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.962736594 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 44310460 ps |
| CPU time | 3.61 seconds |
| Started | Oct 15 12:35:29 AM UTC 24 |
| Finished | Oct 15 12:35:33 AM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962736594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.962736594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.4088149122 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 64108385 ps |
| CPU time | 1.72 seconds |
| Started | Oct 15 12:35:29 AM UTC 24 |
| Finished | Oct 15 12:35:32 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088149122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.4088149122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.633137305 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 40783239 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 12:35:34 AM UTC 24 |
| Finished | Oct 15 12:35:37 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633137305 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.633137305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.15392138 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 280086624 ps |
| CPU time | 3.13 seconds |
| Started | Oct 15 12:35:33 AM UTC 24 |
| Finished | Oct 15 12:35:37 AM UTC 24 |
| Peak memory | 218144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15392138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.15392138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.698673550 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 41108180 ps |
| CPU time | 2.2 seconds |
| Started | Oct 15 12:35:32 AM UTC 24 |
| Finished | Oct 15 12:35:35 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698673550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.698673550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.3996065999 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 114304171 ps |
| CPU time | 3.27 seconds |
| Started | Oct 15 12:35:33 AM UTC 24 |
| Finished | Oct 15 12:35:37 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996065999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3996065999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.875206014 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 94245823 ps |
| CPU time | 2.01 seconds |
| Started | Oct 15 12:35:33 AM UTC 24 |
| Finished | Oct 15 12:35:36 AM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875206014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.875206014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.1043296529 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 282683760 ps |
| CPU time | 3.22 seconds |
| Started | Oct 15 12:35:32 AM UTC 24 |
| Finished | Oct 15 12:35:36 AM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043296529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1043296529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_random.1547928541 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 372491176 ps |
| CPU time | 9.1 seconds |
| Started | Oct 15 12:35:32 AM UTC 24 |
| Finished | Oct 15 12:35:42 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547928541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1547928541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.1537067267 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 99500991 ps |
| CPU time | 2.59 seconds |
| Started | Oct 15 12:35:30 AM UTC 24 |
| Finished | Oct 15 12:35:34 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537067267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1537067267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.23252680 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 433782610 ps |
| CPU time | 3.01 seconds |
| Started | Oct 15 12:35:30 AM UTC 24 |
| Finished | Oct 15 12:35:34 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23252680 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.23252680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.2384573447 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 924505282 ps |
| CPU time | 23.08 seconds |
| Started | Oct 15 12:35:30 AM UTC 24 |
| Finished | Oct 15 12:35:55 AM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384573447 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2384573447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.3647362940 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 503574233 ps |
| CPU time | 5.87 seconds |
| Started | Oct 15 12:35:32 AM UTC 24 |
| Finished | Oct 15 12:35:38 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647362940 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3647362940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.449785145 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 161881723 ps |
| CPU time | 2.75 seconds |
| Started | Oct 15 12:35:33 AM UTC 24 |
| Finished | Oct 15 12:35:37 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449785145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.449785145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.528704438 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 544656697 ps |
| CPU time | 3.28 seconds |
| Started | Oct 15 12:35:30 AM UTC 24 |
| Finished | Oct 15 12:35:35 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528704438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.528704438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.747124100 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 3260526397 ps |
| CPU time | 32.9 seconds |
| Started | Oct 15 12:35:34 AM UTC 24 |
| Finished | Oct 15 12:36:08 AM UTC 24 |
| Peak memory | 231760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747124100 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.747124100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.299369157 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 234284580 ps |
| CPU time | 13.32 seconds |
| Started | Oct 15 12:35:34 AM UTC 24 |
| Finished | Oct 15 12:35:49 AM UTC 24 |
| Peak memory | 232032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=299369157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr _stress_all_with_rand_reset.299369157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.751959461 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 319658286 ps |
| CPU time | 4.68 seconds |
| Started | Oct 15 12:35:33 AM UTC 24 |
| Finished | Oct 15 12:35:39 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751959461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.751959461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.618426522 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 76929707 ps |
| CPU time | 2.1 seconds |
| Started | Oct 15 12:35:33 AM UTC 24 |
| Finished | Oct 15 12:35:36 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618426522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.618426522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.15051045 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 19542879 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:43 AM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15051045 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.15051045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.3753595431 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 57027124 ps |
| CPU time | 3.74 seconds |
| Started | Oct 15 12:35:40 AM UTC 24 |
| Finished | Oct 15 12:35:45 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753595431 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3753595431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.211100213 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 205203144 ps |
| CPU time | 3.72 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:45 AM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211100213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.211100213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.3497568055 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 127449293 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 12:35:40 AM UTC 24 |
| Finished | Oct 15 12:35:44 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497568055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3497568055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.1648495001 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 179492373 ps |
| CPU time | 3.15 seconds |
| Started | Oct 15 12:35:40 AM UTC 24 |
| Finished | Oct 15 12:35:45 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648495001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1648495001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.985758093 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 209374847 ps |
| CPU time | 7.21 seconds |
| Started | Oct 15 12:35:40 AM UTC 24 |
| Finished | Oct 15 12:35:49 AM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985758093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.985758093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_random.3749595053 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 164817613 ps |
| CPU time | 3.62 seconds |
| Started | Oct 15 12:35:40 AM UTC 24 |
| Finished | Oct 15 12:35:45 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749595053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3749595053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.3149569865 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 273810190 ps |
| CPU time | 4.91 seconds |
| Started | Oct 15 12:35:34 AM UTC 24 |
| Finished | Oct 15 12:35:40 AM UTC 24 |
| Peak memory | 215560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149569865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3149569865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.4105031371 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 1418681808 ps |
| CPU time | 5.62 seconds |
| Started | Oct 15 12:35:35 AM UTC 24 |
| Finished | Oct 15 12:35:41 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105031371 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4105031371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.3974214531 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 414146257 ps |
| CPU time | 6.49 seconds |
| Started | Oct 15 12:35:35 AM UTC 24 |
| Finished | Oct 15 12:35:42 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974214531 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3974214531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.1177870043 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 399966579 ps |
| CPU time | 4.6 seconds |
| Started | Oct 15 12:35:40 AM UTC 24 |
| Finished | Oct 15 12:35:46 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177870043 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1177870043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.1334019659 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 629760341 ps |
| CPU time | 4.33 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:46 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334019659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1334019659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.1876325687 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 158436478 ps |
| CPU time | 3.73 seconds |
| Started | Oct 15 12:35:34 AM UTC 24 |
| Finished | Oct 15 12:35:39 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876325687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1876325687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.2423397926 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 2088994097 ps |
| CPU time | 56.33 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:36:39 AM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423397926 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2423397926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.4038360818 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 406373166 ps |
| CPU time | 4.39 seconds |
| Started | Oct 15 12:35:40 AM UTC 24 |
| Finished | Oct 15 12:35:46 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038360818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4038360818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.2725225840 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 62664486 ps |
| CPU time | 3 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:45 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725225840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2725225840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.2463748831 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 64051553 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 12:30:13 AM UTC 24 |
| Finished | Oct 15 12:30:16 AM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463748831 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2463748831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.3533077166 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 101745061 ps |
| CPU time | 4.02 seconds |
| Started | Oct 15 12:30:08 AM UTC 24 |
| Finished | Oct 15 12:30:13 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533077166 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3533077166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.4142612010 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 69507896 ps |
| CPU time | 3.77 seconds |
| Started | Oct 15 12:30:12 AM UTC 24 |
| Finished | Oct 15 12:30:17 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142612010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.4142612010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.1365390336 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 81178842 ps |
| CPU time | 2.61 seconds |
| Started | Oct 15 12:30:10 AM UTC 24 |
| Finished | Oct 15 12:30:13 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365390336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1365390336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.335727725 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 540659203 ps |
| CPU time | 4.51 seconds |
| Started | Oct 15 12:30:10 AM UTC 24 |
| Finished | Oct 15 12:30:15 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335727725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.335727725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.3496668993 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2762168994 ps |
| CPU time | 30.06 seconds |
| Started | Oct 15 12:30:07 AM UTC 24 |
| Finished | Oct 15 12:30:39 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496668993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3496668993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.1010987036 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 42937703 ps |
| CPU time | 3.15 seconds |
| Started | Oct 15 12:30:07 AM UTC 24 |
| Finished | Oct 15 12:30:11 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010987036 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1010987036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.2668661558 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 226148079 ps |
| CPU time | 7.68 seconds |
| Started | Oct 15 12:30:08 AM UTC 24 |
| Finished | Oct 15 12:30:17 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668661558 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2668661558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.3962551485 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 72889541 ps |
| CPU time | 3.87 seconds |
| Started | Oct 15 12:30:12 AM UTC 24 |
| Finished | Oct 15 12:30:17 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962551485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3962551485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.2161103344 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 25842249 ps |
| CPU time | 2.82 seconds |
| Started | Oct 15 12:30:07 AM UTC 24 |
| Finished | Oct 15 12:30:11 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161103344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2161103344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.531534117 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1543224914 ps |
| CPU time | 14.2 seconds |
| Started | Oct 15 12:30:11 AM UTC 24 |
| Finished | Oct 15 12:30:26 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531534117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.531534117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.204350091 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 141296261 ps |
| CPU time | 6.74 seconds |
| Started | Oct 15 12:30:12 AM UTC 24 |
| Finished | Oct 15 12:30:20 AM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204350091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.204350091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.3497725034 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 203724670 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 12:30:22 AM UTC 24 |
| Finished | Oct 15 12:30:24 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497725034 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3497725034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.359814111 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4467906583 ps |
| CPU time | 49.25 seconds |
| Started | Oct 15 12:30:17 AM UTC 24 |
| Finished | Oct 15 12:31:08 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359814111 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.359814111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.3251644719 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1601981098 ps |
| CPU time | 6.41 seconds |
| Started | Oct 15 12:30:20 AM UTC 24 |
| Finished | Oct 15 12:30:28 AM UTC 24 |
| Peak memory | 220036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251644719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3251644719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.2036489634 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 527902184 ps |
| CPU time | 3.2 seconds |
| Started | Oct 15 12:30:18 AM UTC 24 |
| Finished | Oct 15 12:30:22 AM UTC 24 |
| Peak memory | 215600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036489634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2036489634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.2150114967 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 32546565 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 12:30:19 AM UTC 24 |
| Finished | Oct 15 12:30:24 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150114967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2150114967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.1458892160 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 50805873 ps |
| CPU time | 4.06 seconds |
| Started | Oct 15 12:30:20 AM UTC 24 |
| Finished | Oct 15 12:30:25 AM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458892160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1458892160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.1961168859 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 78817073 ps |
| CPU time | 3.6 seconds |
| Started | Oct 15 12:30:18 AM UTC 24 |
| Finished | Oct 15 12:30:23 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961168859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1961168859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_random.1516172188 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 110560309 ps |
| CPU time | 7.29 seconds |
| Started | Oct 15 12:30:16 AM UTC 24 |
| Finished | Oct 15 12:30:24 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516172188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1516172188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.3463960904 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1028855813 ps |
| CPU time | 4.55 seconds |
| Started | Oct 15 12:30:14 AM UTC 24 |
| Finished | Oct 15 12:30:20 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463960904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3463960904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.209124542 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 197364223 ps |
| CPU time | 3.04 seconds |
| Started | Oct 15 12:30:16 AM UTC 24 |
| Finished | Oct 15 12:30:20 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209124542 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.209124542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.1853020016 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 268486296 ps |
| CPU time | 5.12 seconds |
| Started | Oct 15 12:30:15 AM UTC 24 |
| Finished | Oct 15 12:30:21 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853020016 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1853020016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.3140172080 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 36845066 ps |
| CPU time | 2.92 seconds |
| Started | Oct 15 12:30:16 AM UTC 24 |
| Finished | Oct 15 12:30:20 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140172080 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3140172080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.1491194563 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 128012523 ps |
| CPU time | 2.31 seconds |
| Started | Oct 15 12:30:20 AM UTC 24 |
| Finished | Oct 15 12:30:24 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491194563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1491194563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.1095581688 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 201269557 ps |
| CPU time | 3.55 seconds |
| Started | Oct 15 12:30:14 AM UTC 24 |
| Finished | Oct 15 12:30:19 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095581688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1095581688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.1047329406 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2461882406 ps |
| CPU time | 21.69 seconds |
| Started | Oct 15 12:30:18 AM UTC 24 |
| Finished | Oct 15 12:30:41 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047329406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1047329406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.3686280730 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 53365532 ps |
| CPU time | 2.45 seconds |
| Started | Oct 15 12:30:20 AM UTC 24 |
| Finished | Oct 15 12:30:24 AM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686280730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3686280730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.4169712791 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 12715767 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 12:30:33 AM UTC 24 |
| Finished | Oct 15 12:30:36 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169712791 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4169712791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.1745796790 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 52187551 ps |
| CPU time | 5.41 seconds |
| Started | Oct 15 12:30:25 AM UTC 24 |
| Finished | Oct 15 12:30:32 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745796790 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1745796790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.120234405 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 90649010 ps |
| CPU time | 3.08 seconds |
| Started | Oct 15 12:30:25 AM UTC 24 |
| Finished | Oct 15 12:30:30 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120234405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.120234405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.1095612133 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 86202254 ps |
| CPU time | 4.35 seconds |
| Started | Oct 15 12:30:28 AM UTC 24 |
| Finished | Oct 15 12:30:33 AM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095612133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1095612133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.3413028064 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 352832127 ps |
| CPU time | 4.11 seconds |
| Started | Oct 15 12:30:25 AM UTC 24 |
| Finished | Oct 15 12:30:31 AM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413028064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3413028064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_random.4140412581 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 121938968 ps |
| CPU time | 2.8 seconds |
| Started | Oct 15 12:30:25 AM UTC 24 |
| Finished | Oct 15 12:30:30 AM UTC 24 |
| Peak memory | 227708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140412581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4140412581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.2088278634 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 498500224 ps |
| CPU time | 4.41 seconds |
| Started | Oct 15 12:30:23 AM UTC 24 |
| Finished | Oct 15 12:30:28 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088278634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2088278634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.3516387126 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 241226128 ps |
| CPU time | 9.43 seconds |
| Started | Oct 15 12:30:24 AM UTC 24 |
| Finished | Oct 15 12:30:35 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516387126 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3516387126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.1721073703 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 310552380 ps |
| CPU time | 7.76 seconds |
| Started | Oct 15 12:30:23 AM UTC 24 |
| Finished | Oct 15 12:30:32 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721073703 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1721073703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.1787071369 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3792300422 ps |
| CPU time | 17.03 seconds |
| Started | Oct 15 12:30:25 AM UTC 24 |
| Finished | Oct 15 12:30:44 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787071369 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1787071369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.801126200 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 261836476 ps |
| CPU time | 3.08 seconds |
| Started | Oct 15 12:30:33 AM UTC 24 |
| Finished | Oct 15 12:30:37 AM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801126200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.801126200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.2309068640 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 92844845 ps |
| CPU time | 3.55 seconds |
| Started | Oct 15 12:30:22 AM UTC 24 |
| Finished | Oct 15 12:30:26 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309068640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2309068640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.2110114136 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 251631703 ps |
| CPU time | 7.07 seconds |
| Started | Oct 15 12:30:27 AM UTC 24 |
| Finished | Oct 15 12:30:35 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110114136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2110114136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.3168642747 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 119730384 ps |
| CPU time | 1.93 seconds |
| Started | Oct 15 12:30:33 AM UTC 24 |
| Finished | Oct 15 12:30:36 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168642747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3168642747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.3416811063 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 25505561 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:50 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416811063 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3416811063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.3958396857 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 114239423 ps |
| CPU time | 4.27 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:52 AM UTC 24 |
| Peak memory | 229952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958396857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3958396857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.3562023937 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 56211174 ps |
| CPU time | 2.92 seconds |
| Started | Oct 15 12:30:36 AM UTC 24 |
| Finished | Oct 15 12:30:40 AM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562023937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3562023937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.2019787136 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 44359437 ps |
| CPU time | 3.02 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:51 AM UTC 24 |
| Peak memory | 215376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019787136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2019787136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.2730077110 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 92885126 ps |
| CPU time | 3.13 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:51 AM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730077110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2730077110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.1905341676 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 90982157 ps |
| CPU time | 4.96 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:53 AM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905341676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1905341676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_random.1889448421 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 353943168 ps |
| CPU time | 3.19 seconds |
| Started | Oct 15 12:30:36 AM UTC 24 |
| Finished | Oct 15 12:30:40 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889448421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1889448421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.3128049481 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 157212032 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 12:30:34 AM UTC 24 |
| Finished | Oct 15 12:30:38 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128049481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3128049481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.1491242975 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 76475787 ps |
| CPU time | 4.17 seconds |
| Started | Oct 15 12:30:35 AM UTC 24 |
| Finished | Oct 15 12:30:40 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491242975 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1491242975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.898706487 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 438229548 ps |
| CPU time | 5.62 seconds |
| Started | Oct 15 12:30:34 AM UTC 24 |
| Finished | Oct 15 12:30:40 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898706487 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.898706487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.2260605660 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 212711437 ps |
| CPU time | 7.78 seconds |
| Started | Oct 15 12:30:35 AM UTC 24 |
| Finished | Oct 15 12:30:44 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260605660 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2260605660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.3548210049 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 241927520 ps |
| CPU time | 3.9 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:52 AM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548210049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3548210049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.1465408603 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 106265220 ps |
| CPU time | 3.41 seconds |
| Started | Oct 15 12:30:33 AM UTC 24 |
| Finished | Oct 15 12:30:38 AM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465408603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1465408603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.2077864735 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1138733311 ps |
| CPU time | 24.94 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:31:13 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077864735 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2077864735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.631408157 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 332328569 ps |
| CPU time | 5.83 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:54 AM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631408157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.631408157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.158105203 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 38226876 ps |
| CPU time | 3.12 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:51 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158105203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.158105203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.3840324171 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 70000012 ps |
| CPU time | 1.54 seconds |
| Started | Oct 15 12:30:57 AM UTC 24 |
| Finished | Oct 15 12:30:59 AM UTC 24 |
| Peak memory | 213416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840324171 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3840324171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.3334614642 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 149112529 ps |
| CPU time | 3.74 seconds |
| Started | Oct 15 12:30:55 AM UTC 24 |
| Finished | Oct 15 12:31:00 AM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334614642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3334614642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.4028605338 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 98697961 ps |
| CPU time | 3.24 seconds |
| Started | Oct 15 12:30:48 AM UTC 24 |
| Finished | Oct 15 12:30:52 AM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028605338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4028605338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.332525877 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 160954245 ps |
| CPU time | 6.68 seconds |
| Started | Oct 15 12:30:55 AM UTC 24 |
| Finished | Oct 15 12:31:03 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332525877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.332525877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.1512145408 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 478524085 ps |
| CPU time | 4.72 seconds |
| Started | Oct 15 12:30:55 AM UTC 24 |
| Finished | Oct 15 12:31:01 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512145408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1512145408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_random.17949560 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 220326530 ps |
| CPU time | 4.7 seconds |
| Started | Oct 15 12:30:48 AM UTC 24 |
| Finished | Oct 15 12:30:53 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17949560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.17949560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.3593284408 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 272464648 ps |
| CPU time | 3.95 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:52 AM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593284408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3593284408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.3492801205 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 71565658 ps |
| CPU time | 2.64 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:51 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492801205 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3492801205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.4153818035 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 79831269 ps |
| CPU time | 3.67 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:52 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153818035 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.4153818035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.2255839133 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 114753723 ps |
| CPU time | 3.73 seconds |
| Started | Oct 15 12:30:48 AM UTC 24 |
| Finished | Oct 15 12:30:52 AM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255839133 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2255839133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.3965721051 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1146846966 ps |
| CPU time | 24.49 seconds |
| Started | Oct 15 12:30:55 AM UTC 24 |
| Finished | Oct 15 12:31:21 AM UTC 24 |
| Peak memory | 227960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965721051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3965721051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.2962016328 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 97272139 ps |
| CPU time | 2.98 seconds |
| Started | Oct 15 12:30:47 AM UTC 24 |
| Finished | Oct 15 12:30:51 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962016328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2962016328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.2173116181 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 25599561955 ps |
| CPU time | 199.77 seconds |
| Started | Oct 15 12:30:56 AM UTC 24 |
| Finished | Oct 15 12:34:19 AM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173116181 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2173116181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.1377269069 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 563411673 ps |
| CPU time | 3.8 seconds |
| Started | Oct 15 12:30:55 AM UTC 24 |
| Finished | Oct 15 12:31:00 AM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377269069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1377269069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.40327302 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 147559818 ps |
| CPU time | 3.21 seconds |
| Started | Oct 15 12:30:55 AM UTC 24 |
| Finished | Oct 15 12:31:00 AM UTC 24 |
| Peak memory | 219696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40327302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.40327302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest |
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