KMAC/MASKED Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.380m	6.821ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	30.323us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.320s	33.690us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.100s	3.691ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.680s	1.106ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.200s	257.768us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.320s	33.690us	20	20	100.00
		kmac_csr_aliasing	11.680s	1.106ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	22.655us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	20.782us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.273m	524.203ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.714m	59.950ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	40.870m	374.184ms	50	50	100.00
		kmac_test_vectors_sha3_256	44.187m	1.303s	50	50	100.00
		kmac_test_vectors_sha3_384	34.594m	996.473ms	50	50	100.00
		kmac_test_vectors_sha3_512	24.850m	548.808ms	50	50	100.00
		kmac_test_vectors_shake_128	1.845h	1.027s	50	50	100.00
		kmac_test_vectors_shake_256	1.785h	2.746s	49	50	98.00
		kmac_test_vectors_kmac	6.990s	1.082ms	49	50	98.00
		kmac_test_vectors_kmac_xof	7.370s	652.183us	50	50	100.00
V2	sideload	kmac_sideload	9.231m	16.264ms	49	50	98.00
V2	app	kmac_app	6.893m	18.330ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.906m	51.657ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.692m	73.989ms	47	50	94.00
V2	error	kmac_error	8.416m	59.179ms	49	50	98.00
V2	key_error	kmac_key_error	9.090s	7.679ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.070s	571.607us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	52.610s	8.546ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.147m	25.404ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.810s	941.581us	50	50	100.00
V2	stress_all	kmac_stress_all	46.198m	94.312ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.880s	32.330us	50	50	100.00
V2	alert_test	kmac_alert_test	0.950s	68.276us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.380s	467.136us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.380s	467.136us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	30.323us	5	5	100.00
		kmac_csr_rw	1.320s	33.690us	20	20	100.00
		kmac_csr_aliasing	11.680s	1.106ms	5	5	100.00
		kmac_same_csr_outstanding	3.030s	130.730us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	30.323us	5	5	100.00
		kmac_csr_rw	1.320s	33.690us	20	20	100.00
		kmac_csr_aliasing	11.680s	1.106ms	5	5	100.00
		kmac_same_csr_outstanding	3.030s	130.730us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.970s	338.717us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.970s	338.717us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.970s	338.717us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.970s	338.717us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.500s	1.006ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.297m	13.661ms	5	5	100.00
		kmac_tl_intg_err	6.590s	2.602ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.590s	2.602ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.810s	941.581us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.380m	6.821ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.231m	16.264ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.970s	338.717us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.297m	13.661ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.297m	13.661ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.297m	13.661ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.380m	6.821ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.810s	941.581us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.297m	13.661ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.209m	5.591ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.380m	6.821ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	57.469m	486.274ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1275	1290	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	98.40	93.36	99.93	95.45	96.03	98.87	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:

Test kmac_stress_all_with_rand_reset has 5 failures.

5.kmac_stress_all_with_rand_reset.2861428206
Line 541, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17378013491 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 17378013491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_stress_all_with_rand_reset.1204244016
Line 1017, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 35608768579 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 35608768579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 3 failures.

20.kmac_entropy_refresh.186681835
Line 299, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 7196275259 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (176 [0xb0] vs 229 [0xe5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7196275259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.kmac_entropy_refresh.3737798011
Line 319, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 7922997959 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (79 [0x4f] vs 121 [0x79]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7922997959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test kmac_sideload has 1 failures.

22.kmac_sideload.279033546
Line 367, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_sideload/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_burst_write has 2 failures.

40.kmac_burst_write.2849647860
Line 347, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.kmac_burst_write.2010602266
Line 333, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 6.kmac_stress_all_with_rand_reset.3157206385
    Line 992, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 32836513252 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 32836513252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 21.kmac_error.2313538243
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_error/latest/run.log
```
  UVM_FATAL @ 10624324967 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10624324967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

Test kmac_test_vectors_kmac has 1 failures.

27.kmac_test_vectors_kmac.2407053007
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  57196764 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  57196764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_256 has 1 failures.

34.kmac_test_vectors_shake_256.3833520996
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  73750659 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  73750659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---