KMAC/MASKED Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.194m	14.992ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.480s	28.701us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.440s	28.898us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.500s	1.537ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.090s	1.049ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.960s	81.985us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.440s	28.898us	20	20	100.00
		kmac_csr_aliasing	10.090s	1.049ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.120s	10.469us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.800s	45.924us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.333h	88.097ms	48	50	96.00
V2	burst_write	kmac_burst_write	31.013m	362.559ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.035h	198.916ms	49	50	98.00
		kmac_test_vectors_sha3_256	57.017m	369.378ms	50	50	100.00
		kmac_test_vectors_sha3_384	45.395m	142.789ms	49	50	98.00
		kmac_test_vectors_sha3_512	33.987m	402.934ms	50	50	100.00
		kmac_test_vectors_shake_128	2.765h	517.118ms	49	50	98.00
		kmac_test_vectors_shake_256	2.499h	919.652ms	50	50	100.00
		kmac_test_vectors_kmac	10.060s	663.343us	50	50	100.00
		kmac_test_vectors_kmac_xof	22.880s	2.253ms	50	50	100.00
V2	sideload	kmac_sideload	10.697m	21.160ms	50	50	100.00
V2	app	kmac_app	8.868m	75.498ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.628m	11.989ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.581m	59.612ms	49	50	98.00
V2	error	kmac_error	10.742m	17.529ms	50	50	100.00
V2	key_error	kmac_key_error	32.780s	15.876ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	59.960s	1.893ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	25.120s	460.628us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	2.085m	8.301ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	46.500s	2.429ms	50	50	100.00
V2	stress_all	kmac_stress_all	57.653m	616.675ms	48	50	96.00
V2	intr_test	kmac_intr_test	1.190s	41.168us	50	50	100.00
V2	alert_test	kmac_alert_test	1.450s	29.603us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.330s	189.877us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.330s	189.877us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.480s	28.701us	5	5	100.00
		kmac_csr_rw	1.440s	28.898us	20	20	100.00
		kmac_csr_aliasing	10.090s	1.049ms	5	5	100.00
		kmac_same_csr_outstanding	3.100s	116.176us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.480s	28.701us	5	5	100.00
		kmac_csr_rw	1.440s	28.898us	20	20	100.00
		kmac_csr_aliasing	10.090s	1.049ms	5	5	100.00
		kmac_same_csr_outstanding	3.100s	116.176us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.830s	97.762us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.830s	97.762us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.830s	97.762us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.830s	97.762us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.090s	523.556us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.851m	30.862ms	5	5	100.00
		kmac_tl_intg_err	4.660s	380.204us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.660s	380.204us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	46.500s	2.429ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.194m	14.992ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.697m	21.160ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.830s	97.762us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.851m	30.862ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.851m	30.862ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.851m	30.862ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.194m	14.992ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	46.500s	2.429ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.851m	30.862ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.242m	6.066ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.194m	14.992ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.760h	572.977ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1233	1250	98.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.15	97.91	92.65	99.89	76.06	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.1949743557313965422024189429397306798500702011915049568954255567371955035596
    Line 432, in log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16488430107 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16488430107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.1775430901157393275492967348665369809535987425804897510788431926505110387859
    Line 476, in log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20042178608 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20042178608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 0.kmac_test_vectors_sha3_224.13981790572365560628163026156030903660408543570105209805679540399024443517142
    Line 66, in log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  34985557 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  34985557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 7.kmac_stress_all.30565709979321083650610108550950891344122815566306742003394022638561703230021
    Line 69, in log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 149419604 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 149419604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 45.kmac_test_vectors_sha3_384.88286156878128002332129997373039188024965137202856521371115158606322315108382
    Line 66, in log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  28062493 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  28062493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 3 failures:
- Test kmac_long_msg_and_output has 2 failures.
  - 8.kmac_long_msg_and_output.14707101582312155624259764727093565171512042915658624982469156985267490428401
    Log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest/run.log
```
  Job timed out after 90 minutes
```
  - 46.kmac_long_msg_and_output.23094994884445447656546878086930490951221066911397838235929787417157189927847
    Log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest/run.log
```
  Job timed out after 90 minutes
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 37.kmac_test_vectors_shake_128.113982304364129548591375118735102111324771288378840546572169904935250603393490
    Log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_shake_128/latest/run.log
```
  Job timed out after 180 minutes
```

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 1 failures.

13.kmac_entropy_refresh.107281689860462164324553029891967652052881954336417946669954779514369827012533
Line 390, in log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 31104961871 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (61 [0x3d] vs 89 [0x59]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 31104961871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

18.kmac_stress_all.46910863367673115578842657949188683329566429886716937873865588318381819557608
Line 1404, in log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log

  UVM_FATAL @ 10013707100 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (35 [0x23] vs 125 [0x7d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10013707100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

24.kmac_app.62912487396819665021304029174481671935868131536998566767612766830995822631977
Line 180, in log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_app/latest/run.log

  UVM_FATAL @ 2977595237 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (204 [0xcc] vs 172 [0xac]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2977595237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 7.kmac_stress_all_with_rand_reset.64293200777381632173235284651609230713251721969804801442434600175338508702335
    Line 1508, in log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21787788600 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 21787788600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.kmac_stress_all_with_rand_reset.62826585653075819485381165651273813228224461328970082884086776458037075518576
    Line 822, in log /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 72141026555 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 72141026555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```