KMAC/MASKED Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: `877a77116`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.454m	4.245ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.240s	39.880us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	27.193us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.470s	1.080ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.700s	439.606us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.040s	53.817us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	27.193us	20	20	100.00
		kmac_csr_aliasing	10.700s	439.606us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	12.973us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	277.903us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	54.881m	118.534ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.171m	15.664ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.858m	650.689ms	50	50	100.00
		kmac_test_vectors_sha3_256	41.736m	1.329s	50	50	100.00
		kmac_test_vectors_sha3_384	33.087m	782.638ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.417m	116.822ms	50	50	100.00
		kmac_test_vectors_shake_128	1.881h	1.714s	49	50	98.00
		kmac_test_vectors_shake_256	1.579h	357.474ms	49	50	98.00
		kmac_test_vectors_kmac	7.540s	1.684ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.070s	273.066us	50	50	100.00
V2	sideload	kmac_sideload	10.135m	39.698ms	50	50	100.00
V2	app	kmac_app	7.886m	120.237ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.518m	19.479ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.029m	5.525ms	48	50	96.00
V2	error	kmac_error	9.498m	184.543ms	49	50	98.00
V2	key_error	kmac_key_error	8.170s	9.112ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.040s	1.840ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	51.810s	2.257ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.291m	8.201ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.420s	1.600ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.354m	411.443ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.930s	28.733us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	28.623us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.810s	125.362us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.810s	125.362us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.240s	39.880us	5	5	100.00
		kmac_csr_rw	1.260s	27.193us	20	20	100.00
		kmac_csr_aliasing	10.700s	439.606us	5	5	100.00
		kmac_same_csr_outstanding	2.910s	512.698us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.240s	39.880us	5	5	100.00
		kmac_csr_rw	1.260s	27.193us	20	20	100.00
		kmac_csr_aliasing	10.700s	439.606us	5	5	100.00
		kmac_same_csr_outstanding	2.910s	512.698us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.090s	557.959us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.090s	557.959us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.090s	557.959us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.090s	557.959us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.370s	557.486us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.522m	5.632ms	5	5	100.00
		kmac_tl_intg_err	6.130s	1.600ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.130s	1.600ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.420s	1.600ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.454m	4.245ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.135m	39.698ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.090s	557.959us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.522m	5.632ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.522m	5.632ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.522m	5.632ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.454m	4.245ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.420s	1.600ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.522m	5.632ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.047m	18.225ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.454m	4.245ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	52.058m	266.522ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			1271	1290	98.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.06	98.40	93.36	99.93	94.55	96.03	98.87	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:

Test kmac_stress_all_with_rand_reset has 5 failures.

13.kmac_stress_all_with_rand_reset.473227707
Line 454, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11624327437 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 11624327437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.kmac_stress_all_with_rand_reset.2963594228
Line 500, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 131042415876 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 131042415876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 7.kmac_stress_all_with_rand_reset.847663816
    Line 746, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 41356482944 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 41356482944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.kmac_stress_all_with_rand_reset.1664809148
    Line 1010, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 38087695196 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 38087695196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 2 failures:

Test kmac_stress_all_with_rand_reset has 2 failures.

0.kmac_stress_all_with_rand_reset.1186459836
Line 1240, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 51633593523 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (255 [0xff] vs 43 [0x2b]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 51633593523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.kmac_stress_all_with_rand_reset.3121798330
Line 946, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 111738863367 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (23 [0x17] vs 75 [0x4b]) Mismatch between exp_digest[0] and act_digest[0]
  UVM_INFO @ 111738863367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

Test kmac_entropy_refresh has 1 failures.

13.kmac_entropy_refresh.865265594
Line 306, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest/run.log

  UVM_ERROR @ 9177171195 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 9177171195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_256 has 1 failures.

25.kmac_test_vectors_shake_256.919245371
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  57079717 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  57079717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test kmac_error has 1 failures.

20.kmac_error.918984954
Line 369, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

29.kmac_entropy_refresh.1523972205
Line 373, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 0.kmac_key_error.2374118309
    Line 245, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 188406115 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 188406115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 29.kmac_stress_all.1512307555
    Line 453, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 8642373340 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (64 [0x40] vs 10 [0xa]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8642373340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'host_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

Test kmac_stress_all_with_rand_reset has 1 failures.

40.kmac_stress_all_with_rand_reset.1245571556
Line 903, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 49653883238 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_kmac_app_agent[1].m_data_push_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_kmac_app_agent[1].m_data_push_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.kmac_app_vseq.kmac_app_seq.host_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 49653883238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 44.kmac_test_vectors_shake_128.3567477163
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:7e98c3f4-4448-45d7-b5f6-6ee0d5127dfe
```