KMAC/MASKED Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.454m 4.245ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.240s 39.880us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.260s 27.193us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 20.470s 1.080ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 10.700s 439.606us 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.040s 53.817us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.260s 27.193us 20 20 100.00
kmac_csr_aliasing 10.700s 439.606us 5 5 100.00
V1 mem_walk kmac_mem_walk 0.790s 12.973us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.540s 277.903us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 54.881m 118.534ms 50 50 100.00
V2 burst_write kmac_burst_write 27.171m 15.664ms 50 50 100.00
V2 test_vectors kmac_test_vectors_sha3_224 43.858m 650.689ms 50 50 100.00
kmac_test_vectors_sha3_256 41.736m 1.329s 50 50 100.00
kmac_test_vectors_sha3_384 33.087m 782.638ms 50 50 100.00
kmac_test_vectors_sha3_512 23.417m 116.822ms 50 50 100.00
kmac_test_vectors_shake_128 1.881h 1.714s 49 50 98.00
kmac_test_vectors_shake_256 1.579h 357.474ms 49 50 98.00
kmac_test_vectors_kmac 7.540s 1.684ms 50 50 100.00
kmac_test_vectors_kmac_xof 7.070s 273.066us 50 50 100.00
V2 sideload kmac_sideload 10.135m 39.698ms 50 50 100.00
V2 app kmac_app 7.886m 120.237ms 50 50 100.00
V2 app_with_partial_data kmac_app_with_partial_data 6.518m 19.479ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 7.029m 5.525ms 48 50 96.00
V2 error kmac_error 9.498m 184.543ms 49 50 98.00
V2 key_error kmac_key_error 8.170s 9.112ms 49 50 98.00
V2 edn_timeout_error kmac_edn_timeout_error 49.040s 1.840ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 51.810s 2.257ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.291m 8.201ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 43.420s 1.600ms 50 50 100.00
V2 stress_all kmac_stress_all 40.354m 411.443ms 49 50 98.00
V2 intr_test kmac_intr_test 0.930s 28.733us 50 50 100.00
V2 alert_test kmac_alert_test 0.960s 28.623us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.810s 125.362us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.810s 125.362us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.240s 39.880us 5 5 100.00
kmac_csr_rw 1.260s 27.193us 20 20 100.00
kmac_csr_aliasing 10.700s 439.606us 5 5 100.00
kmac_same_csr_outstanding 2.910s 512.698us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.240s 39.880us 5 5 100.00
kmac_csr_rw 1.260s 27.193us 20 20 100.00
kmac_csr_aliasing 10.700s 439.606us 5 5 100.00
kmac_same_csr_outstanding 2.910s 512.698us 20 20 100.00
V2 TOTAL 1043 1050 99.33
V2S shadow_reg_update_error kmac_shadow_reg_errors 2.090s 557.959us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 2.090s 557.959us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 2.090s 557.959us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 2.090s 557.959us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 5.370s 557.486us 20 20 100.00
V2S tl_intg_err kmac_sec_cm 1.522m 5.632ms 5 5 100.00
kmac_tl_intg_err 6.130s 1.600ms 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 6.130s 1.600ms 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 43.420s 1.600ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.454m 4.245ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 10.135m 39.698ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 2.090s 557.959us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.522m 5.632ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.522m 5.632ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.522m 5.632ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.454m 4.245ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 43.420s 1.600ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.522m 5.632ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 7.047m 18.225ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.454m 4.245ms 50 50 100.00
V2S TOTAL 75 75 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 52.058m 266.522ms 38 50 76.00
V3 TOTAL 38 50 76.00
TOTAL 1271 1290 98.53

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 19 76.00
V2S 5 5 5 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.06 98.40 93.36 99.93 94.55 96.03 98.87 98.31

Failure Buckets

Past Results