KMAC/MASKED Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.171m	34.716ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.820s	56.252us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.760s	68.962us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	28.560s	4.017ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.270s	564.051us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.920s	481.821us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.760s	68.962us	20	20	100.00
		kmac_csr_aliasing	11.270s	564.051us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.260s	22.394us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.530s	181.679us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.382h	454.608ms	50	50	100.00
V2	burst_write	kmac_burst_write	30.999m	181.948ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	55.008m	259.051ms	5	5	100.00
		kmac_test_vectors_sha3_256	42.962m	59.706ms	5	5	100.00
		kmac_test_vectors_sha3_384	24.827m	26.958ms	5	5	100.00
		kmac_test_vectors_sha3_512	22.883m	31.057ms	5	5	100.00
		kmac_test_vectors_shake_128	6.585m	96.978ms	5	5	100.00
		kmac_test_vectors_shake_256	54.931m	181.331ms	5	5	100.00
		kmac_test_vectors_kmac	3.720s	99.362us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.480s	161.726us	5	5	100.00
V2	sideload	kmac_sideload	10.985m	41.451ms	49	50	98.00
V2	app	kmac_app	8.673m	56.895ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.073m	38.645ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.191m	8.901ms	50	50	100.00
V2	error	kmac_error	10.313m	6.604ms	50	50	100.00
V2	key_error	kmac_key_error	25.570s	9.340ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.650s	140.685us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	55.690s	5.433ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.380s	5.536ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.422m	13.180ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.040s	3.798ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.226h	944.002ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.350s	25.934us	50	50	100.00
V2	alert_test	kmac_alert_test	1.460s	46.760us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.470s	64.160us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.470s	64.160us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.820s	56.252us	5	5	100.00
		kmac_csr_rw	1.760s	68.962us	20	20	100.00
		kmac_csr_aliasing	11.270s	564.051us	5	5	100.00
		kmac_same_csr_outstanding	4.130s	418.301us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.820s	56.252us	5	5	100.00
		kmac_csr_rw	1.760s	68.962us	20	20	100.00
		kmac_csr_aliasing	11.270s	564.051us	5	5	100.00
		kmac_same_csr_outstanding	4.130s	418.301us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.700s	138.845us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.700s	138.845us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.700s	138.845us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.700s	138.845us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.650s	246.517us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.946m	9.251ms	5	5	100.00
		kmac_tl_intg_err	7.570s	1.135ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.570s	1.135ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.040s	3.798ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.171m	34.716ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.985m	41.451ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.700s	138.845us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.946m	9.251ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.946m	9.251ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.946m	9.251ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.171m	34.716ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.040s	3.798ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.946m	9.251ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.336m	17.712ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.171m	34.716ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.913m	5.960ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			934	940	99.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	26	26	25	96.15
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.95	98.11	92.78	99.89	80.99	95.93	99.07	97.88

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
  • Test kmac_stress_all_with_rand_reset has 5 failures.

    • 1.kmac_stress_all_with_rand_reset.60627691443032082877508904099590468101206796809685537683846114566681943726259
      Line 239, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2334734416 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2334734416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.kmac_stress_all_with_rand_reset.16790764536779594669186121000815079512694574430458607249247565488384483932211
      Line 87, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  56214399 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
        UVM_INFO @  56214399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
  • Test kmac_sideload has 1 failures.

    • 31.kmac_sideload.43080201767913946819365940856590710521219303938022701926589373969215323379602
      Line 67, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_sideload/latest/run.log

        UVM_ERROR @  66639754 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  66639754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.10.13_03.38.38
• 2024.10.10_10.14.52
• 2024.10.04_00.41.45
• 2024.09.25_11.00.45
• 2024.09.19_09.04.31
• 2024.09.12_10.16.09
• 2024.09.10_08.11.01