KMAC/MASKED Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.865m	10.942ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	180.241us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.350s	36.240us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.340s	565.854us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.320s	1.082ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.840s	176.865us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.350s	36.240us	20	20	100.00
		kmac_csr_aliasing	8.320s	1.082ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	25.700us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.360s	21.623us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.907m	328.910ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.242m	29.090ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.858m	602.437ms	50	50	100.00
		kmac_test_vectors_sha3_256	38.957m	542.916ms	49	50	98.00
		kmac_test_vectors_sha3_384	35.579m	1.374s	50	50	100.00
		kmac_test_vectors_sha3_512	24.705m	442.983ms	49	50	98.00
		kmac_test_vectors_shake_128	1.815h	2.175s	50	50	100.00
		kmac_test_vectors_shake_256	1.560h	1.139s	50	50	100.00
		kmac_test_vectors_kmac	10.290s	1.384ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.860s	1.938ms	50	50	100.00
V2	sideload	kmac_sideload	9.683m	192.043ms	50	50	100.00
V2	app	kmac_app	6.564m	35.928ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.681m	23.924ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.539m	74.987ms	49	50	98.00
V2	error	kmac_error	9.959m	85.135ms	49	50	98.00
V2	key_error	kmac_key_error	7.830s	2.682ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	56.980s	1.671ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.110s	20.873ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.239m	75.494ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.075m	3.213ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.289m	95.672ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.890s	31.951us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	25.802us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.430s	218.169us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.430s	218.169us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	180.241us	5	5	100.00
		kmac_csr_rw	1.350s	36.240us	20	20	100.00
		kmac_csr_aliasing	8.320s	1.082ms	5	5	100.00
		kmac_same_csr_outstanding	2.950s	122.731us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	180.241us	5	5	100.00
		kmac_csr_rw	1.350s	36.240us	20	20	100.00
		kmac_csr_aliasing	8.320s	1.082ms	5	5	100.00
		kmac_same_csr_outstanding	2.950s	122.731us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.810s	334.758us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.810s	334.758us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.810s	334.758us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.810s	334.758us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.250s	361.565us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.736m	64.162ms	5	5	100.00
		kmac_tl_intg_err	5.550s	398.811us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.550s	398.811us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.075m	3.213ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.865m	10.942ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.683m	192.043ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.810s	334.758us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.736m	64.162ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.736m	64.162ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.736m	64.162ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.865m	10.942ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.075m	3.213ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.736m	64.162ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.235m	20.430ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.865m	10.942ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	58.150m	118.086ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			1246	1290	96.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.73	98.10	92.71	99.89	93.64	95.97	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test kmac_stress_all_with_rand_reset has 29 failures.
  - 0.kmac_stress_all_with_rand_reset.34807071542223470730089586779445055615591966886677639754996668741701377473129
    Line 432, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64232576616 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 64232576616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.50284302165371209174062709569965034330279278355519552884727865342665068696157
    Line 609, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36235883330 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36235883330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 8.kmac_stress_all_with_rand_reset.16498673017372135945325836947712296771238529025204372631132817028051252153600
    Line 625, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 118158989294 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 118158989294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.kmac_stress_all_with_rand_reset.62010490807703990958818950776586763183816101846086134868357842010401738001406
    Line 1837, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 136766129813 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 136766129813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 3.kmac_test_vectors_sha3_256.2085058669822764512383534813839153521526490618752619017662550721842672964599
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  28744956 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  28744956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 16.kmac_test_vectors_sha3_512.98030794514470421844807495729313614082616808523103903627226134294908341705705
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @  62624220 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  62624220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 17.kmac_stress_all.3516195009175073899621328425503159760336764265102623224078021645109551685732
    Line 1479, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 131482931471 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 131482931471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app_with_partial_data has 1 failures.

3.kmac_app_with_partial_data.58970576992417575569203959437010264987298173146547961384385702067782103573366
Line 379, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 4543474653 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (2 [0x2] vs 57 [0x39]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4543474653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

18.kmac_entropy_refresh.5873088793654748864521714629691451041586083182795494156791657811344682450502
Line 705, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 83474886901 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (209 [0xd1] vs 11 [0xb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 83474886901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

34.kmac_app.29241576581506020368597361761696613989004738052017563466606010816132139949326
Line 547, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_app/latest/run.log

  UVM_FATAL @ 8333785363 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (255 [0xff] vs 193 [0xc1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8333785363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all has 1 failures.
  - 11.kmac_stress_all.1734910415888601762609247859252792010935635763108030361583281936247336423544
    Line 982, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 33267974763 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 33267974763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 27.kmac_error.68811749083169923827959767680657686007132494217418474729312481636622214151688
    Line 976, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_error/latest/run.log
```
  UVM_FATAL @ 10042382402 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10042382402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 30.kmac_stress_all_with_rand_reset.60419574563985052219388092721323383166187470770498317466620026478548606882527
    Line 2077, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 231699449239 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 231699449239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```