Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	243509045	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

169418790

1

T17

7

T18

638

T19

1836

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	212229635	1			T17	11		T18	305		T19	3423
values[0x0]	96350225	1			T17	2		T18	165		T19	27
values[0x1]	104347975	1			T17	9		T18	169		T19	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	189820705	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

223107130

1

T17

10

T18

638

T19

2168

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1619260	1			T19	3		T66	3		T71	2
valid_sources[0x01]	1622245	1			T19	20		T66	20		T14	2
valid_sources[0x02]	1625930	1			T19	10		T66	10		T3	10
valid_sources[0x03]	1623055	1			T18	4		T19	6		T66	6
valid_sources[0x04]	1680855	1			T18	5		T19	13		T66	13
valid_sources[0x05]	1615150	1			T19	12		T66	12		T3	7
valid_sources[0x06]	1645045	1			T18	2		T19	13		T66	13
valid_sources[0x07]	1675760	1			T19	7		T66	7		T1	1
valid_sources[0x08]	1637880	1			T17	1		T19	15		T66	15
valid_sources[0x09]	1622880	1			T19	31		T66	31		T68	5
valid_sources[0x0a]	1625060	1			T19	16		T66	16		T1	1
valid_sources[0x0b]	1570435	1			T18	11		T19	10		T66	10
valid_sources[0x0c]	1529705	1			T19	5		T66	5		T1	2
valid_sources[0x0d]	1535180	1			T19	8		T66	8		T1	1
valid_sources[0x0e]	1589680	1			T18	3		T19	16		T66	16
valid_sources[0x0f]	1600590	1			T19	17		T66	17		T1	1
valid_sources[0x10]	1638970	1			T19	10		T66	10		T20	1757
valid_sources[0x11]	1575995	1			T18	11		T19	10		T66	10
valid_sources[0x12]	1634210	1			T18	2		T19	4		T66	4
valid_sources[0x13]	1588465	1			T19	32		T66	32		T1	1
valid_sources[0x14]	1559445	1			T19	4		T66	4		T68	10
valid_sources[0x15]	1617705	1			T19	27		T66	27		T1	3
valid_sources[0x16]	1661320	1			T18	2		T19	32		T66	32
valid_sources[0x17]	1611930	1			T19	24		T66	24		T69	4
valid_sources[0x18]	1630505	1			T19	8		T66	8		T71	9
valid_sources[0x19]	1671810	1			T19	6		T66	6		T1	2
valid_sources[0x1a]	1680060	1			T18	3		T19	2		T66	2
valid_sources[0x1b]	1646270	1			T19	34		T66	34		T68	7
valid_sources[0x1c]	1552040	1			T18	16		T19	17		T66	17
valid_sources[0x1d]	1608125	1			T18	3		T19	8		T66	8
valid_sources[0x1e]	1596620	1			T18	2		T19	12		T66	12
valid_sources[0x1f]	1615380	1			T19	9		T66	9		T69	3
valid_sources[0x20]	1587745	1			T18	3		T19	7		T66	7
valid_sources[0x21]	1615560	1			T19	28		T66	28		T1	1
valid_sources[0x22]	1636555	1			T18	1		T19	15		T66	15
valid_sources[0x23]	1636905	1			T18	2		T19	4		T66	4
valid_sources[0x24]	1620765	1			T19	13		T66	13		T3	10
valid_sources[0x25]	1605300	1			T19	21		T66	21		T68	1
valid_sources[0x26]	1621860	1			T19	12		T66	12		T1	3
valid_sources[0x27]	1608595	1			T18	2		T19	11		T66	11
valid_sources[0x28]	1599990	1			T18	7		T19	20		T66	20
valid_sources[0x29]	1689345	1			T19	2		T66	2		T71	3
valid_sources[0x2a]	1642780	1			T19	12		T66	12		T68	4
valid_sources[0x2b]	1621465	1			T19	4		T66	4		T1	7
valid_sources[0x2c]	1664745	1			T18	11		T19	1		T66	1
valid_sources[0x2d]	1618405	1			T18	4		T19	12		T66	12
valid_sources[0x2e]	1635090	1			T18	11		T19	18		T66	18
valid_sources[0x2f]	1649965	1			T19	6		T66	6		T68	8
valid_sources[0x30]	1569280	1			T19	27		T66	27		T14	3
valid_sources[0x31]	1651760	1			T18	4		T19	16		T66	16
valid_sources[0x32]	1638095	1			T19	16		T66	16		T1	3
valid_sources[0x33]	1645205	1			T18	3		T19	8		T66	8
valid_sources[0x34]	1592410	1			T19	25		T66	25		T68	1
valid_sources[0x35]	1612515	1			T19	16		T66	16		T71	2
valid_sources[0x36]	1598275	1			T19	27		T66	27		T68	1
valid_sources[0x37]	1621810	1			T17	2		T19	4		T66	4
valid_sources[0x38]	1567070	1			T19	24		T66	24		T68	6
valid_sources[0x39]	1591660	1			T18	11		T19	37		T66	37
valid_sources[0x3a]	1626780	1			T18	2		T19	9		T66	9
valid_sources[0x3b]	1629075	1			T19	3		T66	3		T71	3
valid_sources[0x3c]	1648970	1			T19	10		T66	10		T69	9
valid_sources[0x3d]	1657185	1			T18	6		T19	14		T66	14
valid_sources[0x3e]	1541980	1			T18	1		T19	9		T66	9
valid_sources[0x3f]	1674195	1			T18	3		T19	13		T66	13
valid_sources[0x40]	1651975	1			T19	21		T66	21		T69	3
valid_sources[0x41]	1612275	1			T18	1		T19	9		T66	9
valid_sources[0x42]	1612395	1			T18	16		T19	14		T66	14
valid_sources[0x43]	1592400	1			T19	12		T66	12		T1	1
valid_sources[0x44]	1623885	1			T17	2		T18	2		T19	36
valid_sources[0x45]	1654750	1			T18	1		T19	8		T66	8
valid_sources[0x46]	1617925	1			T18	5		T19	12		T66	12
valid_sources[0x47]	1622860	1			T18	12		T68	1		T3	4
valid_sources[0x48]	1680195	1			T19	31		T66	31		T3	2
valid_sources[0x49]	1600720	1			T19	10		T66	10		T68	3
valid_sources[0x4a]	1616125	1			T18	1		T19	8		T66	8
valid_sources[0x4b]	1651470	1			T18	3		T19	3		T66	3
valid_sources[0x4c]	1637880	1			T18	3		T19	7		T66	7
valid_sources[0x4d]	1603670	1			T19	39		T66	39		T68	8
valid_sources[0x4e]	1608030	1			T19	54		T66	54		T1	2
valid_sources[0x4f]	1633305	1			T18	10		T19	9		T66	9
valid_sources[0x50]	1610930	1			T18	5		T19	8		T66	8
valid_sources[0x51]	1600155	1			T18	1		T19	37		T66	37
valid_sources[0x52]	1608650	1			T19	12		T66	12		T3	25
valid_sources[0x53]	1679090	1			T18	19		T19	1		T66	1
valid_sources[0x54]	1657165	1			T19	19		T66	19		T3	1
valid_sources[0x55]	1633920	1			T18	2		T19	12		T66	12
valid_sources[0x56]	1539525	1			T18	2		T19	14		T66	14
valid_sources[0x57]	1605715	1			T18	2		T19	16		T66	16
valid_sources[0x58]	1561720	1			T18	8		T19	9		T66	9
valid_sources[0x59]	1607110	1			T18	6		T19	8		T66	8
valid_sources[0x5a]	1598070	1			T19	18		T66	18		T3	7
valid_sources[0x5b]	1650365	1			T18	1		T19	4		T66	4
valid_sources[0x5c]	1600635	1			T19	10		T66	10		T20	1728
valid_sources[0x5d]	1617045	1			T18	4		T19	12		T66	12
valid_sources[0x5e]	1632300	1			T19	25		T66	25		T1	1
valid_sources[0x5f]	1610505	1			T19	11		T66	11		T68	5
valid_sources[0x60]	1634760	1			T18	5		T19	37		T66	37
valid_sources[0x61]	1635885	1			T18	6		T19	3		T66	3
valid_sources[0x62]	1585215	1			T18	3		T19	13		T66	13
valid_sources[0x63]	1605210	1			T19	16		T66	16		T68	4
valid_sources[0x64]	1614415	1			T19	9		T66	9		T68	5
valid_sources[0x65]	1582240	1			T17	2		T18	7		T19	10
valid_sources[0x66]	1555750	1			T19	19		T66	19		T1	2
valid_sources[0x67]	1609710	1			T18	3		T19	14		T66	14
valid_sources[0x68]	1667485	1			T18	6		T19	15		T66	15
valid_sources[0x69]	1611060	1			T18	1		T19	6		T66	6
valid_sources[0x6a]	1635270	1			T19	22		T66	22		T3	5
valid_sources[0x6b]	1592300	1			T19	13		T66	13		T20	1723
valid_sources[0x6c]	1623795	1			T18	1		T19	11		T66	11
valid_sources[0x6d]	1589245	1			T19	3		T66	3		T1	1
valid_sources[0x6e]	1580790	1			T19	14		T66	14		T1	1
valid_sources[0x6f]	1561070	1			T18	7		T19	7		T66	7
valid_sources[0x70]	1598895	1			T19	7		T66	7		T1	2
valid_sources[0x71]	1627280	1			T19	11		T66	11		T3	7
valid_sources[0x72]	1615590	1			T19	3		T66	3		T68	2
valid_sources[0x73]	1564195	1			T19	9		T66	9		T68	1
valid_sources[0x74]	1527480	1			T18	4		T19	3		T66	3
valid_sources[0x75]	1611865	1			T18	7		T19	8		T66	8
valid_sources[0x76]	1628755	1			T19	15		T66	15		T3	2
valid_sources[0x77]	1577315	1			T18	1		T19	6		T66	6
valid_sources[0x78]	1612910	1			T19	15		T66	15		T20	1751
valid_sources[0x79]	1570900	1			T19	9		T66	9		T68	2
valid_sources[0x7a]	1630575	1			T19	12		T66	12		T68	5
valid_sources[0x7b]	1612300	1			T19	9		T66	9		T3	7
valid_sources[0x7c]	1656050	1			T19	1		T66	1		T68	7
valid_sources[0x7d]	1601850	1			T18	2		T19	1		T66	1
valid_sources[0x7e]	1633010	1			T19	4		T66	4		T1	1
valid_sources[0x7f]	1636550	1			T17	4		T18	2		T67	4
valid_sources[0x80]	1550580	1			T19	44		T66	44		T69	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65966465

1

T17

6

T18

304

T19

1782

values[0x0]

all_enables

biggest_size

55864610

1

T18

165

T19

24

T66

24

values[0x1]

all_enables

biggest_size

47587715

1

T17

1

T18

169

T19

30