Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	99846950	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1240	1240	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	99846950	0	0
T1	5781	292	0	0
T2	5781	292	0	0
T3	10814	0	0	0
T4	5781	292	0	0
T6	0	292	0	0
T11	1284	0	0	0
T12	4930	0	0	0
T20	0	107146	0	0
T21	0	455924	0	0
T22	0	6181	0	0
T30	0	75686	0	0
T68	2628	280	0	0
T69	1837	0	0	0
T70	947	0	0	0
T71	2174	0	0	0
T72	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240	1240	0	0
T1	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	99649670	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1240	1240	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	99649670	0	0
T1	5781	284	0	0
T2	5781	284	0	0
T3	10814	0	0	0
T4	5781	284	0	0
T6	0	284	0	0
T11	1284	0	0	0
T12	4930	0	0	0
T20	0	107146	0	0
T21	0	455924	0	0
T22	0	6181	0	0
T30	0	75096	0	0
T68	2628	260	0	0
T69	1837	0	0	0
T70	947	0	0	0
T71	2174	0	0	0
T72	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240	1240	0	0
T1	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	295392765	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1240	1240	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	295392765	0	0
T1	5781	347	0	0
T17	1284	22	0	0
T18	4930	678	0	0
T19	22594	3755	0	0
T66	22594	3755	0	0
T67	1284	22	0	0
T68	2628	3	0	0
T69	1837	144	0	0
T70	947	1	0	0
T71	2174	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240	1240	0	0
T1	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	295386645	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1240	1240	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	295386645	0	0
T1	5781	336	0	0
T17	1284	22	0	0
T18	4930	639	0	0
T19	22594	3483	0	0
T66	22594	3483	0	0
T67	1284	22	0	0
T68	2628	3	0	0
T69	1837	132	0	0
T70	947	1	0	0
T71	2174	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5781	5719	0	0
T17	1284	1222	0	0
T18	4930	4868	0	0
T19	22594	22532	0	0
T66	22594	22532	0	0
T67	1284	1222	0	0
T68	2628	2566	0	0
T69	1837	1775	0	0
T70	947	885	0	0
T71	2174	1910	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240	1240	0	0
T1	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0