KMAC/MASKED Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	28.660s	1.925ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	29.369us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.040s	32.815us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.800s	934.951us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.000s	403.473us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.410s	30.369us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.040s	32.815us	20	20	100.00
		kmac_csr_aliasing	6.000s	403.473us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	16.922us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.260s	46.940us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	18.051m	50.514ms	50	50	100.00
V2	burst_write	kmac_burst_write	7.008m	14.830ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.973m	117.330ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.508m	106.843ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.692m	83.520ms	50	50	100.00
		kmac_test_vectors_sha3_512	21.208m	57.499ms	50	50	100.00
		kmac_test_vectors_shake_128	1.562h	320.694ms	50	50	100.00
		kmac_test_vectors_shake_256	1.344h	270.086ms	50	50	100.00
		kmac_test_vectors_kmac	6.360s	322.956us	50	50	100.00
		kmac_test_vectors_kmac_xof	6.180s	309.259us	50	50	100.00
V2	sideload	kmac_sideload	2.417m	7.628ms	50	50	100.00
V2	app	kmac_app	1.788m	6.077ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.951m	7.278ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.004m	7.239ms	50	50	100.00
V2	error	kmac_error	2.628m	8.138ms	50	50	100.00
V2	key_error	kmac_key_error	5.950s	1.580ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.320s	62.261us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.350s	64.850us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	22.620s	3.179ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.650s	72.761us	50	50	100.00
V2	stress_all	kmac_stress_all	15.598m	47.207ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.890s	22.940us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	21.119us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.230s	103.243us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.230s	103.243us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	29.369us	5	5	100.00
		kmac_csr_rw	1.040s	32.815us	20	20	100.00
		kmac_csr_aliasing	6.000s	403.473us	5	5	100.00
		kmac_same_csr_outstanding	1.720s	88.047us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	29.369us	5	5	100.00
		kmac_csr_rw	1.040s	32.815us	20	20	100.00
		kmac_csr_aliasing	6.000s	403.473us	5	5	100.00
		kmac_same_csr_outstanding	1.720s	88.047us	20	20	100.00
V2		TOTAL			1050	1050	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.120s	38.833us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.120s	38.833us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.120s	38.833us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.120s	38.833us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.890s	96.832us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	55.690s	6.415ms	5	5	100.00
		kmac_tl_intg_err	3.200s	193.117us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.200s	193.117us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.650s	72.761us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	28.660s	1.925ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.417m	7.628ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.120s	38.833us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	55.690s	6.415ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	55.690s	6.415ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	55.690s	6.415ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	28.660s	1.925ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.650s	72.761us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	55.690s	6.415ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.357m	7.712ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	28.660s	1.925ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.326m	7.552ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1240	1290	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	25	100.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.63	98.10	88.18	99.93	80.00	95.24	96.52	90.42

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 50 failures:
  • Test kmac_stress_all_with_rand_reset has 50 failures.

    • 0.kmac_stress_all_with_rand_reset.85009197254513948138565410223971586607515573047824581158324987495185095890648
      Line 343, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7552433355 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 7552433355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.89749292489590429304176314493329540522094975941889093261986151261331645979511
      Line 343, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7552433355 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 7552433355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 48 more failures.

Past Results

• Latest
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