Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	324	1			T2	5		T6	1		T14	5
all_values[1]	324	1			T2	5		T6	1		T14	5
all_values[2]	324	1			T2	5		T6	1		T14	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

538

1

T2

9

T6

3

T14

4

auto[1]

434

1

T2

6

T14

11

T58

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

612

1

T2

12

T6

3

T14

6

auto[1]

360

1

T2

3

T14

9

T58

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	132	1			T2	3		T6	1		T21	1
all_values[0]	auto[0]	auto[1]	65	1			T2	1		T14	1		T58	2
all_values[0]	auto[1]	auto[0]	72	1			T2	1		T14	2		T58	1
all_values[0]	auto[1]	auto[1]	55	1			T14	2		T16	2		T17	1
all_values[1]	auto[0]	auto[0]	122	1			T2	4		T6	1		T21	1
all_values[1]	auto[0]	auto[1]	67	1			T58	2		T16	2		T76	2
all_values[1]	auto[1]	auto[0]	82	1			T14	2		T16	4		T17	3
all_values[1]	auto[1]	auto[1]	53	1			T2	1		T14	3		T16	1
all_values[2]	auto[0]	auto[0]	83	1			T6	1		T14	1		T21	1
all_values[2]	auto[0]	auto[1]	69	1			T2	1		T14	2		T58	2
all_values[2]	auto[1]	auto[0]	121	1			T2	4		T14	1		T58	2
all_values[2]	auto[1]	auto[1]	51	1			T14	1		T16	1		T84	3