Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
42.68	30.85	57.75	8.00	0.00	39.88	100.00	62.25

Total tests in report: 215

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
38.06	38.06	30.56	30.56	51.22	51.22	10.59	10.59	0.00	0.00	38.90	38.90	91.88	91.88	43.24	43.24	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1551216574
39.75	1.69	30.82	0.26	53.88	2.66	10.72	0.13	0.00	0.00	39.45	0.55	94.50	2.62	48.87	5.63	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.1541006495
40.82	1.07	30.85	0.04	54.55	0.67	10.78	0.06	0.00	0.00	39.70	0.24	94.50	0.00	55.35	6.48	/workspace/coverage/cover_reg_top/49.kmac_intr_test.1821501331
41.85	1.03	30.85	0.00	56.02	1.47	10.87	0.09	0.00	0.00	39.88	0.18	98.17	3.66	57.18	1.83	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2348774984
42.29	0.43	30.85	0.00	56.92	0.90	11.04	0.17	0.00	0.00	39.88	0.00	98.17	0.00	59.15	1.97	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2352337877
42.67	0.38	30.85	0.00	57.21	0.29	12.19	1.15	0.00	0.00	39.88	0.00	98.43	0.26	60.14	0.99	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3075451335
42.90	0.22	30.85	0.00	57.21	0.00	12.19	0.00	0.00	0.00	39.88	0.00	100.00	1.57	60.14	0.00	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.4018989360
42.98	0.08	30.85	0.00	57.21	0.00	12.19	0.00	0.00	0.00	39.88	0.00	100.00	0.00	60.70	0.56	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1781651530
43.05	0.07	30.85	0.00	57.43	0.22	12.19	0.00	0.00	0.00	39.88	0.00	100.00	0.00	60.99	0.28	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.1920614113
43.11	0.06	30.85	0.00	57.43	0.00	12.19	0.00	0.00	0.00	39.88	0.00	100.00	0.00	61.41	0.42	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.838113736
43.17	0.06	30.85	0.00	57.56	0.13	12.19	0.00	0.00	0.00	39.88	0.00	100.00	0.00	61.69	0.28	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1441447648
43.19	0.03	30.85	0.00	57.75	0.19	12.19	0.00	0.00	0.00	39.88	0.00	100.00	0.00	61.69	0.00	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.2474464331
43.22	0.02	30.85	0.00	57.75	0.00	12.36	0.17	0.00	0.00	39.88	0.00	100.00	0.00	61.69	0.00	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.61917503
43.24	0.02	30.85	0.00	57.75	0.00	12.39	0.03	0.00	0.00	39.88	0.00	100.00	0.00	61.83	0.14	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2535687854
43.26	0.02	30.85	0.00	57.75	0.00	12.39	0.00	0.00	0.00	39.88	0.00	100.00	0.00	61.97	0.14	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3225842129
43.28	0.02	30.85	0.00	57.75	0.00	12.39	0.00	0.00	0.00	39.88	0.00	100.00	0.00	62.11	0.14	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2454874758
43.30	0.02	30.85	0.00	57.75	0.00	12.39	0.00	0.00	0.00	39.88	0.00	100.00	0.00	62.25	0.14	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.249372889
43.31	0.01	30.85	0.00	57.75	0.00	12.40	0.01	0.00	0.00	39.88	0.00	100.00	0.00	62.25	0.00	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1490607606

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3037987003
/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3439441059
/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.29057040
/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3164169144
/workspace/coverage/cover_reg_top/0.kmac_csr_rw.1062206432
/workspace/coverage/cover_reg_top/0.kmac_intr_test.2450519112
/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.604887791
/workspace/coverage/cover_reg_top/0.kmac_mem_walk.2157559433
/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3950650582
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3748877149
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1841971626
/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1184312266
/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.4196829607
/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2049348342
/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.307654989
/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.749660234
/workspace/coverage/cover_reg_top/1.kmac_csr_rw.1012169910
/workspace/coverage/cover_reg_top/1.kmac_intr_test.2905177088
/workspace/coverage/cover_reg_top/1.kmac_mem_walk.874050865
/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.426450314
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3695739049
/workspace/coverage/cover_reg_top/1.kmac_tl_errors.569687700
/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2366921054
/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2008942353
/workspace/coverage/cover_reg_top/10.kmac_csr_rw.1302275080
/workspace/coverage/cover_reg_top/10.kmac_intr_test.3986382148
/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2731902940
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1591628936
/workspace/coverage/cover_reg_top/10.kmac_tl_errors.1524065595
/workspace/coverage/cover_reg_top/11.kmac_csr_rw.3381592362
/workspace/coverage/cover_reg_top/11.kmac_intr_test.3377110729
/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2671411664
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.68571746
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1963639607
/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3536938080
/workspace/coverage/cover_reg_top/12.kmac_csr_rw.1025903844
/workspace/coverage/cover_reg_top/12.kmac_intr_test.1780789685
/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.861081619
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3472745163
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3497257693
/workspace/coverage/cover_reg_top/12.kmac_tl_errors.3093139614
/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1553561014
/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2093801089
/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2118099099
/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2387709337
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3929882152
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2030488925
/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1864563841
/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3964959068
/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3304754766
/workspace/coverage/cover_reg_top/14.kmac_csr_rw.1570953052
/workspace/coverage/cover_reg_top/14.kmac_intr_test.3341756151
/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.4099279712
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1444955274
/workspace/coverage/cover_reg_top/14.kmac_tl_errors.3589469590
/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1032826427
/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.456901435
/workspace/coverage/cover_reg_top/15.kmac_csr_rw.1994581554
/workspace/coverage/cover_reg_top/15.kmac_intr_test.1499101428
/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1801333064
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2241429282
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2892993988
/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2840120087
/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.661751935
/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1861830459
/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1707485108
/workspace/coverage/cover_reg_top/16.kmac_intr_test.2949478502
/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.788371304
/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3383601999
/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.1755046206
/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1921631474
/workspace/coverage/cover_reg_top/17.kmac_csr_rw.4116493741
/workspace/coverage/cover_reg_top/17.kmac_intr_test.3980471312
/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2625471840
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3891010738
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.225487696
/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3745515250
/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.4132830605
/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3383135475
/workspace/coverage/cover_reg_top/18.kmac_csr_rw.4091696078
/workspace/coverage/cover_reg_top/18.kmac_intr_test.3050761789
/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1254514254
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1380034364
/workspace/coverage/cover_reg_top/18.kmac_tl_errors.2206931064
/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1450647648
/workspace/coverage/cover_reg_top/19.kmac_csr_rw.2392185965
/workspace/coverage/cover_reg_top/19.kmac_intr_test.3799853199
/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.304044302
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2647288827
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2350674481
/workspace/coverage/cover_reg_top/19.kmac_tl_errors.2891857976
/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3049388355
/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.866062205
/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.525734965
/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.451774927
/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.648609532
/workspace/coverage/cover_reg_top/2.kmac_csr_rw.2404322200
/workspace/coverage/cover_reg_top/2.kmac_intr_test.3733169843
/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3563709254
/workspace/coverage/cover_reg_top/2.kmac_mem_walk.2715660119
/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2697787221
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3568365258
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3384873701
/workspace/coverage/cover_reg_top/2.kmac_tl_errors.4271927801
/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.381413049
/workspace/coverage/cover_reg_top/20.kmac_intr_test.4028380479
/workspace/coverage/cover_reg_top/21.kmac_intr_test.3153915181
/workspace/coverage/cover_reg_top/22.kmac_intr_test.1266100669
/workspace/coverage/cover_reg_top/23.kmac_intr_test.941932193
/workspace/coverage/cover_reg_top/24.kmac_intr_test.1554600448
/workspace/coverage/cover_reg_top/25.kmac_intr_test.488307969
/workspace/coverage/cover_reg_top/26.kmac_intr_test.352443458
/workspace/coverage/cover_reg_top/27.kmac_intr_test.302737263
/workspace/coverage/cover_reg_top/28.kmac_intr_test.2560868566
/workspace/coverage/cover_reg_top/29.kmac_intr_test.4059189065
/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.2822954160
/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.4118655960
/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3742687665
/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1332500965
/workspace/coverage/cover_reg_top/3.kmac_csr_rw.2812730616
/workspace/coverage/cover_reg_top/3.kmac_intr_test.2498182461
/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1873492143
/workspace/coverage/cover_reg_top/3.kmac_mem_walk.155445570
/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3251033287
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3212631258
/workspace/coverage/cover_reg_top/3.kmac_tl_errors.2108168042
/workspace/coverage/cover_reg_top/30.kmac_intr_test.3534559194
/workspace/coverage/cover_reg_top/31.kmac_intr_test.23392159
/workspace/coverage/cover_reg_top/32.kmac_intr_test.2111474969
/workspace/coverage/cover_reg_top/33.kmac_intr_test.538506818
/workspace/coverage/cover_reg_top/34.kmac_intr_test.1132435477
/workspace/coverage/cover_reg_top/35.kmac_intr_test.2811786242
/workspace/coverage/cover_reg_top/36.kmac_intr_test.102335570
/workspace/coverage/cover_reg_top/37.kmac_intr_test.118702181
/workspace/coverage/cover_reg_top/38.kmac_intr_test.1116007189
/workspace/coverage/cover_reg_top/39.kmac_intr_test.2598193493
/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3896310651
/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2145111538
/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3366419360
/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1233416416
/workspace/coverage/cover_reg_top/4.kmac_csr_rw.289747953
/workspace/coverage/cover_reg_top/4.kmac_intr_test.3950794099
/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.71073699
/workspace/coverage/cover_reg_top/4.kmac_mem_walk.3696328435
/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.508569933
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2336775676
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2324970130
/workspace/coverage/cover_reg_top/4.kmac_tl_errors.1304812613
/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3397791779
/workspace/coverage/cover_reg_top/40.kmac_intr_test.744766498
/workspace/coverage/cover_reg_top/41.kmac_intr_test.885115247
/workspace/coverage/cover_reg_top/42.kmac_intr_test.346619096
/workspace/coverage/cover_reg_top/43.kmac_intr_test.1464133286
/workspace/coverage/cover_reg_top/44.kmac_intr_test.54940551
/workspace/coverage/cover_reg_top/45.kmac_intr_test.701005764
/workspace/coverage/cover_reg_top/46.kmac_intr_test.935575936
/workspace/coverage/cover_reg_top/47.kmac_intr_test.2149480697
/workspace/coverage/cover_reg_top/48.kmac_intr_test.2337981136
/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3901789146
/workspace/coverage/cover_reg_top/5.kmac_csr_rw.1762392480
/workspace/coverage/cover_reg_top/5.kmac_intr_test.2881188811
/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1031234511
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2478556062
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2921729098
/workspace/coverage/cover_reg_top/5.kmac_tl_errors.2072232423
/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2408370890
/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.890737842
/workspace/coverage/cover_reg_top/6.kmac_csr_rw.2276666283
/workspace/coverage/cover_reg_top/6.kmac_intr_test.2147308082
/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3143867335
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.4150004006
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3247319532
/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3028361779
/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3382672853
/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1127941375
/workspace/coverage/cover_reg_top/7.kmac_csr_rw.345376810
/workspace/coverage/cover_reg_top/7.kmac_intr_test.1456502825
/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1300981256
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2320791497
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3952822943
/workspace/coverage/cover_reg_top/7.kmac_tl_errors.2548760577
/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3095893192
/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3917698459
/workspace/coverage/cover_reg_top/8.kmac_csr_rw.485006780
/workspace/coverage/cover_reg_top/8.kmac_intr_test.2856145691
/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.456650702
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2254826045
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3558552422
/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1630885376
/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1648314977
/workspace/coverage/cover_reg_top/9.kmac_csr_rw.1669441215
/workspace/coverage/cover_reg_top/9.kmac_intr_test.79933955
/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3859309595
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2938163038
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2266522437
/workspace/coverage/cover_reg_top/9.kmac_tl_errors.1221003598
/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.666211356

Total test records in report: 215

tests.html | tests1.html | tests2.html | tests3.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1551216574	Dec 20 12:33:13 PM PST 23	Dec 20 12:34:04 PM PST 23	207401268 ps
T2	/workspace/coverage/cover_reg_top/23.kmac_intr_test.941932193	Dec 20 12:36:58 PM PST 23	Dec 20 12:37:36 PM PST 23	22549662 ps
T3	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2049348342	Dec 20 12:33:16 PM PST 23	Dec 20 12:34:24 PM PST 23	1084467650 ps
T4	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.456901435	Dec 20 12:37:03 PM PST 23	Dec 20 12:37:44 PM PST 23	91707747 ps
T5	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2348774984	Dec 20 12:37:08 PM PST 23	Dec 20 12:37:52 PM PST 23	163519378 ps
T6	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.1920614113	Dec 20 12:36:43 PM PST 23	Dec 20 12:37:16 PM PST 23	149383214 ps
T14	/workspace/coverage/cover_reg_top/27.kmac_intr_test.302737263	Dec 20 12:36:31 PM PST 23	Dec 20 12:36:36 PM PST 23	22048881 ps
T18	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.4099279712	Dec 20 12:36:28 PM PST 23	Dec 20 12:36:35 PM PST 23	98301092 ps
T19	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3383135475	Dec 20 12:37:01 PM PST 23	Dec 20 12:37:42 PM PST 23	100966134 ps
T20	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.485006780	Dec 20 12:36:51 PM PST 23	Dec 20 12:37:24 PM PST 23	117190028 ps
T31	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.2404322200	Dec 20 12:32:53 PM PST 23	Dec 20 12:33:41 PM PST 23	110267070 ps
T7	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3497257693	Dec 20 12:37:13 PM PST 23	Dec 20 12:38:02 PM PST 23	141032638 ps
T32	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3748877149	Dec 20 12:32:53 PM PST 23	Dec 20 12:33:42 PM PST 23	22213060 ps
T37	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.4196829607	Dec 20 12:32:55 PM PST 23	Dec 20 12:33:54 PM PST 23	880236415 ps
T21	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.2474464331	Dec 20 12:36:43 PM PST 23	Dec 20 12:37:07 PM PST 23	40536882 ps
T15	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3366419360	Dec 20 12:36:33 PM PST 23	Dec 20 12:36:39 PM PST 23	62130941 ps
T58	/workspace/coverage/cover_reg_top/29.kmac_intr_test.4059189065	Dec 20 12:36:36 PM PST 23	Dec 20 12:36:46 PM PST 23	35487316 ps
T89	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.2157559433	Dec 20 12:32:55 PM PST 23	Dec 20 12:33:44 PM PST 23	11785241 ps
T22	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3917698459	Dec 20 12:36:42 PM PST 23	Dec 20 12:37:20 PM PST 23	56625520 ps
T59	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.1012169910	Dec 20 12:33:01 PM PST 23	Dec 20 12:33:52 PM PST 23	44313809 ps
T33	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.666211356	Dec 20 12:36:37 PM PST 23	Dec 20 12:36:54 PM PST 23	541882737 ps
T16	/workspace/coverage/cover_reg_top/49.kmac_intr_test.1821501331	Dec 20 12:36:57 PM PST 23	Dec 20 12:37:33 PM PST 23	39278370 ps
T41	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.4118655960	Dec 20 12:36:30 PM PST 23	Dec 20 12:36:46 PM PST 23	1393621733 ps
T42	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3143867335	Dec 20 12:36:31 PM PST 23	Dec 20 12:36:38 PM PST 23	378702956 ps
T43	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.1302275080	Dec 20 12:36:56 PM PST 23	Dec 20 12:37:33 PM PST 23	36787271 ps
T8	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3075451335	Dec 20 12:37:21 PM PST 23	Dec 20 12:38:27 PM PST 23	199103219 ps
T23	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2093801089	Dec 20 12:37:21 PM PST 23	Dec 20 12:38:27 PM PST 23	62446185 ps
T71	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2535687854	Dec 20 12:37:16 PM PST 23	Dec 20 12:38:13 PM PST 23	79495776 ps
T44	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2336775676	Dec 20 12:36:39 PM PST 23	Dec 20 12:36:53 PM PST 23	70658070 ps
T60	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3952822943	Dec 20 12:36:36 PM PST 23	Dec 20 12:36:47 PM PST 23	68538194 ps
T24	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.1541006495	Dec 20 12:33:15 PM PST 23	Dec 20 12:34:06 PM PST 23	332683313 ps
T25	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.2891857976	Dec 20 12:37:41 PM PST 23	Dec 20 12:38:59 PM PST 23	36978426 ps
T17	/workspace/coverage/cover_reg_top/33.kmac_intr_test.538506818	Dec 20 12:37:03 PM PST 23	Dec 20 12:37:44 PM PST 23	40287638 ps
T74	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.4116493741	Dec 20 12:36:56 PM PST 23	Dec 20 12:37:34 PM PST 23	31419616 ps
T76	/workspace/coverage/cover_reg_top/10.kmac_intr_test.3986382148	Dec 20 12:37:18 PM PST 23	Dec 20 12:38:15 PM PST 23	26369167 ps
T84	/workspace/coverage/cover_reg_top/47.kmac_intr_test.2149480697	Dec 20 12:37:17 PM PST 23	Dec 20 12:38:14 PM PST 23	22360051 ps
T61	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1963639607	Dec 20 12:37:01 PM PST 23	Dec 20 12:37:42 PM PST 23	422007211 ps
T26	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2454874758	Dec 20 12:37:27 PM PST 23	Dec 20 12:38:43 PM PST 23	120178824 ps
T27	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.1524065595	Dec 20 12:37:17 PM PST 23	Dec 20 12:38:13 PM PST 23	50028737 ps
T62	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1841971626	Dec 20 12:32:58 PM PST 23	Dec 20 12:33:50 PM PST 23	173807111 ps
T90	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3536938080	Dec 20 12:37:05 PM PST 23	Dec 20 12:37:46 PM PST 23	38803573 ps
T77	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1127941375	Dec 20 12:37:03 PM PST 23	Dec 20 12:37:44 PM PST 23	34810249 ps
T75	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.1669441215	Dec 20 12:36:55 PM PST 23	Dec 20 12:37:31 PM PST 23	113749778 ps
T63	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2625471840	Dec 20 12:36:59 PM PST 23	Dec 20 12:37:39 PM PST 23	511669657 ps
T28	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.3589469590	Dec 20 12:37:09 PM PST 23	Dec 20 12:37:53 PM PST 23	33578206 ps
T68	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3472745163	Dec 20 12:37:15 PM PST 23	Dec 20 12:38:11 PM PST 23	156006711 ps
T91	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.345376810	Dec 20 12:36:42 PM PST 23	Dec 20 12:37:02 PM PST 23	16947953 ps
T38	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3964959068	Dec 20 12:37:22 PM PST 23	Dec 20 12:38:31 PM PST 23	109268980 ps
T29	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1861830459	Dec 20 12:36:36 PM PST 23	Dec 20 12:36:49 PM PST 23	88498603 ps
T92	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2387709337	Dec 20 12:37:23 PM PST 23	Dec 20 12:38:36 PM PST 23	345560249 ps
T39	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2408370890	Dec 20 12:36:34 PM PST 23	Dec 20 12:36:47 PM PST 23	1202600632 ps
T85	/workspace/coverage/cover_reg_top/46.kmac_intr_test.935575936	Dec 20 12:37:08 PM PST 23	Dec 20 12:37:51 PM PST 23	22474406 ps
T93	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2118099099	Dec 20 12:37:18 PM PST 23	Dec 20 12:38:17 PM PST 23	73220114 ps
T94	/workspace/coverage/cover_reg_top/37.kmac_intr_test.118702181	Dec 20 12:36:29 PM PST 23	Dec 20 12:36:35 PM PST 23	16945749 ps
T30	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.890737842	Dec 20 12:36:25 PM PST 23	Dec 20 12:36:28 PM PST 23	19868115 ps
T95	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3695739049	Dec 20 12:32:57 PM PST 23	Dec 20 12:33:50 PM PST 23	123810052 ps
T34	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.4132830605	Dec 20 12:36:44 PM PST 23	Dec 20 12:37:11 PM PST 23	207396421 ps
T88	/workspace/coverage/cover_reg_top/18.kmac_intr_test.3050761789	Dec 20 12:37:21 PM PST 23	Dec 20 12:38:26 PM PST 23	49573045 ps
T35	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.3093139614	Dec 20 12:37:23 PM PST 23	Dec 20 12:38:30 PM PST 23	186563803 ps
T96	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3397791779	Dec 20 12:36:24 PM PST 23	Dec 20 12:36:28 PM PST 23	194522549 ps
T97	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1648314977	Dec 20 12:36:37 PM PST 23	Dec 20 12:36:51 PM PST 23	46665925 ps
T98	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.749660234	Dec 20 12:33:01 PM PST 23	Dec 20 12:33:52 PM PST 23	74834141 ps
T64	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2352337877	Dec 20 12:33:00 PM PST 23	Dec 20 12:33:52 PM PST 23	171155803 ps
T99	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2671411664	Dec 20 12:37:31 PM PST 23	Dec 20 12:38:50 PM PST 23	198629330 ps
T67	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2320791497	Dec 20 12:36:27 PM PST 23	Dec 20 12:36:30 PM PST 23	37765614 ps
T100	/workspace/coverage/cover_reg_top/1.kmac_intr_test.2905177088	Dec 20 12:33:01 PM PST 23	Dec 20 12:33:51 PM PST 23	47253426 ps
T80	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.381413049	Dec 20 12:32:50 PM PST 23	Dec 20 12:33:40 PM PST 23	75421521 ps
T101	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.289747953	Dec 20 12:36:35 PM PST 23	Dec 20 12:36:44 PM PST 23	27791333 ps
T102	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.307654989	Dec 20 12:33:03 PM PST 23	Dec 20 12:33:53 PM PST 23	87160304 ps
T40	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2366921054	Dec 20 12:33:19 PM PST 23	Dec 20 12:34:10 PM PST 23	675014893 ps
T86	/workspace/coverage/cover_reg_top/31.kmac_intr_test.23392159	Dec 20 12:37:00 PM PST 23	Dec 20 12:37:39 PM PST 23	107880128 ps
T103	/workspace/coverage/cover_reg_top/24.kmac_intr_test.1554600448	Dec 20 12:37:30 PM PST 23	Dec 20 12:38:42 PM PST 23	91271463 ps
T104	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.304044302	Dec 20 12:37:14 PM PST 23	Dec 20 12:38:05 PM PST 23	196592631 ps
T87	/workspace/coverage/cover_reg_top/39.kmac_intr_test.2598193493	Dec 20 12:36:43 PM PST 23	Dec 20 12:37:08 PM PST 23	54608720 ps
T105	/workspace/coverage/cover_reg_top/41.kmac_intr_test.885115247	Dec 20 12:36:54 PM PST 23	Dec 20 12:37:30 PM PST 23	26161236 ps
T36	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.569687700	Dec 20 12:33:15 PM PST 23	Dec 20 12:34:04 PM PST 23	132640202 ps
T106	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.2812730616	Dec 20 12:36:42 PM PST 23	Dec 20 12:37:00 PM PST 23	168595159 ps
T107	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2697787221	Dec 20 12:33:07 PM PST 23	Dec 20 12:33:59 PM PST 23	218002096 ps
T108	/workspace/coverage/cover_reg_top/45.kmac_intr_test.701005764	Dec 20 12:36:52 PM PST 23	Dec 20 12:37:27 PM PST 23	38608840 ps
T109	/workspace/coverage/cover_reg_top/11.kmac_intr_test.3377110729	Dec 20 12:37:08 PM PST 23	Dec 20 12:37:51 PM PST 23	29039376 ps
T72	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3745515250	Dec 20 12:36:56 PM PST 23	Dec 20 12:37:42 PM PST 23	381167080 ps
T45	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1873492143	Dec 20 12:33:04 PM PST 23	Dec 20 12:33:55 PM PST 23	18533853 ps
T46	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2478556062	Dec 20 12:36:38 PM PST 23	Dec 20 12:36:52 PM PST 23	52660463 ps
T47	/workspace/coverage/cover_reg_top/40.kmac_intr_test.744766498	Dec 20 12:37:03 PM PST 23	Dec 20 12:37:43 PM PST 23	26800946 ps
T48	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1781651530	Dec 20 12:37:16 PM PST 23	Dec 20 12:38:11 PM PST 23	10873327 ps
T49	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.71073699	Dec 20 12:36:43 PM PST 23	Dec 20 12:37:08 PM PST 23	27193886 ps
T50	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1254514254	Dec 20 12:37:14 PM PST 23	Dec 20 12:38:07 PM PST 23	425245595 ps
T51	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.866062205	Dec 20 12:33:04 PM PST 23	Dec 20 12:33:58 PM PST 23	87837292 ps
T52	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3164169144	Dec 20 12:33:10 PM PST 23	Dec 20 12:34:01 PM PST 23	31807725 ps
T53	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1444955274	Dec 20 12:37:10 PM PST 23	Dec 20 12:37:56 PM PST 23	106236590 ps
T54	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1184312266	Dec 20 12:32:59 PM PST 23	Dec 20 12:33:53 PM PST 23	408049968 ps
T110	/workspace/coverage/cover_reg_top/28.kmac_intr_test.2560868566	Dec 20 12:37:05 PM PST 23	Dec 20 12:37:46 PM PST 23	84754311 ps
T111	/workspace/coverage/cover_reg_top/19.kmac_intr_test.3799853199	Dec 20 12:37:10 PM PST 23	Dec 20 12:37:54 PM PST 23	13665753 ps
T112	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3384873701	Dec 20 12:32:51 PM PST 23	Dec 20 12:33:40 PM PST 23	62651475 ps
T113	/workspace/coverage/cover_reg_top/14.kmac_intr_test.3341756151	Dec 20 12:37:29 PM PST 23	Dec 20 12:38:43 PM PST 23	12894053 ps
T114	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.1994581554	Dec 20 12:36:27 PM PST 23	Dec 20 12:36:29 PM PST 23	27157767 ps
T115	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3037987003	Dec 20 12:32:59 PM PST 23	Dec 20 12:33:57 PM PST 23	169474026 ps
T116	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.1221003598	Dec 20 12:36:26 PM PST 23	Dec 20 12:36:30 PM PST 23	103479915 ps
T117	/workspace/coverage/cover_reg_top/0.kmac_intr_test.2450519112	Dec 20 12:32:53 PM PST 23	Dec 20 12:33:41 PM PST 23	16848938 ps
T118	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.4091696078	Dec 20 12:37:07 PM PST 23	Dec 20 12:37:50 PM PST 23	33034003 ps
T119	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.525734965	Dec 20 12:32:49 PM PST 23	Dec 20 12:33:57 PM PST 23	1052349689 ps
T120	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.68571746	Dec 20 12:37:04 PM PST 23	Dec 20 12:37:45 PM PST 23	29620712 ps
T121	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.155445570	Dec 20 12:33:12 PM PST 23	Dec 20 12:34:01 PM PST 23	25839087 ps
T122	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3891010738	Dec 20 12:37:05 PM PST 23	Dec 20 12:37:46 PM PST 23	48024799 ps
T123	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2145111538	Dec 20 12:36:48 PM PST 23	Dec 20 12:37:39 PM PST 23	4506214187 ps
T124	/workspace/coverage/cover_reg_top/7.kmac_intr_test.1456502825	Dec 20 12:36:23 PM PST 23	Dec 20 12:36:25 PM PST 23	22444360 ps
T125	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1864563841	Dec 20 12:37:07 PM PST 23	Dec 20 12:37:50 PM PST 23	605662656 ps
T126	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2008942353	Dec 20 12:37:05 PM PST 23	Dec 20 12:37:47 PM PST 23	17721083 ps
T127	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3439441059	Dec 20 12:33:21 PM PST 23	Dec 20 12:34:27 PM PST 23	2111535705 ps
T128	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.1025903844	Dec 20 12:37:17 PM PST 23	Dec 20 12:38:15 PM PST 23	100216979 ps
T129	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3028361779	Dec 20 12:36:40 PM PST 23	Dec 20 12:36:57 PM PST 23	61038309 ps
T130	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.648609532	Dec 20 12:33:12 PM PST 23	Dec 20 12:34:02 PM PST 23	64875511 ps
T131	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.2108168042	Dec 20 12:33:01 PM PST 23	Dec 20 12:33:53 PM PST 23	151830448 ps
T132	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2731902940	Dec 20 12:37:21 PM PST 23	Dec 20 12:38:24 PM PST 23	95339014 ps
T133	/workspace/coverage/cover_reg_top/9.kmac_intr_test.79933955	Dec 20 12:36:39 PM PST 23	Dec 20 12:36:53 PM PST 23	122742572 ps
T134	/workspace/coverage/cover_reg_top/38.kmac_intr_test.1116007189	Dec 20 12:36:54 PM PST 23	Dec 20 12:37:31 PM PST 23	58809276 ps
T65	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1441447648	Dec 20 12:33:14 PM PST 23	Dec 20 12:34:03 PM PST 23	101381683 ps
T70	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3929882152	Dec 20 12:37:06 PM PST 23	Dec 20 12:37:50 PM PST 23	54038008 ps
T135	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3212631258	Dec 20 12:33:08 PM PST 23	Dec 20 12:33:59 PM PST 23	21038718 ps
T136	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.788371304	Dec 20 12:37:09 PM PST 23	Dec 20 12:37:53 PM PST 23	33953371 ps
T137	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.1762392480	Dec 20 12:36:25 PM PST 23	Dec 20 12:36:27 PM PST 23	64247977 ps
T138	/workspace/coverage/cover_reg_top/26.kmac_intr_test.352443458	Dec 20 12:37:23 PM PST 23	Dec 20 12:38:34 PM PST 23	22737727 ps
T139	/workspace/coverage/cover_reg_top/6.kmac_intr_test.2147308082	Dec 20 12:36:32 PM PST 23	Dec 20 12:36:39 PM PST 23	16627183 ps
T140	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.426450314	Dec 20 12:32:56 PM PST 23	Dec 20 12:33:46 PM PST 23	39596790 ps
T141	/workspace/coverage/cover_reg_top/15.kmac_intr_test.1499101428	Dec 20 12:36:43 PM PST 23	Dec 20 12:37:06 PM PST 23	49498580 ps
T142	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1332500965	Dec 20 12:37:11 PM PST 23	Dec 20 12:37:57 PM PST 23	62187453 ps
T143	/workspace/coverage/cover_reg_top/8.kmac_intr_test.2856145691	Dec 20 12:36:50 PM PST 23	Dec 20 12:37:23 PM PST 23	13711235 ps
T144	/workspace/coverage/cover_reg_top/44.kmac_intr_test.54940551	Dec 20 12:36:47 PM PST 23	Dec 20 12:37:17 PM PST 23	87362289 ps
T145	/workspace/coverage/cover_reg_top/2.kmac_intr_test.3733169843	Dec 20 12:33:08 PM PST 23	Dec 20 12:33:59 PM PST 23	50133427 ps
T146	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3950650582	Dec 20 12:33:15 PM PST 23	Dec 20 12:34:04 PM PST 23	190035062 ps
T147	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.1062206432	Dec 20 12:33:12 PM PST 23	Dec 20 12:34:02 PM PST 23	22363180 ps
T148	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.1304812613	Dec 20 12:36:28 PM PST 23	Dec 20 12:36:34 PM PST 23	22073701 ps
T149	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3304754766	Dec 20 12:36:40 PM PST 23	Dec 20 12:36:55 PM PST 23	31825961 ps
T55	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3563709254	Dec 20 12:33:09 PM PST 23	Dec 20 12:34:00 PM PST 23	19201371 ps
T150	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.1570953052	Dec 20 12:38:44 PM PST 23	Dec 20 12:39:45 PM PST 23	19995537 ps
T151	/workspace/coverage/cover_reg_top/36.kmac_intr_test.102335570	Dec 20 12:36:39 PM PST 23	Dec 20 12:36:54 PM PST 23	33437896 ps
T152	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3950794099	Dec 20 12:36:36 PM PST 23	Dec 20 12:36:48 PM PST 23	12536582 ps
T153	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.3381592362	Dec 20 12:36:51 PM PST 23	Dec 20 12:37:26 PM PST 23	31605540 ps
T154	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3859309595	Dec 20 12:37:20 PM PST 23	Dec 20 12:38:26 PM PST 23	115688180 ps
T82	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3382672853	Dec 20 12:36:25 PM PST 23	Dec 20 12:36:31 PM PST 23	586717616 ps
T155	/workspace/coverage/cover_reg_top/30.kmac_intr_test.3534559194	Dec 20 12:36:39 PM PST 23	Dec 20 12:36:54 PM PST 23	85561312 ps
T156	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.1755046206	Dec 20 12:37:06 PM PST 23	Dec 20 12:37:51 PM PST 23	199172352 ps
T73	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2840120087	Dec 20 12:36:38 PM PST 23	Dec 20 12:36:52 PM PST 23	147822129 ps
T157	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2938163038	Dec 20 12:36:33 PM PST 23	Dec 20 12:36:40 PM PST 23	54305468 ps
T158	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.225487696	Dec 20 12:37:07 PM PST 23	Dec 20 12:37:48 PM PST 23	112022306 ps
T159	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.2072232423	Dec 20 12:36:32 PM PST 23	Dec 20 12:36:39 PM PST 23	1014603672 ps
T160	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3568365258	Dec 20 12:32:53 PM PST 23	Dec 20 12:33:41 PM PST 23	41517537 ps
T9	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2647288827	Dec 20 12:37:14 PM PST 23	Dec 20 12:38:07 PM PST 23	37868954 ps
T66	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3247319532	Dec 20 12:36:27 PM PST 23	Dec 20 12:36:32 PM PST 23	419221372 ps
T161	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1450647648	Dec 20 12:37:21 PM PST 23	Dec 20 12:38:26 PM PST 23	32817750 ps
T162	/workspace/coverage/cover_reg_top/34.kmac_intr_test.1132435477	Dec 20 12:36:33 PM PST 23	Dec 20 12:36:40 PM PST 23	16886164 ps
T56	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.604887791	Dec 20 12:32:55 PM PST 23	Dec 20 12:33:45 PM PST 23	32271364 ps
T163	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2241429282	Dec 20 12:36:36 PM PST 23	Dec 20 12:36:48 PM PST 23	319494623 ps
T164	/workspace/coverage/cover_reg_top/35.kmac_intr_test.2811786242	Dec 20 12:36:36 PM PST 23	Dec 20 12:36:48 PM PST 23	22839308 ps
T10	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.61917503	Dec 20 12:36:44 PM PST 23	Dec 20 12:37:09 PM PST 23	34238550 ps
T57	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.4018989360	Dec 20 12:32:57 PM PST 23	Dec 20 12:33:48 PM PST 23	45929664 ps
T165	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1707485108	Dec 20 12:36:48 PM PST 23	Dec 20 12:37:19 PM PST 23	94687969 ps
T166	/workspace/coverage/cover_reg_top/16.kmac_intr_test.2949478502	Dec 20 12:36:42 PM PST 23	Dec 20 12:37:02 PM PST 23	14225357 ps
T167	/workspace/coverage/cover_reg_top/17.kmac_intr_test.3980471312	Dec 20 12:37:18 PM PST 23	Dec 20 12:38:15 PM PST 23	14070049 ps
T168	/workspace/coverage/cover_reg_top/20.kmac_intr_test.4028380479	Dec 20 12:37:09 PM PST 23	Dec 20 12:37:52 PM PST 23	15026076 ps
T81	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1553561014	Dec 20 12:37:17 PM PST 23	Dec 20 12:38:24 PM PST 23	229334283 ps
T169	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.456650702	Dec 20 12:36:24 PM PST 23	Dec 20 12:36:26 PM PST 23	34982894 ps
T170	/workspace/coverage/cover_reg_top/3.kmac_intr_test.2498182461	Dec 20 12:36:34 PM PST 23	Dec 20 12:36:42 PM PST 23	50259275 ps
T171	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.2392185965	Dec 20 12:37:18 PM PST 23	Dec 20 12:38:16 PM PST 23	36821328 ps
T172	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.874050865	Dec 20 12:33:00 PM PST 23	Dec 20 12:33:50 PM PST 23	15215127 ps
T173	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.3696328435	Dec 20 12:36:22 PM PST 23	Dec 20 12:36:23 PM PST 23	33088671 ps
T174	/workspace/coverage/cover_reg_top/42.kmac_intr_test.346619096	Dec 20 12:36:43 PM PST 23	Dec 20 12:37:08 PM PST 23	44974113 ps
T175	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1801333064	Dec 20 12:36:33 PM PST 23	Dec 20 12:36:41 PM PST 23	63000786 ps
T13	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1490607606	Dec 20 12:37:17 PM PST 23	Dec 20 12:38:16 PM PST 23	187167615 ps
T176	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3901789146	Dec 20 12:36:26 PM PST 23	Dec 20 12:36:29 PM PST 23	78431849 ps
T177	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1233416416	Dec 20 12:36:32 PM PST 23	Dec 20 12:36:40 PM PST 23	37104364 ps
T178	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3049388355	Dec 20 12:36:54 PM PST 23	Dec 20 12:37:32 PM PST 23	213029238 ps
T179	/workspace/coverage/cover_reg_top/43.kmac_intr_test.1464133286	Dec 20 12:36:41 PM PST 23	Dec 20 12:36:58 PM PST 23	33128870 ps
T180	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1031234511	Dec 20 12:36:25 PM PST 23	Dec 20 12:36:28 PM PST 23	102473155 ps
T181	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.661751935	Dec 20 12:36:27 PM PST 23	Dec 20 12:36:32 PM PST 23	411522382 ps
T182	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.4150004006	Dec 20 12:37:24 PM PST 23	Dec 20 12:38:37 PM PST 23	182107874 ps
T183	/workspace/coverage/cover_reg_top/25.kmac_intr_test.488307969	Dec 20 12:37:13 PM PST 23	Dec 20 12:38:01 PM PST 23	14383783 ps
T184	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.508569933	Dec 20 12:36:49 PM PST 23	Dec 20 12:37:22 PM PST 23	173744095 ps
T185	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2030488925	Dec 20 12:37:07 PM PST 23	Dec 20 12:37:49 PM PST 23	73124164 ps
T186	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3095893192	Dec 20 12:37:05 PM PST 23	Dec 20 12:37:48 PM PST 23	173641412 ps
T69	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3383601999	Dec 20 12:36:35 PM PST 23	Dec 20 12:36:47 PM PST 23	94393327 ps
T187	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.2548760577	Dec 20 12:37:08 PM PST 23	Dec 20 12:37:51 PM PST 23	106338871 ps
T78	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.249372889	Dec 20 12:36:50 PM PST 23	Dec 20 12:37:25 PM PST 23	42856022 ps
T188	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.2822954160	Dec 20 12:36:49 PM PST 23	Dec 20 12:37:30 PM PST 23	315715905 ps
T189	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1921631474	Dec 20 12:37:10 PM PST 23	Dec 20 12:37:55 PM PST 23	75823506 ps
T190	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1380034364	Dec 20 12:37:08 PM PST 23	Dec 20 12:37:51 PM PST 23	43480096 ps
T191	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.29057040	Dec 20 12:33:11 PM PST 23	Dec 20 12:34:01 PM PST 23	40016509 ps
T192	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.451774927	Dec 20 12:32:57 PM PST 23	Dec 20 12:33:47 PM PST 23	69407316 ps
T193	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1591628936	Dec 20 12:36:46 PM PST 23	Dec 20 12:37:14 PM PST 23	62824601 ps
T194	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.2206931064	Dec 20 12:37:16 PM PST 23	Dec 20 12:38:11 PM PST 23	91706997 ps
T195	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2892993988	Dec 20 12:36:45 PM PST 23	Dec 20 12:37:12 PM PST 23	63149774 ps
T196	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2350674481	Dec 20 12:37:12 PM PST 23	Dec 20 12:38:02 PM PST 23	181006005 ps
T197	/workspace/coverage/cover_reg_top/5.kmac_intr_test.2881188811	Dec 20 12:36:27 PM PST 23	Dec 20 12:36:30 PM PST 23	40805738 ps
T83	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.838113736	Dec 20 12:37:00 PM PST 23	Dec 20 12:37:42 PM PST 23	183554462 ps
T198	/workspace/coverage/cover_reg_top/22.kmac_intr_test.1266100669	Dec 20 12:37:13 PM PST 23	Dec 20 12:38:03 PM PST 23	15908702 ps
T199	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3896310651	Dec 20 12:36:30 PM PST 23	Dec 20 12:36:46 PM PST 23	456992388 ps
T200	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1630885376	Dec 20 12:36:43 PM PST 23	Dec 20 12:37:09 PM PST 23	103459504 ps
T201	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3251033287	Dec 20 12:36:59 PM PST 23	Dec 20 12:37:39 PM PST 23	107394365 ps
T202	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2254826045	Dec 20 12:36:38 PM PST 23	Dec 20 12:37:08 PM PST 23	27237526 ps
T203	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2337981136	Dec 20 12:37:16 PM PST 23	Dec 20 12:38:10 PM PST 23	16120840 ps
T204	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2324970130	Dec 20 12:36:44 PM PST 23	Dec 20 12:37:12 PM PST 23	185700248 ps
T205	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.2715660119	Dec 20 12:33:04 PM PST 23	Dec 20 12:33:54 PM PST 23	46521284 ps
T11	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2266522437	Dec 20 12:37:27 PM PST 23	Dec 20 12:38:43 PM PST 23	75532901 ps
T206	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2111474969	Dec 20 12:37:20 PM PST 23	Dec 20 12:38:20 PM PST 23	46977906 ps
T207	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.2276666283	Dec 20 12:36:29 PM PST 23	Dec 20 12:36:34 PM PST 23	22900150 ps
T208	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.861081619	Dec 20 12:37:18 PM PST 23	Dec 20 12:38:16 PM PST 23	80280578 ps
T209	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3742687665	Dec 20 12:36:30 PM PST 23	Dec 20 12:36:35 PM PST 23	39772090 ps
T79	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3225842129	Dec 20 12:36:44 PM PST 23	Dec 20 12:37:14 PM PST 23	343879283 ps
T210	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.4271927801	Dec 20 12:32:54 PM PST 23	Dec 20 12:33:44 PM PST 23	112903091 ps
T12	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2921729098	Dec 20 12:37:01 PM PST 23	Dec 20 12:37:43 PM PST 23	209706154 ps
T211	/workspace/coverage/cover_reg_top/12.kmac_intr_test.1780789685	Dec 20 12:37:10 PM PST 23	Dec 20 12:37:54 PM PST 23	16304845 ps
T212	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3153915181	Dec 20 12:37:31 PM PST 23	Dec 20 12:38:46 PM PST 23	57126409 ps
T213	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3558552422	Dec 20 12:36:25 PM PST 23	Dec 20 12:36:28 PM PST 23	137681890 ps
T214	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1032826427	Dec 20 12:37:23 PM PST 23	Dec 20 12:38:34 PM PST 23	452665450 ps
T215	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1300981256	Dec 20 12:37:00 PM PST 23	Dec 20 12:37:39 PM PST 23	345898368 ps

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1551216574
Short name	T1
Test name
Test status
Simulation time	207401268 ps
CPU time	2.87 seconds
Started	Dec 20 12:33:13 PM PST 23
Finished	Dec 20 12:34:04 PM PST 23
Peak memory	217780 kb
Host	smart-391bef1a-bd48-453d-a28a-08db8d689a67
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551216574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.15512 16574 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.1541006495
Short name	T24
Test name
Test status
Simulation time	332683313 ps
CPU time	3.26 seconds
Started	Dec 20 12:33:15 PM PST 23
Finished	Dec 20 12:34:06 PM PST 23
Peak memory	217724 kb
Host	smart-9fb70686-fb3a-410f-9625-51159e61642e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541006495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1541006495 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.1821501331
Short name	T16
Test name
Test status
Simulation time	39278370 ps
CPU time	0.75 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:33 PM PST 23
Peak memory	217452 kb
Host	smart-39031e33-46a0-4f22-8952-27d4e30f18f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821501331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1821501331 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2348774984
Short name	T5
Test name
Test status
Simulation time	163519378 ps
CPU time	1.22 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:52 PM PST 23
Peak memory	218236 kb
Host	smart-b853b40f-b58b-4e0d-8544-9ad9b0178ea5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348774984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg _errors.2348774984 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2352337877
Short name	T64
Test name
Test status
Simulation time	171155803 ps
CPU time	2.44 seconds
Started	Dec 20 12:33:00 PM PST 23
Finished	Dec 20 12:33:52 PM PST 23
Peak memory	221124 kb
Host	smart-3d7e0b8d-4654-49ed-afd0-4b5136432f34
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352337877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.2352337877 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3075451335
Short name	T8
Test name
Test status
Simulation time	199103219 ps
CPU time	1.62 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:27 PM PST 23
Peak memory	217124 kb
Host	smart-0892232a-8e77-4632-b7ae-2d00993f3c70
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075451335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.3075451335 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.4018989360
Short name	T57
Test name
Test status
Simulation time	45929664 ps
CPU time	1.59 seconds
Started	Dec 20 12:32:57 PM PST 23
Finished	Dec 20 12:33:48 PM PST 23
Peak memory	217704 kb
Host	smart-852af1b7-28e7-47b1-8005-2cb7d037e2c4
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018989360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.4018989360 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1781651530
Short name	T48
Test name
Test status
Simulation time	10873327 ps
CPU time	0.77 seconds
Started	Dec 20 12:37:16 PM PST 23
Finished	Dec 20 12:38:11 PM PST 23
Peak memory	216800 kb
Host	smart-6c589061-5c6a-47b7-8ea6-82e817e66b69
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781651530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1781651530 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.1920614113
Short name	T6
Test name
Test status
Simulation time	149383214 ps
CPU time	2.18 seconds
Started	Dec 20 12:36:43 PM PST 23
Finished	Dec 20 12:37:16 PM PST 23
Peak memory	217976 kb
Host	smart-d3c121fa-e013-44bf-96a8-f157ac97f6bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920614113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1920614113 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.838113736
Short name	T83
Test name
Test status
Simulation time	183554462 ps
CPU time	3.76 seconds
Started	Dec 20 12:37:00 PM PST 23
Finished	Dec 20 12:37:42 PM PST 23
Peak memory	216872 kb
Host	smart-d422d189-8f43-48ea-bfb2-532fd19757fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838113736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.83811 3736 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1441447648
Short name	T65
Test name
Test status
Simulation time	101381683 ps
CPU time	1.28 seconds
Started	Dec 20 12:33:14 PM PST 23
Finished	Dec 20 12:34:03 PM PST 23
Peak memory	218348 kb
Host	smart-7488ea61-6fe0-4f4d-880e-3049387cc97b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441447648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_ errors.1441447648 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.2474464331
Short name	T21
Test name
Test status
Simulation time	40536882 ps
CPU time	1.59 seconds
Started	Dec 20 12:36:43 PM PST 23
Finished	Dec 20 12:37:07 PM PST 23
Peak memory	217780 kb
Host	smart-fe533ab0-8980-4ef4-880b-f1272690c139
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474464331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2474464331 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.61917503
Short name	T10
Test name
Test status
Simulation time	34238550 ps
CPU time	1.86 seconds
Started	Dec 20 12:36:44 PM PST 23
Finished	Dec 20 12:37:09 PM PST 23
Peak memory	225324 kb
Host	smart-7d9796e6-13f1-4821-b534-35785aef4b28
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61917503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_ shadow_reg_errors_with_csr_rw.61917503 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2535687854
Short name	T71
Test name
Test status
Simulation time	79495776 ps
CPU time	2.57 seconds
Started	Dec 20 12:37:16 PM PST 23
Finished	Dec 20 12:38:13 PM PST 23
Peak memory	217420 kb
Host	smart-40ba2d0c-5121-4986-a9cb-2b947fcfc17e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535687854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2535 687854 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3225842129
Short name	T79
Test name
Test status
Simulation time	343879283 ps
CPU time	5.1 seconds
Started	Dec 20 12:36:44 PM PST 23
Finished	Dec 20 12:37:14 PM PST 23
Peak memory	217332 kb
Host	smart-50477c17-92e0-4506-a8da-f81316531208
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225842129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3225 842129 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2454874758
Short name	T26
Test name
Test status
Simulation time	120178824 ps
CPU time	2.46 seconds
Started	Dec 20 12:37:27 PM PST 23
Finished	Dec 20 12:38:43 PM PST 23
Peak memory	222536 kb
Host	smart-f1e3a6d1-b8e8-4744-95aa-f0ee0f257264
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454874758 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.2454874758 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.249372889
Short name	T78
Test name
Test status
Simulation time	42856022 ps
CPU time	2.63 seconds
Started	Dec 20 12:36:50 PM PST 23
Finished	Dec 20 12:37:25 PM PST 23
Peak memory	217948 kb
Host	smart-6eabb1db-a0a5-438b-b927-cf9789d27ab3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249372889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.249372889 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1490607606
Short name	T13
Test name
Test status
Simulation time	187167615 ps
CPU time	2.43 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:16 PM PST 23
Peak memory	221464 kb
Host	smart-007379d6-c462-4fce-ab02-bebfa6b2b4b4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490607606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.1490607606 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3037987003
Short name	T115
Test name
Test status
Simulation time	169474026 ps
CPU time	9.1 seconds
Started	Dec 20 12:32:59 PM PST 23
Finished	Dec 20 12:33:57 PM PST 23
Peak memory	217788 kb
Host	smart-a063f8e1-42d4-4b0e-ba2c-bc8085a73c58
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037987003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3037987 003 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3439441059
Short name	T127
Test name
Test status
Simulation time	2111535705 ps
CPU time	21.13 seconds
Started	Dec 20 12:33:21 PM PST 23
Finished	Dec 20 12:34:27 PM PST 23
Peak memory	216972 kb
Host	smart-6b661193-d145-4aec-997a-cbfb9736c7f8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439441059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3439441 059 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.29057040
Short name	T191
Test name
Test status
Simulation time	40016509 ps
CPU time	0.96 seconds
Started	Dec 20 12:33:11 PM PST 23
Finished	Dec 20 12:34:01 PM PST 23
Peak memory	216628 kb
Host	smart-ad308df5-b7b5-4188-83c0-80bd67f91ef3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29057040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.29057040 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3164169144
Short name	T52
Test name
Test status
Simulation time	31807725 ps
CPU time	1.87 seconds
Started	Dec 20 12:33:10 PM PST 23
Finished	Dec 20 12:34:01 PM PST 23
Peak memory	222376 kb
Host	smart-7a97fd1d-02de-48de-aca7-9251489081f5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164169144 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3164169144 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.1062206432
Short name	T147
Test name
Test status
Simulation time	22363180 ps
CPU time	0.93 seconds
Started	Dec 20 12:33:12 PM PST 23
Finished	Dec 20 12:34:02 PM PST 23
Peak memory	216716 kb
Host	smart-1f9945fb-2762-4619-8da2-7193f872f938
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062206432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.1062206432 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.2450519112
Short name	T117
Test name
Test status
Simulation time	16848938 ps
CPU time	0.81 seconds
Started	Dec 20 12:32:53 PM PST 23
Finished	Dec 20 12:33:41 PM PST 23
Peak memory	217452 kb
Host	smart-50774bde-b1ed-4e4b-a97f-af1d5614e4f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450519112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2450519112 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.604887791
Short name	T56
Test name
Test status
Simulation time	32271364 ps
CPU time	1.23 seconds
Started	Dec 20 12:32:55 PM PST 23
Finished	Dec 20 12:33:45 PM PST 23
Peak memory	217712 kb
Host	smart-b1d8f9ff-1f49-44d1-8e8f-9fd897386985
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604887791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial _access.604887791 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.2157559433
Short name	T89
Test name
Test status
Simulation time	11785241 ps
CPU time	0.75 seconds
Started	Dec 20 12:32:55 PM PST 23
Finished	Dec 20 12:33:44 PM PST 23
Peak memory	217452 kb
Host	smart-3ec3cca4-74e9-443a-9daa-8723cb42d8c0
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157559433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2157559433 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3950650582
Short name	T146
Test name
Test status
Simulation time	190035062 ps
CPU time	1.65 seconds
Started	Dec 20 12:33:15 PM PST 23
Finished	Dec 20 12:34:04 PM PST 23
Peak memory	216792 kb
Host	smart-9755efa7-d45d-4d09-9dc0-3567c0917b8a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950650582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.3950650582 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3748877149
Short name	T32
Test name
Test status
Simulation time	22213060 ps
CPU time	1.04 seconds
Started	Dec 20 12:32:53 PM PST 23
Finished	Dec 20 12:33:42 PM PST 23
Peak memory	217984 kb
Host	smart-6c9d80e3-abfe-41af-abe4-34c1ca2dc12d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748877149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.3748877149 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1841971626
Short name	T62
Test name
Test status
Simulation time	173807111 ps
CPU time	3.18 seconds
Started	Dec 20 12:32:58 PM PST 23
Finished	Dec 20 12:33:50 PM PST 23
Peak memory	225244 kb
Host	smart-9e1d6b57-1d90-4eaa-b77b-9bc356c137da
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841971626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac _shadow_reg_errors_with_csr_rw.1841971626 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1184312266
Short name	T54
Test name
Test status
Simulation time	408049968 ps
CPU time	5.13 seconds
Started	Dec 20 12:32:59 PM PST 23
Finished	Dec 20 12:33:53 PM PST 23
Peak memory	224788 kb
Host	smart-1c385050-8e83-4a39-97f3-fb49fbc7ebe2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184312266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.11843 12266 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.4196829607
Short name	T37
Test name
Test status
Simulation time	880236415 ps
CPU time	11.36 seconds
Started	Dec 20 12:32:55 PM PST 23
Finished	Dec 20 12:33:54 PM PST 23
Peak memory	217796 kb
Host	smart-7ca1c2cd-e0c4-420d-8692-cd6a181b6779
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196829607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.4196829 607 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2049348342
Short name	T3
Test name
Test status
Simulation time	1084467650 ps
CPU time	20.69 seconds
Started	Dec 20 12:33:16 PM PST 23
Finished	Dec 20 12:34:24 PM PST 23
Peak memory	217860 kb
Host	smart-eca4fdf2-720a-4d31-ac12-9a65cc1e6fd1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049348342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2049348 342 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.307654989
Short name	T102
Test name
Test status
Simulation time	87160304 ps
CPU time	0.99 seconds
Started	Dec 20 12:33:03 PM PST 23
Finished	Dec 20 12:33:53 PM PST 23
Peak memory	217268 kb
Host	smart-4ae28c1b-d0c2-48dd-98c7-34ab8bdec40f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307654989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.30765498 9 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.749660234
Short name	T98
Test name
Test status
Simulation time	74834141 ps
CPU time	1.56 seconds
Started	Dec 20 12:33:01 PM PST 23
Finished	Dec 20 12:33:52 PM PST 23
Peak memory	218668 kb
Host	smart-a73c6cd4-6260-41ad-bfe1-88e1ff16a5db
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749660234 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.749660234 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.1012169910
Short name	T59
Test name
Test status
Simulation time	44313809 ps
CPU time	0.93 seconds
Started	Dec 20 12:33:01 PM PST 23
Finished	Dec 20 12:33:52 PM PST 23
Peak memory	217468 kb
Host	smart-b5cbafb5-94b9-45c0-b695-4f97eef32bf8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012169910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1012169910 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.2905177088
Short name	T100
Test name
Test status
Simulation time	47253426 ps
CPU time	0.78 seconds
Started	Dec 20 12:33:01 PM PST 23
Finished	Dec 20 12:33:51 PM PST 23
Peak memory	216448 kb
Host	smart-8e46e8f9-5b7c-4675-8056-f80c08e8b995
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905177088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2905177088 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.874050865
Short name	T172
Test name
Test status
Simulation time	15215127 ps
CPU time	0.73 seconds
Started	Dec 20 12:33:00 PM PST 23
Finished	Dec 20 12:33:50 PM PST 23
Peak memory	217368 kb
Host	smart-4dca4244-05ad-4b6f-ab2f-dfb4fed9cb26
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874050865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.874050865 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.426450314
Short name	T140
Test name
Test status
Simulation time	39596790 ps
CPU time	2.19 seconds
Started	Dec 20 12:32:56 PM PST 23
Finished	Dec 20 12:33:46 PM PST 23
Peak memory	216872 kb
Host	smart-17a8cd57-f053-4f3c-ae66-0fef6373c05c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426450314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_ outstanding.426450314 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3695739049
Short name	T95
Test name
Test status
Simulation time	123810052 ps
CPU time	3.33 seconds
Started	Dec 20 12:32:57 PM PST 23
Finished	Dec 20 12:33:50 PM PST 23
Peak memory	221460 kb
Host	smart-c55514ec-f303-4b8a-bced-e621a8ac5f22
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695739049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac _shadow_reg_errors_with_csr_rw.3695739049 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.569687700
Short name	T36
Test name
Test status
Simulation time	132640202 ps
CPU time	1.59 seconds
Started	Dec 20 12:33:15 PM PST 23
Finished	Dec 20 12:34:04 PM PST 23
Peak memory	217832 kb
Host	smart-d86853a5-9429-4752-80d5-86182198f8ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569687700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.569687700 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2366921054
Short name	T40
Test name
Test status
Simulation time	675014893 ps
CPU time	4.32 seconds
Started	Dec 20 12:33:19 PM PST 23
Finished	Dec 20 12:34:10 PM PST 23
Peak memory	217868 kb
Host	smart-4324c8c3-acaf-4f8a-af66-3943b93697f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366921054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.23669 21054 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2008942353
Short name	T126
Test name
Test status
Simulation time	17721083 ps
CPU time	1.32 seconds
Started	Dec 20 12:37:05 PM PST 23
Finished	Dec 20 12:37:47 PM PST 23
Peak memory	220160 kb
Host	smart-e447b881-c9a0-40ee-89bd-4a59502c4d9f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008942353 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.2008942353 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.1302275080
Short name	T43
Test name
Test status
Simulation time	36787271 ps
CPU time	1.21 seconds
Started	Dec 20 12:36:56 PM PST 23
Finished	Dec 20 12:37:33 PM PST 23
Peak memory	217772 kb
Host	smart-fb48ff26-3f08-4474-b765-fec6ec4de861
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302275080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1302275080 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.3986382148
Short name	T76
Test name
Test status
Simulation time	26369167 ps
CPU time	0.79 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:15 PM PST 23
Peak memory	216736 kb
Host	smart-9c73ad2d-5e2e-4775-b5af-9725f6179cce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986382148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3986382148 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2731902940
Short name	T132
Test name
Test status
Simulation time	95339014 ps
CPU time	1.47 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:24 PM PST 23
Peak memory	217732 kb
Host	smart-963ea948-71fa-498e-a112-2a6cacaadbe9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731902940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.2731902940 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1591628936
Short name	T193
Test name
Test status
Simulation time	62824601 ps
CPU time	1.07 seconds
Started	Dec 20 12:36:46 PM PST 23
Finished	Dec 20 12:37:14 PM PST 23
Peak memory	225088 kb
Host	smart-0b2a2494-fb43-4fe7-aa7a-7061d04c3b8b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591628936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.1591628936 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.1524065595
Short name	T27
Test name
Test status
Simulation time	50028737 ps
CPU time	1.73 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:13 PM PST 23
Peak memory	217788 kb
Host	smart-2eea7302-68ed-484a-b8cc-4a2cb82dceb9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524065595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1524065595 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.3381592362
Short name	T153
Test name
Test status
Simulation time	31605540 ps
CPU time	1.16 seconds
Started	Dec 20 12:36:51 PM PST 23
Finished	Dec 20 12:37:26 PM PST 23
Peak memory	217024 kb
Host	smart-7b02c954-dafb-4cd4-8b94-781a51b4027a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381592362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3381592362 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.3377110729
Short name	T109
Test name
Test status
Simulation time	29039376 ps
CPU time	0.78 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:51 PM PST 23
Peak memory	216864 kb
Host	smart-0bf87364-48bb-449a-ba83-ccc41ea76574
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377110729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3377110729 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2671411664
Short name	T99
Test name
Test status
Simulation time	198629330 ps
CPU time	2.68 seconds
Started	Dec 20 12:37:31 PM PST 23
Finished	Dec 20 12:38:50 PM PST 23
Peak memory	217668 kb
Host	smart-cbff1742-1410-4d2c-a907-ea5ea2811b38
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671411664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs r_outstanding.2671411664 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.68571746
Short name	T120
Test name
Test status
Simulation time	29620712 ps
CPU time	1.04 seconds
Started	Dec 20 12:37:04 PM PST 23
Finished	Dec 20 12:37:45 PM PST 23
Peak memory	217020 kb
Host	smart-5daf0751-cf4a-4e5a-953a-e6943a71d41e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68571746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_e rrors.68571746 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1963639607
Short name	T61
Test name
Test status
Simulation time	422007211 ps
CPU time	2.77 seconds
Started	Dec 20 12:37:01 PM PST 23
Finished	Dec 20 12:37:42 PM PST 23
Peak memory	225244 kb
Host	smart-b3056fb4-0c6c-41ed-bd31-172b9330675f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963639607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.1963639607 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3536938080
Short name	T90
Test name
Test status
Simulation time	38803573 ps
CPU time	1.41 seconds
Started	Dec 20 12:37:05 PM PST 23
Finished	Dec 20 12:37:46 PM PST 23
Peak memory	219204 kb
Host	smart-648e964b-48bb-4a30-b896-ed3a95032736
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536938080 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.3536938080 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.1025903844
Short name	T128
Test name
Test status
Simulation time	100216979 ps
CPU time	1.16 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:15 PM PST 23
Peak memory	217540 kb
Host	smart-91456277-683a-43dc-a149-95075f3a4cf9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025903844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1025903844 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.1780789685
Short name	T211
Test name
Test status
Simulation time	16304845 ps
CPU time	0.81 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:54 PM PST 23
Peak memory	216924 kb
Host	smart-a85658f3-303c-4e4c-9b4c-ee94f21312e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780789685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1780789685 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.861081619
Short name	T208
Test name
Test status
Simulation time	80280578 ps
CPU time	1.45 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:16 PM PST 23
Peak memory	217396 kb
Host	smart-74f2c660-6e49-4d82-ab98-679c98978151
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861081619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr _outstanding.861081619 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3472745163
Short name	T68
Test name
Test status
Simulation time	156006711 ps
CPU time	1.02 seconds
Started	Dec 20 12:37:15 PM PST 23
Finished	Dec 20 12:38:11 PM PST 23
Peak memory	217952 kb
Host	smart-211d1259-11f8-408d-a62e-08fd878ed4ca
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472745163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.3472745163 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3497257693
Short name	T7
Test name
Test status
Simulation time	141032638 ps
CPU time	1.96 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:02 PM PST 23
Peak memory	220988 kb
Host	smart-5e8a292c-9bf8-457e-bde4-bf868a1d7159
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497257693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma c_shadow_reg_errors_with_csr_rw.3497257693 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.3093139614
Short name	T35
Test name
Test status
Simulation time	186563803 ps
CPU time	1.72 seconds
Started	Dec 20 12:37:23 PM PST 23
Finished	Dec 20 12:38:30 PM PST 23
Peak memory	217116 kb
Host	smart-c2c6fa2e-3233-486e-a824-fba32024b229
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093139614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3093139614 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1553561014
Short name	T81
Test name
Test status
Simulation time	229334283 ps
CPU time	2.4 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:24 PM PST 23
Peak memory	216752 kb
Host	smart-b36c9d36-4505-4cc1-8b83-27b71f773449
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553561014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1553 561014 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2093801089
Short name	T23
Test name
Test status
Simulation time	62446185 ps
CPU time	1.8 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:27 PM PST 23
Peak memory	222092 kb
Host	smart-485576ab-3d28-4c79-a0e7-98d3cc186182
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093801089 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2093801089 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2118099099
Short name	T93
Test name
Test status
Simulation time	73220114 ps
CPU time	1.17 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:17 PM PST 23
Peak memory	217756 kb
Host	smart-d7c0c7f5-3b9f-4d44-b495-d503507c0c0c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118099099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2118099099 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2387709337
Short name	T92
Test name
Test status
Simulation time	345560249 ps
CPU time	1.74 seconds
Started	Dec 20 12:37:23 PM PST 23
Finished	Dec 20 12:38:36 PM PST 23
Peak memory	217772 kb
Host	smart-0f6aaabe-fb1b-4929-aee8-ee4d18103c75
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387709337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.2387709337 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3929882152
Short name	T70
Test name
Test status
Simulation time	54038008 ps
CPU time	1.06 seconds
Started	Dec 20 12:37:06 PM PST 23
Finished	Dec 20 12:37:50 PM PST 23
Peak memory	218240 kb
Host	smart-bd1befc8-cccd-4315-b2af-15147d8980d7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929882152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.3929882152 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2030488925
Short name	T185
Test name
Test status
Simulation time	73124164 ps
CPU time	1.92 seconds
Started	Dec 20 12:37:07 PM PST 23
Finished	Dec 20 12:37:49 PM PST 23
Peak memory	221960 kb
Host	smart-53803d52-0f42-4211-83f0-6dd5f3a6fb4f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030488925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.2030488925 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1864563841
Short name	T125
Test name
Test status
Simulation time	605662656 ps
CPU time	1.77 seconds
Started	Dec 20 12:37:07 PM PST 23
Finished	Dec 20 12:37:50 PM PST 23
Peak memory	217656 kb
Host	smart-e4d8aa09-7755-45c1-819d-941134da5dea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864563841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1864563841 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3964959068
Short name	T38
Test name
Test status
Simulation time	109268980 ps
CPU time	2.94 seconds
Started	Dec 20 12:37:22 PM PST 23
Finished	Dec 20 12:38:31 PM PST 23
Peak memory	217576 kb
Host	smart-0e677dc1-ec85-4d8b-9d9a-22ea25fb9d40
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964959068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3964 959068 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3304754766
Short name	T149
Test name
Test status
Simulation time	31825961 ps
CPU time	1.34 seconds
Started	Dec 20 12:36:40 PM PST 23
Finished	Dec 20 12:36:55 PM PST 23
Peak memory	218752 kb
Host	smart-9341cd6e-517f-4f68-836d-241ec2088729
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304754766 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.3304754766 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.1570953052
Short name	T150
Test name
Test status
Simulation time	19995537 ps
CPU time	0.97 seconds
Started	Dec 20 12:38:44 PM PST 23
Finished	Dec 20 12:39:45 PM PST 23
Peak memory	216432 kb
Host	smart-8bd46f25-ce7b-4818-a344-7bc7b752551f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570953052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1570953052 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.3341756151
Short name	T113
Test name
Test status
Simulation time	12894053 ps
CPU time	0.76 seconds
Started	Dec 20 12:37:29 PM PST 23
Finished	Dec 20 12:38:43 PM PST 23
Peak memory	217584 kb
Host	smart-76bdf50e-bfa6-4214-96c2-09147c163084
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341756151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3341756151 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.4099279712
Short name	T18
Test name
Test status
Simulation time	98301092 ps
CPU time	1.9 seconds
Started	Dec 20 12:36:28 PM PST 23
Finished	Dec 20 12:36:35 PM PST 23
Peak memory	217712 kb
Host	smart-235156c5-4ec6-4708-b53d-dc0a3fd0bcf5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099279712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.4099279712 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1444955274
Short name	T53
Test name
Test status
Simulation time	106236590 ps
CPU time	1.33 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:56 PM PST 23
Peak memory	219116 kb
Host	smart-f9e9a42d-f1a6-4a5a-9dea-f5afb73dde68
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444955274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg _errors.1444955274 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.3589469590
Short name	T28
Test name
Test status
Simulation time	33578206 ps
CPU time	1.96 seconds
Started	Dec 20 12:37:09 PM PST 23
Finished	Dec 20 12:37:53 PM PST 23
Peak memory	217592 kb
Host	smart-b16a36a7-5f78-4f3c-bbfe-4c429949010c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589469590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3589469590 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1032826427
Short name	T214
Test name
Test status
Simulation time	452665450 ps
CPU time	3.22 seconds
Started	Dec 20 12:37:23 PM PST 23
Finished	Dec 20 12:38:34 PM PST 23
Peak memory	217764 kb
Host	smart-35f8ca91-c937-417b-9e3a-245bafc2093f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032826427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1032 826427 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.456901435
Short name	T4
Test name
Test status
Simulation time	91707747 ps
CPU time	1.64 seconds
Started	Dec 20 12:37:03 PM PST 23
Finished	Dec 20 12:37:44 PM PST 23
Peak memory	222684 kb
Host	smart-b22fbebb-f5aa-429f-9f61-892c2aad87e4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456901435 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.456901435 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.1994581554
Short name	T114
Test name
Test status
Simulation time	27157767 ps
CPU time	1.22 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:29 PM PST 23
Peak memory	217700 kb
Host	smart-5516505b-ba98-41a1-8036-bad38a842396
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994581554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1994581554 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.1499101428
Short name	T141
Test name
Test status
Simulation time	49498580 ps
CPU time	0.77 seconds
Started	Dec 20 12:36:43 PM PST 23
Finished	Dec 20 12:37:06 PM PST 23
Peak memory	217528 kb
Host	smart-473d08d1-22b2-47e4-8035-da61fb9fdb51
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499101428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1499101428 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1801333064
Short name	T175
Test name
Test status
Simulation time	63000786 ps
CPU time	1.7 seconds
Started	Dec 20 12:36:33 PM PST 23
Finished	Dec 20 12:36:41 PM PST 23
Peak memory	216764 kb
Host	smart-1487e48c-c712-4861-861d-884b0d97d231
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801333064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs r_outstanding.1801333064 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2241429282
Short name	T163
Test name
Test status
Simulation time	319494623 ps
CPU time	1.16 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:48 PM PST 23
Peak memory	218332 kb
Host	smart-c6b45030-4ffe-4cb5-95f2-17a82fff3fde
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241429282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.2241429282 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2892993988
Short name	T195
Test name
Test status
Simulation time	63149774 ps
CPU time	1.94 seconds
Started	Dec 20 12:36:45 PM PST 23
Finished	Dec 20 12:37:12 PM PST 23
Peak memory	220788 kb
Host	smart-005f776e-6115-429d-8ec8-07c9d11d0f04
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892993988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.2892993988 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2840120087
Short name	T73
Test name
Test status
Simulation time	147822129 ps
CPU time	2.62 seconds
Started	Dec 20 12:36:38 PM PST 23
Finished	Dec 20 12:36:52 PM PST 23
Peak memory	217808 kb
Host	smart-73b26718-4ddf-40c6-8f77-5b2c9df246a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840120087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2840120087 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.661751935
Short name	T181
Test name
Test status
Simulation time	411522382 ps
CPU time	2.94 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:32 PM PST 23
Peak memory	217808 kb
Host	smart-75a9540e-62a6-4322-9244-81768d180cdf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661751935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.66175 1935 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1861830459
Short name	T29
Test name
Test status
Simulation time	88498603 ps
CPU time	1.41 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:49 PM PST 23
Peak memory	218796 kb
Host	smart-7db2b19e-e147-44c1-900a-5365f53db175
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861830459 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.1861830459 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1707485108
Short name	T165
Test name
Test status
Simulation time	94687969 ps
CPU time	1.24 seconds
Started	Dec 20 12:36:48 PM PST 23
Finished	Dec 20 12:37:19 PM PST 23
Peak memory	217124 kb
Host	smart-da8e17bc-cb6c-4cbe-8757-b98a8c5c1fda
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707485108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1707485108 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.2949478502
Short name	T166
Test name
Test status
Simulation time	14225357 ps
CPU time	0.81 seconds
Started	Dec 20 12:36:42 PM PST 23
Finished	Dec 20 12:37:02 PM PST 23
Peak memory	217584 kb
Host	smart-41bfc400-d1db-4109-9b81-a96136e427d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949478502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2949478502 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.788371304
Short name	T136
Test name
Test status
Simulation time	33953371 ps
CPU time	1.51 seconds
Started	Dec 20 12:37:09 PM PST 23
Finished	Dec 20 12:37:53 PM PST 23
Peak memory	216856 kb
Host	smart-2ac59b05-59e0-4b26-a4df-41a1b4451132
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788371304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr _outstanding.788371304 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3383601999
Short name	T69
Test name
Test status
Simulation time	94393327 ps
CPU time	2.65 seconds
Started	Dec 20 12:36:35 PM PST 23
Finished	Dec 20 12:36:47 PM PST 23
Peak memory	220564 kb
Host	smart-4cd05786-316d-4a61-b445-95cc4134f6e3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383601999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma c_shadow_reg_errors_with_csr_rw.3383601999 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.1755046206
Short name	T156
Test name
Test status
Simulation time	199172352 ps
CPU time	2.52 seconds
Started	Dec 20 12:37:06 PM PST 23
Finished	Dec 20 12:37:51 PM PST 23
Peak memory	217816 kb
Host	smart-3b05506a-410a-4215-a29f-9858792aa524
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755046206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1755 046206 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1921631474
Short name	T189
Test name
Test status
Simulation time	75823506 ps
CPU time	1.27 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:55 PM PST 23
Peak memory	218780 kb
Host	smart-21cbd22c-2b73-473c-906c-fe773ffdda79
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921631474 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.1921631474 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.4116493741
Short name	T74
Test name
Test status
Simulation time	31419616 ps
CPU time	1.16 seconds
Started	Dec 20 12:36:56 PM PST 23
Finished	Dec 20 12:37:34 PM PST 23
Peak memory	217108 kb
Host	smart-128249d4-1afe-4e64-b1ed-2ce1fef6168b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116493741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.4116493741 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.3980471312
Short name	T167
Test name
Test status
Simulation time	14070049 ps
CPU time	0.81 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:15 PM PST 23
Peak memory	216704 kb
Host	smart-a442a686-d8bd-48de-b51d-78837d34395e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980471312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3980471312 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2625471840
Short name	T63
Test name
Test status
Simulation time	511669657 ps
CPU time	2.61 seconds
Started	Dec 20 12:36:59 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	216800 kb
Host	smart-4d850c87-2914-4582-bf81-55d9cc87d5b9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625471840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.2625471840 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3891010738
Short name	T122
Test name
Test status
Simulation time	48024799 ps
CPU time	1.06 seconds
Started	Dec 20 12:37:05 PM PST 23
Finished	Dec 20 12:37:46 PM PST 23
Peak memory	218256 kb
Host	smart-e99ad9c7-d7ac-438a-844d-fe8d964f4097
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891010738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg _errors.3891010738 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.225487696
Short name	T158
Test name
Test status
Simulation time	112022306 ps
CPU time	1.73 seconds
Started	Dec 20 12:37:07 PM PST 23
Finished	Dec 20 12:37:48 PM PST 23
Peak memory	225260 kb
Host	smart-a9076338-0b2e-4eef-904c-3b02362b9d60
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225487696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac _shadow_reg_errors_with_csr_rw.225487696 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3745515250
Short name	T72
Test name
Test status
Simulation time	381167080 ps
CPU time	3.09 seconds
Started	Dec 20 12:36:56 PM PST 23
Finished	Dec 20 12:37:42 PM PST 23
Peak memory	217012 kb
Host	smart-65c8f3de-a0c5-4a95-ba1e-c93e6084f241
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745515250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3745515250 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.4132830605
Short name	T34
Test name
Test status
Simulation time	207396421 ps
CPU time	2.94 seconds
Started	Dec 20 12:36:44 PM PST 23
Finished	Dec 20 12:37:11 PM PST 23
Peak memory	217728 kb
Host	smart-8cf66f50-5ed5-4b28-a5c1-aaee4b6294ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132830605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.4132 830605 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3383135475
Short name	T19
Test name
Test status
Simulation time	100966134 ps
CPU time	1.98 seconds
Started	Dec 20 12:37:01 PM PST 23
Finished	Dec 20 12:37:42 PM PST 23
Peak memory	222872 kb
Host	smart-d8fdc92a-23ac-4c3a-9edc-f5cc7da54082
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383135475 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.3383135475 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.4091696078
Short name	T118
Test name
Test status
Simulation time	33034003 ps
CPU time	1.21 seconds
Started	Dec 20 12:37:07 PM PST 23
Finished	Dec 20 12:37:50 PM PST 23
Peak memory	217820 kb
Host	smart-6a75767d-e9f3-44ea-a410-4e52b54b96cb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091696078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.4091696078 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.3050761789
Short name	T88
Test name
Test status
Simulation time	49573045 ps
CPU time	0.78 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:26 PM PST 23
Peak memory	217388 kb
Host	smart-d9f74ae6-124f-413e-886b-3a60ee07007a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050761789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3050761789 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1254514254
Short name	T50
Test name
Test status
Simulation time	425245595 ps
CPU time	2.73 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:07 PM PST 23
Peak memory	216944 kb
Host	smart-36de4650-ab39-4368-bf54-a078ad895028
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254514254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.1254514254 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1380034364
Short name	T190
Test name
Test status
Simulation time	43480096 ps
CPU time	1.15 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:51 PM PST 23
Peak memory	219264 kb
Host	smart-98414b74-95ba-4be7-a2a5-b0587c0a43fa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380034364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.1380034364 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.2206931064
Short name	T194
Test name
Test status
Simulation time	91706997 ps
CPU time	1.84 seconds
Started	Dec 20 12:37:16 PM PST 23
Finished	Dec 20 12:38:11 PM PST 23
Peak memory	217912 kb
Host	smart-c4a42d38-c038-44e7-b691-060095a472d6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206931064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2206931064 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1450647648
Short name	T161
Test name
Test status
Simulation time	32817750 ps
CPU time	1.22 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:26 PM PST 23
Peak memory	218528 kb
Host	smart-d24642f6-4ed5-46c6-bfb8-6cf0556eb08e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450647648 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.1450647648 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.2392185965
Short name	T171
Test name
Test status
Simulation time	36821328 ps
CPU time	1.22 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:16 PM PST 23
Peak memory	217728 kb
Host	smart-4ca58f6f-5378-42d9-96f8-3d0923bc85f3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392185965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2392185965 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.3799853199
Short name	T111
Test name
Test status
Simulation time	13665753 ps
CPU time	0.75 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:54 PM PST 23
Peak memory	217248 kb
Host	smart-4a49872f-a623-4e8a-871d-60e01d1b8434
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799853199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.3799853199 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.304044302
Short name	T104
Test name
Test status
Simulation time	196592631 ps
CPU time	1.69 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:05 PM PST 23
Peak memory	217508 kb
Host	smart-be3bd455-76f9-4aae-91d1-1be8b99caac6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304044302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr _outstanding.304044302 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2647288827
Short name	T9
Test name
Test status
Simulation time	37868954 ps
CPU time	1.29 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:07 PM PST 23
Peak memory	218096 kb
Host	smart-b52a444a-a10a-438e-a088-ff312ff05a0d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647288827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.2647288827 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2350674481
Short name	T196
Test name
Test status
Simulation time	181006005 ps
CPU time	3.22 seconds
Started	Dec 20 12:37:12 PM PST 23
Finished	Dec 20 12:38:02 PM PST 23
Peak memory	221728 kb
Host	smart-c55c61fa-3f84-4763-a66e-8f126d0dd945
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350674481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma c_shadow_reg_errors_with_csr_rw.2350674481 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.2891857976
Short name	T25
Test name
Test status
Simulation time	36978426 ps
CPU time	2.23 seconds
Started	Dec 20 12:37:41 PM PST 23
Finished	Dec 20 12:38:59 PM PST 23
Peak memory	217968 kb
Host	smart-109179ec-33d0-4371-9e4f-19e0a6052c83
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891857976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2891857976 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.3049388355
Short name	T178
Test name
Test status
Simulation time	213029238 ps
CPU time	2.59 seconds
Started	Dec 20 12:36:54 PM PST 23
Finished	Dec 20 12:37:32 PM PST 23
Peak memory	216628 kb
Host	smart-729872cc-92f0-4357-b0a7-ec20e747bf7f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049388355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3049 388355 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.866062205
Short name	T51
Test name
Test status
Simulation time	87837292 ps
CPU time	4.85 seconds
Started	Dec 20 12:33:04 PM PST 23
Finished	Dec 20 12:33:58 PM PST 23
Peak memory	217824 kb
Host	smart-0d034419-ff56-4b57-a59d-78e6fb55bbdb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866062205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.86606220 5 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.525734965
Short name	T119
Test name
Test status
Simulation time	1052349689 ps
CPU time	21.01 seconds
Started	Dec 20 12:32:49 PM PST 23
Finished	Dec 20 12:33:57 PM PST 23
Peak memory	217848 kb
Host	smart-05cf5771-e0db-46d3-a3a7-81a50c9abc5e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525734965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.52573496 5 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.451774927
Short name	T192
Test name
Test status
Simulation time	69407316 ps
CPU time	1.11 seconds
Started	Dec 20 12:32:57 PM PST 23
Finished	Dec 20 12:33:47 PM PST 23
Peak memory	217736 kb
Host	smart-f617e988-71d7-4e9f-8c9a-07fe891d3b39
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451774927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.45177492 7 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.648609532
Short name	T130
Test name
Test status
Simulation time	64875511 ps
CPU time	1.63 seconds
Started	Dec 20 12:33:12 PM PST 23
Finished	Dec 20 12:34:02 PM PST 23
Peak memory	222880 kb
Host	smart-3a30cb2a-d7e1-46aa-9a99-1010e8894e28
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648609532 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.648609532 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.2404322200
Short name	T31
Test name
Test status
Simulation time	110267070 ps
CPU time	1.11 seconds
Started	Dec 20 12:32:53 PM PST 23
Finished	Dec 20 12:33:41 PM PST 23
Peak memory	221632 kb
Host	smart-0ea46fba-c938-4763-a507-67007eef2b54
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404322200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2404322200 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.3733169843
Short name	T145
Test name
Test status
Simulation time	50133427 ps
CPU time	0.8 seconds
Started	Dec 20 12:33:08 PM PST 23
Finished	Dec 20 12:33:59 PM PST 23
Peak memory	217556 kb
Host	smart-3411356e-3726-4878-a15a-ec3c0f764de7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733169843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3733169843 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3563709254
Short name	T55
Test name
Test status
Simulation time	19201371 ps
CPU time	1.13 seconds
Started	Dec 20 12:33:09 PM PST 23
Finished	Dec 20 12:34:00 PM PST 23
Peak memory	217808 kb
Host	smart-776e4a7e-6a0c-42b0-917b-e05198652c36
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563709254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.3563709254 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.2715660119
Short name	T205
Test name
Test status
Simulation time	46521284 ps
CPU time	0.73 seconds
Started	Dec 20 12:33:04 PM PST 23
Finished	Dec 20 12:33:54 PM PST 23
Peak memory	216668 kb
Host	smart-b3b83ae2-95f4-46e7-901f-259b32668ef5
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715660119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2715660119 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2697787221
Short name	T107
Test name
Test status
Simulation time	218002096 ps
CPU time	1.79 seconds
Started	Dec 20 12:33:07 PM PST 23
Finished	Dec 20 12:33:59 PM PST 23
Peak memory	216980 kb
Host	smart-34925a18-0290-452b-a31c-f83522aa6d67
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697787221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.2697787221 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3568365258
Short name	T160
Test name
Test status
Simulation time	41517537 ps
CPU time	0.97 seconds
Started	Dec 20 12:32:53 PM PST 23
Finished	Dec 20 12:33:41 PM PST 23
Peak memory	217812 kb
Host	smart-88fd4167-c0ad-4970-b364-573b3a4713f9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568365258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.3568365258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3384873701
Short name	T112
Test name
Test status
Simulation time	62651475 ps
CPU time	1.86 seconds
Started	Dec 20 12:32:51 PM PST 23
Finished	Dec 20 12:33:40 PM PST 23
Peak memory	217824 kb
Host	smart-77564472-17ee-4127-bd8e-134478a84708
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384873701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac _shadow_reg_errors_with_csr_rw.3384873701 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.4271927801
Short name	T210
Test name
Test status
Simulation time	112903091 ps
CPU time	2.63 seconds
Started	Dec 20 12:32:54 PM PST 23
Finished	Dec 20 12:33:44 PM PST 23
Peak memory	217968 kb
Host	smart-bbe9ac98-7231-4502-bba5-5a2bf8145346
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271927801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.4271927801 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.381413049
Short name	T80
Test name
Test status
Simulation time	75421521 ps
CPU time	2.54 seconds
Started	Dec 20 12:32:50 PM PST 23
Finished	Dec 20 12:33:40 PM PST 23
Peak memory	216904 kb
Host	smart-cb6a1d97-5d6f-4115-beff-2825383a22f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381413049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.381413 049 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.4028380479
Short name	T168
Test name
Test status
Simulation time	15026076 ps
CPU time	0.79 seconds
Started	Dec 20 12:37:09 PM PST 23
Finished	Dec 20 12:37:52 PM PST 23
Peak memory	217304 kb
Host	smart-b597e2d5-32a1-43d9-926c-87d28d91662a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028380479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.4028380479 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3153915181
Short name	T212
Test name
Test status
Simulation time	57126409 ps
CPU time	0.77 seconds
Started	Dec 20 12:37:31 PM PST 23
Finished	Dec 20 12:38:46 PM PST 23
Peak memory	217396 kb
Host	smart-bc04ad21-2f4f-4c50-8eb8-f12cfcc4b9e8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153915181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3153915181 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.1266100669
Short name	T198
Test name
Test status
Simulation time	15908702 ps
CPU time	0.79 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:03 PM PST 23
Peak memory	217308 kb
Host	smart-eb62796e-f16f-4ce3-b3a3-fea8a6c3d580
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266100669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1266100669 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.941932193
Short name	T2
Test name
Test status
Simulation time	22549662 ps
CPU time	0.77 seconds
Started	Dec 20 12:36:58 PM PST 23
Finished	Dec 20 12:37:36 PM PST 23
Peak memory	217368 kb
Host	smart-568dbb4a-587c-4d5f-a9c7-b80e4d7e866c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941932193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.941932193 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.1554600448
Short name	T103
Test name
Test status
Simulation time	91271463 ps
CPU time	0.79 seconds
Started	Dec 20 12:37:30 PM PST 23
Finished	Dec 20 12:38:42 PM PST 23
Peak memory	216440 kb
Host	smart-439b4d5a-92ea-4081-aad6-e634b3b75697
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554600448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1554600448 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.488307969
Short name	T183
Test name
Test status
Simulation time	14383783 ps
CPU time	0.77 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:01 PM PST 23
Peak memory	216600 kb
Host	smart-16c9f071-370d-4638-bba0-728c87432723
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488307969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.488307969 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.352443458
Short name	T138
Test name
Test status
Simulation time	22737727 ps
CPU time	0.77 seconds
Started	Dec 20 12:37:23 PM PST 23
Finished	Dec 20 12:38:34 PM PST 23
Peak memory	217264 kb
Host	smart-154d5ac7-ba5b-429a-b934-745bdb4a56f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352443458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.352443458 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.302737263
Short name	T14
Test name
Test status
Simulation time	22048881 ps
CPU time	0.79 seconds
Started	Dec 20 12:36:31 PM PST 23
Finished	Dec 20 12:36:36 PM PST 23
Peak memory	217520 kb
Host	smart-b90378c2-4bdd-46a7-9b69-b6fda962c31d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302737263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.302737263 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.2560868566
Short name	T110
Test name
Test status
Simulation time	84754311 ps
CPU time	0.78 seconds
Started	Dec 20 12:37:05 PM PST 23
Finished	Dec 20 12:37:46 PM PST 23
Peak memory	217696 kb
Host	smart-68ff3068-5003-4680-ab0c-6f5c87b8d668
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560868566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2560868566 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.4059189065
Short name	T58
Test name
Test status
Simulation time	35487316 ps
CPU time	0.81 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:46 PM PST 23
Peak memory	216656 kb
Host	smart-cf9a35ba-0c3a-4a6b-9ab4-7f5e42bcfea0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059189065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.4059189065 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.2822954160
Short name	T188
Test name
Test status
Simulation time	315715905 ps
CPU time	9.48 seconds
Started	Dec 20 12:36:49 PM PST 23
Finished	Dec 20 12:37:30 PM PST 23
Peak memory	217708 kb
Host	smart-14dee486-c311-448d-bc87-6a1030b1dd5c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822954160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2822954 160 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.4118655960
Short name	T41
Test name
Test status
Simulation time	1393621733 ps
CPU time	11.75 seconds
Started	Dec 20 12:36:30 PM PST 23
Finished	Dec 20 12:36:46 PM PST 23
Peak memory	216880 kb
Host	smart-e838b8ab-441f-49b6-ad24-3501f0f290ee
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118655960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.4118655 960 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3742687665
Short name	T209
Test name
Test status
Simulation time	39772090 ps
CPU time	1.01 seconds
Started	Dec 20 12:36:30 PM PST 23
Finished	Dec 20 12:36:35 PM PST 23
Peak memory	217544 kb
Host	smart-7664a8bc-efd4-4e3d-8a3b-abca8de92aae
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742687665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3742687 665 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1332500965
Short name	T142
Test name
Test status
Simulation time	62187453 ps
CPU time	1.18 seconds
Started	Dec 20 12:37:11 PM PST 23
Finished	Dec 20 12:37:57 PM PST 23
Peak memory	218588 kb
Host	smart-a6c7097a-9817-4091-8d97-bcfcf56742ea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332500965 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.1332500965 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.2812730616
Short name	T106
Test name
Test status
Simulation time	168595159 ps
CPU time	1.09 seconds
Started	Dec 20 12:36:42 PM PST 23
Finished	Dec 20 12:37:00 PM PST 23
Peak memory	217588 kb
Host	smart-c5fe9d85-1967-494a-bacc-4680f5914d15
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812730616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2812730616 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.2498182461
Short name	T170
Test name
Test status
Simulation time	50259275 ps
CPU time	0.8 seconds
Started	Dec 20 12:36:34 PM PST 23
Finished	Dec 20 12:36:42 PM PST 23
Peak memory	217456 kb
Host	smart-1aec8baf-31f1-4258-9222-757972dec21d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498182461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2498182461 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1873492143
Short name	T45
Test name
Test status
Simulation time	18533853 ps
CPU time	1.12 seconds
Started	Dec 20 12:33:04 PM PST 23
Finished	Dec 20 12:33:55 PM PST 23
Peak memory	217692 kb
Host	smart-a8665d79-305e-4682-ab4c-fc32bf00e7e1
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873492143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.1873492143 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.155445570
Short name	T121
Test name
Test status
Simulation time	25839087 ps
CPU time	0.76 seconds
Started	Dec 20 12:33:12 PM PST 23
Finished	Dec 20 12:34:01 PM PST 23
Peak memory	217488 kb
Host	smart-a176d180-527a-40bc-b286-f915e50ae657
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155445570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.155445570 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3251033287
Short name	T201
Test name
Test status
Simulation time	107394365 ps
CPU time	2.66 seconds
Started	Dec 20 12:36:59 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	216984 kb
Host	smart-bd287427-7dd7-4676-b114-1a02a029a1a3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251033287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.3251033287 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3212631258
Short name	T135
Test name
Test status
Simulation time	21038718 ps
CPU time	1.02 seconds
Started	Dec 20 12:33:08 PM PST 23
Finished	Dec 20 12:33:59 PM PST 23
Peak memory	224992 kb
Host	smart-7fb7769b-3a66-486b-a7f6-b08c40375710
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212631258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.3212631258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.2108168042
Short name	T131
Test name
Test status
Simulation time	151830448 ps
CPU time	2.55 seconds
Started	Dec 20 12:33:01 PM PST 23
Finished	Dec 20 12:33:53 PM PST 23
Peak memory	217104 kb
Host	smart-6f8cda6e-89f7-44ec-9b6f-d3365eebc36c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108168042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2108168042 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.3534559194
Short name	T155
Test name
Test status
Simulation time	85561312 ps
CPU time	0.75 seconds
Started	Dec 20 12:36:39 PM PST 23
Finished	Dec 20 12:36:54 PM PST 23
Peak memory	217540 kb
Host	smart-c4455141-e19c-4be4-bd9d-13fcc5ac21da
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534559194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3534559194 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.23392159
Short name	T86
Test name
Test status
Simulation time	107880128 ps
CPU time	0.81 seconds
Started	Dec 20 12:37:00 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	217448 kb
Host	smart-8ea85619-a0ca-45c8-a131-601dd6328924
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23392159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.23392159 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2111474969
Short name	T206
Test name
Test status
Simulation time	46977906 ps
CPU time	0.79 seconds
Started	Dec 20 12:37:20 PM PST 23
Finished	Dec 20 12:38:20 PM PST 23
Peak memory	216652 kb
Host	smart-40c8acd8-4c75-4a35-953f-3607c4b0479c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111474969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2111474969 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.538506818
Short name	T17
Test name
Test status
Simulation time	40287638 ps
CPU time	0.82 seconds
Started	Dec 20 12:37:03 PM PST 23
Finished	Dec 20 12:37:44 PM PST 23
Peak memory	216800 kb
Host	smart-9076cd3f-755d-4b56-bac0-8bd675de54a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538506818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.538506818 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.1132435477
Short name	T162
Test name
Test status
Simulation time	16886164 ps
CPU time	0.76 seconds
Started	Dec 20 12:36:33 PM PST 23
Finished	Dec 20 12:36:40 PM PST 23
Peak memory	217572 kb
Host	smart-51a2dfca-5a27-495c-a0e5-075017cc0d5b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132435477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1132435477 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.2811786242
Short name	T164
Test name
Test status
Simulation time	22839308 ps
CPU time	0.78 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:48 PM PST 23
Peak memory	216740 kb
Host	smart-4dba1528-a7c0-4ed5-8b5a-506b47b9c748
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811786242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2811786242 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.102335570
Short name	T151
Test name
Test status
Simulation time	33437896 ps
CPU time	0.75 seconds
Started	Dec 20 12:36:39 PM PST 23
Finished	Dec 20 12:36:54 PM PST 23
Peak memory	217372 kb
Host	smart-3df1126a-415c-4976-afe7-85b6c4c6022d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102335570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.102335570 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.118702181
Short name	T94
Test name
Test status
Simulation time	16945749 ps
CPU time	0.8 seconds
Started	Dec 20 12:36:29 PM PST 23
Finished	Dec 20 12:36:35 PM PST 23
Peak memory	217420 kb
Host	smart-5447e816-f9ed-4730-92a7-e7ac579903e0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118702181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.118702181 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.1116007189
Short name	T134
Test name
Test status
Simulation time	58809276 ps
CPU time	0.77 seconds
Started	Dec 20 12:36:54 PM PST 23
Finished	Dec 20 12:37:31 PM PST 23
Peak memory	217524 kb
Host	smart-01e197a1-89a1-4bcf-ad53-f48c4f64ed5f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116007189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1116007189 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.2598193493
Short name	T87
Test name
Test status
Simulation time	54608720 ps
CPU time	0.8 seconds
Started	Dec 20 12:36:43 PM PST 23
Finished	Dec 20 12:37:08 PM PST 23
Peak memory	216656 kb
Host	smart-44313271-1c97-4572-beac-d23ca6a4348a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598193493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2598193493 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3896310651
Short name	T199
Test name
Test status
Simulation time	456992388 ps
CPU time	11.2 seconds
Started	Dec 20 12:36:30 PM PST 23
Finished	Dec 20 12:36:46 PM PST 23
Peak memory	217628 kb
Host	smart-b7f1eb95-d03a-413a-8fa1-0e9b20b3c6fe
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896310651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3896310 651 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2145111538
Short name	T123
Test name
Test status
Simulation time	4506214187 ps
CPU time	21.34 seconds
Started	Dec 20 12:36:48 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	217748 kb
Host	smart-d517b449-6c50-4233-a269-69e44e5dbda9
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145111538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2145111 538 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3366419360
Short name	T15
Test name
Test status
Simulation time	62130941 ps
CPU time	1.08 seconds
Started	Dec 20 12:36:33 PM PST 23
Finished	Dec 20 12:36:39 PM PST 23
Peak memory	217832 kb
Host	smart-47d79e73-e504-4a4e-a012-e9511ffc27f9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366419360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3366419 360 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1233416416
Short name	T177
Test name
Test status
Simulation time	37104364 ps
CPU time	1.29 seconds
Started	Dec 20 12:36:32 PM PST 23
Finished	Dec 20 12:36:40 PM PST 23
Peak memory	218600 kb
Host	smart-1ba5a220-678f-49d8-8d8b-c6cc6eb61aee
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233416416 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.1233416416 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.289747953
Short name	T101
Test name
Test status
Simulation time	27791333 ps
CPU time	1.02 seconds
Started	Dec 20 12:36:35 PM PST 23
Finished	Dec 20 12:36:44 PM PST 23
Peak memory	217524 kb
Host	smart-5d51f70a-c808-4f5c-9a1c-c17d25fc5ab6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289747953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.289747953 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3950794099
Short name	T152
Test name
Test status
Simulation time	12536582 ps
CPU time	0.8 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:48 PM PST 23
Peak memory	217528 kb
Host	smart-bc587e65-a1b1-4087-9218-bc0a868971bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950794099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3950794099 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.71073699
Short name	T49
Test name
Test status
Simulation time	27193886 ps
CPU time	1.14 seconds
Started	Dec 20 12:36:43 PM PST 23
Finished	Dec 20 12:37:08 PM PST 23
Peak memory	217620 kb
Host	smart-ab4fcf9f-9caa-4a12-9e3c-a66173fa7449
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71073699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_ access.71073699 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.3696328435
Short name	T173
Test name
Test status
Simulation time	33088671 ps
CPU time	0.73 seconds
Started	Dec 20 12:36:22 PM PST 23
Finished	Dec 20 12:36:23 PM PST 23
Peak memory	217464 kb
Host	smart-d06544cf-6c56-4092-94bb-6ebb1045110e
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696328435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3696328435 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.508569933
Short name	T184
Test name
Test status
Simulation time	173744095 ps
CPU time	1.64 seconds
Started	Dec 20 12:36:49 PM PST 23
Finished	Dec 20 12:37:22 PM PST 23
Peak memory	217712 kb
Host	smart-409251db-68d1-4603-ad88-2859335bb0e8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508569933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_ outstanding.508569933 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2336775676
Short name	T44
Test name
Test status
Simulation time	70658070 ps
CPU time	0.96 seconds
Started	Dec 20 12:36:39 PM PST 23
Finished	Dec 20 12:36:53 PM PST 23
Peak memory	217472 kb
Host	smart-a42a5223-73e3-4209-8d05-c9ee63565396
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336775676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.2336775676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2324970130
Short name	T204
Test name
Test status
Simulation time	185700248 ps
CPU time	3.03 seconds
Started	Dec 20 12:36:44 PM PST 23
Finished	Dec 20 12:37:12 PM PST 23
Peak memory	221696 kb
Host	smart-487d3383-9f4a-403e-a488-e3c84fc83b2f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324970130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.2324970130 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.1304812613
Short name	T148
Test name
Test status
Simulation time	22073701 ps
CPU time	1.52 seconds
Started	Dec 20 12:36:28 PM PST 23
Finished	Dec 20 12:36:34 PM PST 23
Peak memory	217756 kb
Host	smart-d361b751-ca77-4547-92c0-d5ac1cef33c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304812613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1304812613 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3397791779
Short name	T96
Test name
Test status
Simulation time	194522549 ps
CPU time	2.69 seconds
Started	Dec 20 12:36:24 PM PST 23
Finished	Dec 20 12:36:28 PM PST 23
Peak memory	217040 kb
Host	smart-1a6213ae-517e-4eb6-a973-724b8e14bd50
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397791779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.33977 91779 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.744766498
Short name	T47
Test name
Test status
Simulation time	26800946 ps
CPU time	0.77 seconds
Started	Dec 20 12:37:03 PM PST 23
Finished	Dec 20 12:37:43 PM PST 23
Peak memory	217388 kb
Host	smart-22093ae3-1ced-4ca9-b4e1-80cfb250d30c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744766498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.744766498 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.885115247
Short name	T105
Test name
Test status
Simulation time	26161236 ps
CPU time	0.78 seconds
Started	Dec 20 12:36:54 PM PST 23
Finished	Dec 20 12:37:30 PM PST 23
Peak memory	217472 kb
Host	smart-87b6635d-3c28-49ef-b154-6f2fa465f9e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885115247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.885115247 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.346619096
Short name	T174
Test name
Test status
Simulation time	44974113 ps
CPU time	0.8 seconds
Started	Dec 20 12:36:43 PM PST 23
Finished	Dec 20 12:37:08 PM PST 23
Peak memory	217524 kb
Host	smart-9feaf7a5-c3f5-41e8-ba3f-9a6a907ab9d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346619096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.346619096 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.1464133286
Short name	T179
Test name
Test status
Simulation time	33128870 ps
CPU time	0.79 seconds
Started	Dec 20 12:36:41 PM PST 23
Finished	Dec 20 12:36:58 PM PST 23
Peak memory	216616 kb
Host	smart-0d22595d-701f-4927-a0b0-28e3f6bf5331
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464133286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1464133286 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.54940551
Short name	T144
Test name
Test status
Simulation time	87362289 ps
CPU time	0.78 seconds
Started	Dec 20 12:36:47 PM PST 23
Finished	Dec 20 12:37:17 PM PST 23
Peak memory	216456 kb
Host	smart-94443191-175f-4835-a13a-67ad19cfe7db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54940551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.54940551 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.701005764
Short name	T108
Test name
Test status
Simulation time	38608840 ps
CPU time	0.77 seconds
Started	Dec 20 12:36:52 PM PST 23
Finished	Dec 20 12:37:27 PM PST 23
Peak memory	217408 kb
Host	smart-852fc9c9-3242-46e9-8ec2-ae8fa25c90eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701005764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.701005764 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.935575936
Short name	T85
Test name
Test status
Simulation time	22474406 ps
CPU time	0.77 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:51 PM PST 23
Peak memory	216780 kb
Host	smart-d06bf909-23f7-4cb6-a13a-5dc3427cb971
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935575936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.935575936 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.2149480697
Short name	T84
Test name
Test status
Simulation time	22360051 ps
CPU time	0.77 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:14 PM PST 23
Peak memory	216720 kb
Host	smart-0ee24042-907f-49d6-8a72-e670e1d094e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149480697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.2149480697 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2337981136
Short name	T203
Test name
Test status
Simulation time	16120840 ps
CPU time	0.84 seconds
Started	Dec 20 12:37:16 PM PST 23
Finished	Dec 20 12:38:10 PM PST 23
Peak memory	217560 kb
Host	smart-e0eb27ec-30ba-4aa3-ae87-20824304b344
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337981136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2337981136 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3901789146
Short name	T176
Test name
Test status
Simulation time	78431849 ps
CPU time	1.61 seconds
Started	Dec 20 12:36:26 PM PST 23
Finished	Dec 20 12:36:29 PM PST 23
Peak memory	222196 kb
Host	smart-6652d90f-eeab-4143-a674-c2cd46cbef31
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901789146 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3901789146 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.1762392480
Short name	T137
Test name
Test status
Simulation time	64247977 ps
CPU time	1.21 seconds
Started	Dec 20 12:36:25 PM PST 23
Finished	Dec 20 12:36:27 PM PST 23
Peak memory	217764 kb
Host	smart-ccc61d49-28c6-48b7-b9aa-1d598f00e651
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762392480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1762392480 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.2881188811
Short name	T197
Test name
Test status
Simulation time	40805738 ps
CPU time	0.8 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:30 PM PST 23
Peak memory	217476 kb
Host	smart-43a599fd-410a-44ac-bf16-975edb767d91
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881188811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2881188811 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1031234511
Short name	T180
Test name
Test status
Simulation time	102473155 ps
CPU time	1.59 seconds
Started	Dec 20 12:36:25 PM PST 23
Finished	Dec 20 12:36:28 PM PST 23
Peak memory	217752 kb
Host	smart-e442b2ea-4ca1-43f1-acac-a17247555a54
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031234511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.1031234511 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2478556062
Short name	T46
Test name
Test status
Simulation time	52660463 ps
CPU time	1.12 seconds
Started	Dec 20 12:36:38 PM PST 23
Finished	Dec 20 12:36:52 PM PST 23
Peak memory	224776 kb
Host	smart-0b17ea8e-290e-4e81-8e85-b144695982cd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478556062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.2478556062 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2921729098
Short name	T12
Test name
Test status
Simulation time	209706154 ps
CPU time	2.63 seconds
Started	Dec 20 12:37:01 PM PST 23
Finished	Dec 20 12:37:43 PM PST 23
Peak memory	221080 kb
Host	smart-160414e9-79a8-4f4d-b286-10923255108d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921729098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.2921729098 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.2072232423
Short name	T159
Test name
Test status
Simulation time	1014603672 ps
CPU time	2.67 seconds
Started	Dec 20 12:36:32 PM PST 23
Finished	Dec 20 12:36:39 PM PST 23
Peak memory	217872 kb
Host	smart-37690579-898f-476f-b37e-3d839de68283
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072232423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2072232423 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2408370890
Short name	T39
Test name
Test status
Simulation time	1202600632 ps
CPU time	5.18 seconds
Started	Dec 20 12:36:34 PM PST 23
Finished	Dec 20 12:36:47 PM PST 23
Peak memory	217612 kb
Host	smart-e57b0303-d092-4f9f-9d65-af678a99b32c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408370890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.24083 70890 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.890737842
Short name	T30
Test name
Test status
Simulation time	19868115 ps
CPU time	1.63 seconds
Started	Dec 20 12:36:25 PM PST 23
Finished	Dec 20 12:36:28 PM PST 23
Peak memory	222240 kb
Host	smart-73bcc655-5849-4a4d-83e8-1e16ca92f463
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890737842 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.890737842 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.2276666283
Short name	T207
Test name
Test status
Simulation time	22900150 ps
CPU time	0.94 seconds
Started	Dec 20 12:36:29 PM PST 23
Finished	Dec 20 12:36:34 PM PST 23
Peak memory	217380 kb
Host	smart-e5476948-1871-45a5-ad1b-94e9d11a28ea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276666283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.2276666283 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.2147308082
Short name	T139
Test name
Test status
Simulation time	16627183 ps
CPU time	0.82 seconds
Started	Dec 20 12:36:32 PM PST 23
Finished	Dec 20 12:36:39 PM PST 23
Peak memory	217476 kb
Host	smart-579acb8e-05fc-4490-bfee-68a7149857db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147308082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2147308082 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3143867335
Short name	T42
Test name
Test status
Simulation time	378702956 ps
CPU time	2.72 seconds
Started	Dec 20 12:36:31 PM PST 23
Finished	Dec 20 12:36:38 PM PST 23
Peak memory	217660 kb
Host	smart-65175458-c6d9-4f8b-ae60-e408d5e0e749
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143867335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.3143867335 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.4150004006
Short name	T182
Test name
Test status
Simulation time	182107874 ps
CPU time	1.47 seconds
Started	Dec 20 12:37:24 PM PST 23
Finished	Dec 20 12:38:37 PM PST 23
Peak memory	219000 kb
Host	smart-f30edf6e-6da0-4960-ad48-af42be61e206
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150004006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.4150004006 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3247319532
Short name	T66
Test name
Test status
Simulation time	419221372 ps
CPU time	3.03 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:32 PM PST 23
Peak memory	220840 kb
Host	smart-d2d9b89e-a539-4dcd-b7d9-1e818967cbdd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247319532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac _shadow_reg_errors_with_csr_rw.3247319532 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3028361779
Short name	T129
Test name
Test status
Simulation time	61038309 ps
CPU time	1.38 seconds
Started	Dec 20 12:36:40 PM PST 23
Finished	Dec 20 12:36:57 PM PST 23
Peak memory	217756 kb
Host	smart-b4066b4d-ca91-44a7-b45b-91e45d6413ad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028361779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3028361779 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3382672853
Short name	T82
Test name
Test status
Simulation time	586717616 ps
CPU time	4.31 seconds
Started	Dec 20 12:36:25 PM PST 23
Finished	Dec 20 12:36:31 PM PST 23
Peak memory	216900 kb
Host	smart-f1ed392c-d4c0-4654-ba17-d566c3a59930
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382672853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.33826 72853 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1127941375
Short name	T77
Test name
Test status
Simulation time	34810249 ps
CPU time	1.77 seconds
Started	Dec 20 12:37:03 PM PST 23
Finished	Dec 20 12:37:44 PM PST 23
Peak memory	222388 kb
Host	smart-3ea2c4f1-ca7e-428a-8507-c067d3257332
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127941375 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.1127941375 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.345376810
Short name	T91
Test name
Test status
Simulation time	16947953 ps
CPU time	1.09 seconds
Started	Dec 20 12:36:42 PM PST 23
Finished	Dec 20 12:37:02 PM PST 23
Peak memory	217520 kb
Host	smart-5d4b2128-474b-4d14-a964-d9b1bcdb4c48
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345376810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.345376810 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.1456502825
Short name	T124
Test name
Test status
Simulation time	22444360 ps
CPU time	0.8 seconds
Started	Dec 20 12:36:23 PM PST 23
Finished	Dec 20 12:36:25 PM PST 23
Peak memory	217512 kb
Host	smart-d0d5c8be-18ca-4b60-aec8-c911da306c0b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456502825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1456502825 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1300981256
Short name	T215
Test name
Test status
Simulation time	345898368 ps
CPU time	1.78 seconds
Started	Dec 20 12:37:00 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	217688 kb
Host	smart-976444bd-3f35-4907-85c1-167368f1cb77
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300981256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr _outstanding.1300981256 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2320791497
Short name	T67
Test name
Test status
Simulation time	37765614 ps
CPU time	1.3 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:30 PM PST 23
Peak memory	218292 kb
Host	smart-aed3e855-beab-406a-a337-81474209341f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320791497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.2320791497 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3952822943
Short name	T60
Test name
Test status
Simulation time	68538194 ps
CPU time	1.71 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:47 PM PST 23
Peak memory	222072 kb
Host	smart-adbce980-85b1-4595-a98f-ab3f288b4c3b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952822943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.3952822943 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.2548760577
Short name	T187
Test name
Test status
Simulation time	106338871 ps
CPU time	2.13 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:51 PM PST 23
Peak memory	216908 kb
Host	smart-42731f9a-2945-4da2-acb9-969402097ba1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548760577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2548760577 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3095893192
Short name	T186
Test name
Test status
Simulation time	173641412 ps
CPU time	2.52 seconds
Started	Dec 20 12:37:05 PM PST 23
Finished	Dec 20 12:37:48 PM PST 23
Peak memory	217676 kb
Host	smart-c5c9c94b-82e2-472b-a7a2-1db6724f3310
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095893192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.30958 93192 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3917698459
Short name	T22
Test name
Test status
Simulation time	56625520 ps
CPU time	1.37 seconds
Started	Dec 20 12:36:42 PM PST 23
Finished	Dec 20 12:37:20 PM PST 23
Peak memory	218712 kb
Host	smart-660212be-ba88-4a34-91f6-691c10abe83d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917698459 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3917698459 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.485006780
Short name	T20
Test name
Test status
Simulation time	117190028 ps
CPU time	1.21 seconds
Started	Dec 20 12:36:51 PM PST 23
Finished	Dec 20 12:37:24 PM PST 23
Peak memory	217744 kb
Host	smart-256fbd84-cfde-44a6-b92b-71811137f557
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485006780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.485006780 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.2856145691
Short name	T143
Test name
Test status
Simulation time	13711235 ps
CPU time	0.84 seconds
Started	Dec 20 12:36:50 PM PST 23
Finished	Dec 20 12:37:23 PM PST 23
Peak memory	217532 kb
Host	smart-9ca840a0-4394-49f6-84cc-28a68fe858ab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856145691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2856145691 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.456650702
Short name	T169
Test name
Test status
Simulation time	34982894 ps
CPU time	1.63 seconds
Started	Dec 20 12:36:24 PM PST 23
Finished	Dec 20 12:36:26 PM PST 23
Peak memory	217732 kb
Host	smart-70d854d7-5121-4449-b4b9-618c173b979e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456650702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_ outstanding.456650702 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2254826045
Short name	T202
Test name
Test status
Simulation time	27237526 ps
CPU time	1.13 seconds
Started	Dec 20 12:36:38 PM PST 23
Finished	Dec 20 12:37:08 PM PST 23
Peak memory	225016 kb
Host	smart-30ccd125-5fed-467e-b414-9ea54efd4745
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254826045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_ errors.2254826045 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3558552422
Short name	T213
Test name
Test status
Simulation time	137681890 ps
CPU time	1.99 seconds
Started	Dec 20 12:36:25 PM PST 23
Finished	Dec 20 12:36:28 PM PST 23
Peak memory	220592 kb
Host	smart-bea43045-1cd5-4d56-b879-18dd7029dc7d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558552422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.3558552422 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1630885376
Short name	T200
Test name
Test status
Simulation time	103459504 ps
CPU time	2.41 seconds
Started	Dec 20 12:36:43 PM PST 23
Finished	Dec 20 12:37:09 PM PST 23
Peak memory	216880 kb
Host	smart-06efc40c-f514-4f82-8b31-f3c0d911af16
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630885376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.16308 85376 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1648314977
Short name	T97
Test name
Test status
Simulation time	46665925 ps
CPU time	1.66 seconds
Started	Dec 20 12:36:37 PM PST 23
Finished	Dec 20 12:36:51 PM PST 23
Peak memory	218696 kb
Host	smart-4337aceb-9bb4-4fab-9fbe-b1a43ab27fcd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648314977 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.1648314977 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.1669441215
Short name	T75
Test name
Test status
Simulation time	113749778 ps
CPU time	1.21 seconds
Started	Dec 20 12:36:55 PM PST 23
Finished	Dec 20 12:37:31 PM PST 23
Peak memory	217696 kb
Host	smart-ec377be1-ac74-45b1-89ff-5486b96bfd11
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669441215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1669441215 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.79933955
Short name	T133
Test name
Test status
Simulation time	122742572 ps
CPU time	0.78 seconds
Started	Dec 20 12:36:39 PM PST 23
Finished	Dec 20 12:36:53 PM PST 23
Peak memory	217428 kb
Host	smart-bb8551ec-6385-41fe-bb81-5059f38b82c0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79933955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.79933955 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3859309595
Short name	T154
Test name
Test status
Simulation time	115688180 ps
CPU time	1.7 seconds
Started	Dec 20 12:37:20 PM PST 23
Finished	Dec 20 12:38:26 PM PST 23
Peak memory	217584 kb
Host	smart-498dd2e8-c6c1-4458-98a5-5d334de5ba0e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859309595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr _outstanding.3859309595 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2938163038
Short name	T157
Test name
Test status
Simulation time	54305468 ps
CPU time	1.24 seconds
Started	Dec 20 12:36:33 PM PST 23
Finished	Dec 20 12:36:40 PM PST 23
Peak memory	225140 kb
Host	smart-d668285f-ddef-41b7-8e4a-76f0750b01a8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938163038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.2938163038 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2266522437
Short name	T11
Test name
Test status
Simulation time	75532901 ps
CPU time	2.46 seconds
Started	Dec 20 12:37:27 PM PST 23
Finished	Dec 20 12:38:43 PM PST 23
Peak memory	220948 kb
Host	smart-b4c0992b-9f37-4611-a457-f027b5d43ae8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266522437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.2266522437 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.1221003598
Short name	T116
Test name
Test status
Simulation time	103479915 ps
CPU time	2.02 seconds
Started	Dec 20 12:36:26 PM PST 23
Finished	Dec 20 12:36:30 PM PST 23
Peak memory	217952 kb
Host	smart-a846db84-0753-4733-987c-1648f7b22805
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221003598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1221003598 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.666211356
Short name	T33
Test name
Test status
Simulation time	541882737 ps
CPU time	4.16 seconds
Started	Dec 20 12:36:37 PM PST 23
Finished	Dec 20 12:36:54 PM PST 23
Peak memory	217744 kb
Host	smart-aa27ac28-e8dd-464b-aa01-3e995abc3726
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666211356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.666211 356 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest