Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1			T2	4		T14	4		T58	4
all_values[1]	263	1			T2	4		T14	4		T58	4
all_values[2]	263	1			T2	4		T14	4		T58	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

459

1

T2

6

T14

3

T58

11

auto[1]

330

1

T2

6

T14

9

T58

1

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324

1

T2

8

T14

5

T58

6

auto[1]

465

1

T2

4

T14

7

T58

6

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

465

1

T2

9

T14

9

T58

8

auto[1]

324

1

T2

3

T14

3

T58

4

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

67

1

T2

1

T58

2

T16

2

all_values[0]

auto[0]

auto[0]

auto[1]

24

1

T58

1

T84

1

T87

1

all_values[0]

auto[0]

auto[1]

auto[0]

42

1

T2

2

T14

1

T16

1

all_values[0]

auto[0]

auto[1]

auto[1]

20

1

T14

2

T16

1

T85

2

all_values[0]

auto[1]

auto[0]

auto[1]

67

1

T2

1

T14

1

T58

1

all_values[0]

auto[1]

auto[1]

auto[1]

43

1

T16

2

T17

2

T85

2

all_values[1]

auto[0]

auto[0]

auto[0]

71

1

T2

3

T58

1

T16

2

all_values[1]

auto[0]

auto[0]

auto[1]

25

1

T58

1

T16

2

T84

1

all_values[1]

auto[0]

auto[1]

auto[0]

40

1

T2

1

T14

1

T17

2

all_values[1]

auto[0]

auto[1]

auto[1]

23

1

T14

2

T16

1

T17

1

all_values[1]

auto[1]

auto[0]

auto[1]

64

1

T58

2

T16

2

T76

2

all_values[1]

auto[1]

auto[1]

auto[1]

40

1

T14

1

T17

1

T76

1

all_values[2]

auto[0]

auto[0]

auto[0]

64

1

T2

1

T14

2

T58

2

all_values[2]

auto[0]

auto[0]

auto[1]

19

1

T17

1

T88

1

T86

1

all_values[2]

auto[0]

auto[1]

auto[0]

40

1

T14

1

T58

1

T16

1

all_values[2]

auto[0]

auto[1]

auto[1]

30

1

T2

1

T16

2

T17

1

all_values[2]

auto[1]

auto[0]

auto[1]

58

1

T58

1

T16

2

T17

1

all_values[2]

auto[1]

auto[1]

auto[1]

52

1

T2

2

T14

1

T16

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal