Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
204207 |
1 |
|
|
T4 |
5 |
|
T5 |
2375 |
|
T10 |
104 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
109471 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
68658 |
1 |
|
|
T4 |
4 |
|
T5 |
76 |
|
T10 |
1 |
seven_bytes |
3722 |
1 |
|
|
T5 |
68 |
|
T10 |
3 |
|
T26 |
26 |
six_bytes |
3754 |
1 |
|
|
T5 |
65 |
|
T10 |
2 |
|
T26 |
17 |
five_bytes |
3802 |
1 |
|
|
T5 |
71 |
|
T10 |
1 |
|
T26 |
23 |
four_bytes |
3718 |
1 |
|
|
T5 |
60 |
|
T10 |
4 |
|
T26 |
14 |
three_bytes |
3747 |
1 |
|
|
T5 |
51 |
|
T10 |
2 |
|
T26 |
12 |
two_bytes |
3644 |
1 |
|
|
T5 |
68 |
|
T10 |
5 |
|
T26 |
17 |
one_byte |
3691 |
1 |
|
|
T5 |
70 |
|
T10 |
3 |
|
T26 |
23 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
200447 |
1 |
|
|
T4 |
3 |
|
T5 |
2349 |
|
T10 |
100 |
auto[1] |
3760 |
1 |
|
|
T4 |
2 |
|
T5 |
26 |
|
T10 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
204207 |
1 |
|
|
T4 |
5 |
|
T5 |
2375 |
|
T10 |
104 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
204198 |
1 |
|
|
T4 |
5 |
|
T5 |
2375 |
|
T10 |
104 |
auto[1] |
9 |
1 |
|
|
T32 |
1 |
|
T136 |
1 |
|
T39 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1255 |
1 |
|
|
T4 |
1 |
|
T5 |
4 |
|
T26 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3760 |
1 |
|
|
T4 |
2 |
|
T5 |
26 |
|
T10 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
188912 |
1 |
|
|
T4 |
114 |
|
T5 |
1964 |
|
T10 |
239 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
99825 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
65434 |
1 |
|
|
T4 |
112 |
|
T5 |
39 |
|
T10 |
6 |
seven_bytes |
3343 |
1 |
|
|
T5 |
45 |
|
T10 |
6 |
|
T26 |
6 |
six_bytes |
3471 |
1 |
|
|
T5 |
48 |
|
T10 |
10 |
|
T26 |
6 |
five_bytes |
3338 |
1 |
|
|
T5 |
49 |
|
T10 |
4 |
|
T26 |
3 |
four_bytes |
3292 |
1 |
|
|
T5 |
54 |
|
T10 |
10 |
|
T26 |
5 |
three_bytes |
3381 |
1 |
|
|
T5 |
63 |
|
T10 |
6 |
|
T26 |
2 |
two_bytes |
3432 |
1 |
|
|
T5 |
59 |
|
T10 |
7 |
|
T26 |
3 |
one_byte |
3396 |
1 |
|
|
T5 |
46 |
|
T10 |
12 |
|
T26 |
3 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
185234 |
1 |
|
|
T4 |
110 |
|
T5 |
1936 |
|
T10 |
237 |
auto[1] |
3678 |
1 |
|
|
T4 |
4 |
|
T5 |
28 |
|
T10 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
188912 |
1 |
|
|
T4 |
114 |
|
T5 |
1964 |
|
T10 |
239 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
188903 |
1 |
|
|
T4 |
114 |
|
T5 |
1964 |
|
T10 |
239 |
auto[1] |
9 |
1 |
|
|
T70 |
1 |
|
T137 |
1 |
|
T138 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1243 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T24 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3678 |
1 |
|
|
T4 |
4 |
|
T5 |
28 |
|
T10 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
380742 |
1 |
|
|
T4 |
56 |
|
T5 |
2397 |
|
T10 |
362 |
auto[1] |
582 |
1 |
|
|
T37 |
19 |
|
T38 |
54 |
|
T39 |
104 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
197599 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
136700 |
1 |
|
|
T4 |
55 |
|
T5 |
66 |
|
T10 |
14 |
seven_bytes |
6654 |
1 |
|
|
T5 |
60 |
|
T10 |
8 |
|
T26 |
2 |
six_bytes |
6725 |
1 |
|
|
T5 |
62 |
|
T10 |
13 |
|
T26 |
8 |
five_bytes |
6713 |
1 |
|
|
T5 |
63 |
|
T10 |
5 |
|
T26 |
5 |
four_bytes |
6604 |
1 |
|
|
T5 |
63 |
|
T10 |
7 |
|
T26 |
7 |
three_bytes |
6872 |
1 |
|
|
T5 |
76 |
|
T10 |
5 |
|
T26 |
3 |
two_bytes |
6687 |
1 |
|
|
T5 |
74 |
|
T10 |
12 |
|
T26 |
6 |
one_byte |
6770 |
1 |
|
|
T5 |
70 |
|
T10 |
5 |
|
T26 |
6 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
374040 |
1 |
|
|
T4 |
54 |
|
T5 |
2355 |
|
T10 |
356 |
auto[1] |
7284 |
1 |
|
|
T4 |
2 |
|
T5 |
42 |
|
T10 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
381324 |
1 |
|
|
T4 |
56 |
|
T5 |
2397 |
|
T10 |
362 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
381300 |
1 |
|
|
T4 |
56 |
|
T5 |
2397 |
|
T10 |
362 |
auto[1] |
24 |
1 |
|
|
T39 |
1 |
|
T139 |
1 |
|
T140 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2524 |
1 |
|
|
T4 |
1 |
|
T5 |
7 |
|
T10 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
7284 |
1 |
|
|
T4 |
2 |
|
T5 |
42 |
|
T10 |
6 |