Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	267569392	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

193619529

1

T1

3521

T2

8

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	238418564	1			T1	6845		T2	11		T3	20
values[0x0]	106887507	1			T1	51		T2	7		T3	7
values[0x1]	115882850	1			T1	69		T2	4		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	207735164	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

253453757

1

T1

4209

T2

10

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3286305	1			T47	3		T48	2		T50	2
valid_sources[0x01]	1321235	1			T47	4		T48	11		T49	1
valid_sources[0x02]	1634337	1			T47	5		T48	5		T52	7
valid_sources[0x03]	1323971	1			T47	4		T48	9		T50	3
valid_sources[0x04]	1998599	1			T47	7		T49	1		T52	2
valid_sources[0x05]	1323244	1			T1	60		T47	2		T48	1
valid_sources[0x06]	1315625	1			T47	5		T48	1		T50	2
valid_sources[0x07]	2231597	1			T47	6		T48	9		T50	2
valid_sources[0x08]	1317281	1			T2	1		T47	1		T48	7
valid_sources[0x09]	1320609	1			T1	60		T47	4		T48	7
valid_sources[0x0a]	1325421	1			T1	60		T47	5		T48	5
valid_sources[0x0b]	1973874	1			T47	7		T48	5		T52	4
valid_sources[0x0c]	1348158	1			T1	60		T47	3		T48	10
valid_sources[0x0d]	1891583	1			T47	8		T48	5		T50	1
valid_sources[0x0e]	1326038	1			T47	5		T48	8		T50	1
valid_sources[0x0f]	1317566	1			T1	60		T47	7		T48	7
valid_sources[0x10]	1563445	1			T47	5		T48	10		T49	6
valid_sources[0x11]	1335879	1			T47	3		T48	10		T49	2
valid_sources[0x12]	1321632	1			T1	91		T47	9		T48	8
valid_sources[0x13]	2184631	1			T3	1		T47	2		T48	5
valid_sources[0x14]	4669874	1			T1	60		T47	3		T48	5
valid_sources[0x15]	3824375	1			T47	4		T48	9		T50	2
valid_sources[0x16]	1325649	1			T47	5		T48	2		T49	2
valid_sources[0x17]	1543657	1			T47	9		T48	11		T50	1
valid_sources[0x18]	1322266	1			T1	60		T2	1		T47	5
valid_sources[0x19]	1330552	1			T3	1		T47	3		T48	1
valid_sources[0x1a]	1328503	1			T1	120		T47	3		T48	6
valid_sources[0x1b]	1324081	1			T2	1		T47	7		T48	6
valid_sources[0x1c]	3078908	1			T3	1		T47	3		T48	6
valid_sources[0x1d]	1931698	1			T1	60		T47	9		T48	1
valid_sources[0x1e]	1325277	1			T1	90		T47	9		T48	13
valid_sources[0x1f]	1327480	1			T47	7		T48	14		T50	2
valid_sources[0x20]	1969159	1			T1	60		T2	2		T47	2
valid_sources[0x21]	1323006	1			T3	1		T47	4		T48	5
valid_sources[0x22]	1316255	1			T3	1		T47	8		T48	1
valid_sources[0x23]	4143097	1			T47	9		T48	4		T49	1
valid_sources[0x24]	1319176	1			T47	7		T49	3		T50	2
valid_sources[0x25]	1323760	1			T47	1		T48	5		T50	1
valid_sources[0x26]	2156412	1			T47	3		T48	4		T49	5
valid_sources[0x27]	2234780	1			T47	6		T48	11		T52	5
valid_sources[0x28]	1319165	1			T47	6		T48	9		T49	2
valid_sources[0x29]	1318209	1			T3	1		T47	2		T48	2
valid_sources[0x2a]	1339404	1			T1	60		T47	5		T48	2
valid_sources[0x2b]	1969230	1			T1	60		T47	5		T48	2
valid_sources[0x2c]	1329527	1			T1	60		T47	2		T48	9
valid_sources[0x2d]	1335325	1			T1	60		T47	5		T48	3
valid_sources[0x2e]	3648895	1			T2	1		T47	7		T48	5
valid_sources[0x2f]	1322716	1			T47	3		T48	3		T49	1
valid_sources[0x30]	1983669	1			T1	120		T47	9		T48	4
valid_sources[0x31]	1361364	1			T47	3		T48	2		T50	5
valid_sources[0x32]	1324870	1			T1	60		T47	6		T48	7
valid_sources[0x33]	1319684	1			T47	5		T48	5		T49	1
valid_sources[0x34]	1322733	1			T47	9		T48	9		T52	5
valid_sources[0x35]	1448414	1			T3	1		T47	9		T48	11
valid_sources[0x36]	1477565	1			T47	11		T48	6		T49	4
valid_sources[0x37]	1322163	1			T3	1		T47	6		T48	4
valid_sources[0x38]	1320299	1			T1	60		T47	2		T48	7
valid_sources[0x39]	1329388	1			T47	6		T48	7		T50	2
valid_sources[0x3a]	3290141	1			T47	8		T48	8		T50	2
valid_sources[0x3b]	3320105	1			T1	60		T47	4		T48	5
valid_sources[0x3c]	2263977	1			T1	60		T47	12		T48	1
valid_sources[0x3d]	2434683	1			T47	4		T48	6		T49	4
valid_sources[0x3e]	2273868	1			T1	120		T47	4		T48	6
valid_sources[0x3f]	1320858	1			T1	60		T47	6		T48	5
valid_sources[0x40]	1772458	1			T1	180		T3	1		T47	5
valid_sources[0x41]	1356057	1			T3	1		T47	3		T48	7
valid_sources[0x42]	1365462	1			T1	60		T47	4		T48	8
valid_sources[0x43]	2498633	1			T1	120		T3	1		T47	7
valid_sources[0x44]	1327167	1			T1	60		T47	2		T48	7
valid_sources[0x45]	1436004	1			T3	2		T47	7		T48	3
valid_sources[0x46]	1317708	1			T47	4		T48	4		T50	2
valid_sources[0x47]	1323622	1			T47	1		T48	4		T49	1
valid_sources[0x48]	1356055	1			T1	60		T47	9		T48	8
valid_sources[0x49]	3663124	1			T3	1		T47	6		T48	1
valid_sources[0x4a]	1455046	1			T47	5		T48	7		T50	1
valid_sources[0x4b]	1309508	1			T47	8		T48	9		T49	1
valid_sources[0x4c]	1325552	1			T47	6		T48	4		T52	6
valid_sources[0x4d]	1335803	1			T47	4		T48	4		T50	1
valid_sources[0x4e]	1996911	1			T47	4		T48	2		T49	1
valid_sources[0x4f]	3387755	1			T47	5		T48	1		T50	1
valid_sources[0x50]	2474499	1			T1	60		T47	2		T48	6
valid_sources[0x51]	2297526	1			T47	4		T48	11		T49	3
valid_sources[0x52]	1832476	1			T1	60		T2	3		T3	2
valid_sources[0x53]	1324529	1			T1	30		T47	6		T48	4
valid_sources[0x54]	2078731	1			T3	1		T47	7		T48	11
valid_sources[0x55]	1321387	1			T47	5		T48	4		T49	1
valid_sources[0x56]	1323956	1			T1	90		T47	6		T48	3
valid_sources[0x57]	1326981	1			T1	60		T47	9		T48	5
valid_sources[0x58]	1319853	1			T1	60		T47	8		T48	1
valid_sources[0x59]	1364337	1			T47	10		T48	12		T52	4
valid_sources[0x5a]	1341539	1			T47	3		T48	12		T50	2
valid_sources[0x5b]	1317822	1			T47	12		T48	1		T52	5
valid_sources[0x5c]	1640221	1			T47	6		T48	8		T50	3
valid_sources[0x5d]	1325368	1			T47	10		T48	3		T50	2
valid_sources[0x5e]	1369794	1			T3	2		T47	5		T48	3
valid_sources[0x5f]	1322869	1			T1	60		T47	2		T48	9
valid_sources[0x60]	2191595	1			T3	1		T47	4		T48	6
valid_sources[0x61]	1323864	1			T3	1		T47	7		T48	7
valid_sources[0x62]	1317241	1			T47	8		T48	6		T50	1
valid_sources[0x63]	3676380	1			T47	7		T49	7		T50	1
valid_sources[0x64]	1325534	1			T1	60		T47	1		T48	15
valid_sources[0x65]	1334847	1			T1	60		T48	9		T50	2
valid_sources[0x66]	1311385	1			T47	6		T48	3		T50	1
valid_sources[0x67]	2215731	1			T1	60		T2	1		T47	1
valid_sources[0x68]	1981843	1			T1	60		T47	2		T48	7
valid_sources[0x69]	2073636	1			T1	120		T3	1		T47	4
valid_sources[0x6a]	1852299	1			T47	9		T48	5		T52	6
valid_sources[0x6b]	1386181	1			T1	60		T47	8		T48	3
valid_sources[0x6c]	1766778	1			T1	120		T47	6		T48	7
valid_sources[0x6d]	1316651	1			T47	2		T48	10		T50	3
valid_sources[0x6e]	1321260	1			T47	10		T48	2		T50	1
valid_sources[0x6f]	3258039	1			T1	60		T3	1		T47	9
valid_sources[0x70]	1319186	1			T47	5		T48	17		T50	1
valid_sources[0x71]	1327300	1			T47	2		T48	6		T50	1
valid_sources[0x72]	1443828	1			T1	211		T47	5		T48	7
valid_sources[0x73]	1493237	1			T1	60		T47	8		T48	7
valid_sources[0x74]	1345069	1			T1	60		T47	8		T48	10
valid_sources[0x75]	1320982	1			T47	5		T48	2		T49	1
valid_sources[0x76]	3057243	1			T47	5		T48	2		T50	1
valid_sources[0x77]	1412643	1			T48	4		T50	1		T52	4
valid_sources[0x78]	4585699	1			T1	60		T47	6		T48	7
valid_sources[0x79]	3135910	1			T1	60		T47	5		T48	7
valid_sources[0x7a]	1816457	1			T2	4		T47	3		T48	2
valid_sources[0x7b]	6639138	1			T47	3		T48	4		T49	3
valid_sources[0x7c]	3634350	1			T1	60		T47	8		T48	7
valid_sources[0x7d]	1327541	1			T1	60		T47	3		T48	7
valid_sources[0x7e]	1315132	1			T3	1		T47	5		T48	4
valid_sources[0x7f]	1780623	1			T47	4		T48	7		T50	2
valid_sources[0x80]	1323141	1			T1	60		T47	8		T48	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75231087

1

T1

3410

T2

4

T3

12

values[0x0]

all_enables

biggest_size

63543054

1

T1

48

T2

3

T3

1

values[0x1]

all_enables

biggest_size

54845388

1

T1

63

T2

1

T3

5