Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
275066376 |
1 |
|
|
T1 |
3444 |
|
T2 |
14 |
|
T3 |
22 |
full_word |
194084072 |
1 |
|
|
T1 |
3521 |
|
T2 |
8 |
|
T3 |
18 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
469150138 |
1 |
|
|
T1 |
6965 |
|
T2 |
22 |
|
T3 |
40 |
auto[TlIntgErrCmd] |
100 |
1 |
|
|
T47 |
7 |
|
T48 |
4 |
|
T65 |
6 |
auto[TlIntgErrData] |
114 |
1 |
|
|
T47 |
3 |
|
T48 |
4 |
|
T65 |
9 |
auto[TlIntgErrBoth] |
96 |
1 |
|
|
T48 |
2 |
|
T65 |
5 |
|
T108 |
4 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
239842017 |
1 |
|
|
T1 |
6845 |
|
T2 |
11 |
|
T3 |
20 |
auto[1] |
229308431 |
1 |
|
|
T1 |
120 |
|
T2 |
11 |
|
T3 |
20 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
164495274 |
1 |
|
|
T1 |
3435 |
|
T2 |
7 |
|
T3 |
8 |
auto[TlIntgErrNone] |
partial |
auto[1] |
110570810 |
1 |
|
|
T1 |
9 |
|
T2 |
7 |
|
T3 |
14 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
75346604 |
1 |
|
|
T1 |
3410 |
|
T2 |
4 |
|
T3 |
12 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
118737450 |
1 |
|
|
T1 |
111 |
|
T2 |
4 |
|
T3 |
6 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
36 |
1 |
|
|
T47 |
3 |
|
T48 |
1 |
|
T65 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
58 |
1 |
|
|
T47 |
3 |
|
T48 |
3 |
|
T65 |
4 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
2 |
1 |
|
|
T150 |
1 |
|
T151 |
1 |
|
- |
- |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
|
T47 |
1 |
|
T108 |
1 |
|
T152 |
2 |
auto[TlIntgErrData] |
partial |
auto[0] |
56 |
1 |
|
|
T47 |
2 |
|
T48 |
3 |
|
T65 |
4 |
auto[TlIntgErrData] |
partial |
auto[1] |
50 |
1 |
|
|
T47 |
1 |
|
T48 |
1 |
|
T65 |
4 |
auto[TlIntgErrData] |
full_word |
auto[0] |
4 |
1 |
|
|
T108 |
1 |
|
T109 |
1 |
|
T153 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
4 |
1 |
|
|
T65 |
1 |
|
T147 |
1 |
|
T154 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
40 |
1 |
|
|
T48 |
1 |
|
T65 |
3 |
|
T109 |
3 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
52 |
1 |
|
|
T48 |
1 |
|
T65 |
2 |
|
T108 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
1 |
1 |
|
|
T108 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
3 |
1 |
|
|
T108 |
1 |
|
T153 |
1 |
|
T155 |
1 |