| | | | | | | |
gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
gen_alert_tx[1].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
gen_entropy.u_entropy |
99.29 |
100.00 |
95.74 |
100.00 |
100.00 |
100.00 |
100.00 |
gen_lfsrs[0].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[10].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[11].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[12].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[13].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[14].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[15].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[16].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[17].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[18].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[19].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[1].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[20].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[21].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[22].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[23].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[24].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[2].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[3].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[4].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[5].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[6].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[7].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[8].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
gen_lfsrs[9].u_lfsr_chunk |
100.00 |
|
|
100.00 |
|
|
|
u_entropy_configured |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_prim_buf.u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_hash_count |
100.00 |
|
|
100.00 |
|
|
|
u_seed_idx_count |
100.00 |
|
|
100.00 |
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_entropy.u_prim_sync_reqack_data |
95.83 |
100.00 |
83.33 |
|
|
100.00 |
100.00 |
u_prim_sync_reqack |
95.83 |
100.00 |
83.33 |
|
|
100.00 |
100.00 |
gen_nrz_hs_protocol.ack_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_nrz_hs_protocol.req_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
intr_fifo_empty |
93.75 |
100.00 |
75.00 |
|
|
100.00 |
100.00 |
intr_kmac_done |
93.75 |
100.00 |
75.00 |
|
|
100.00 |
100.00 |
intr_kmac_err |
93.75 |
100.00 |
75.00 |
|
|
100.00 |
100.00 |
kmac_csr_assert |
100.00 |
|
|
|
|
|
100.00 |
sha3pad_assert_cov_if |
100.00 |
|
|
|
|
|
100.00 |
tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_app_intf |
97.42 |
97.45 |
90.82 |
|
100.00 |
98.82 |
100.00 |
u_appid_arb |
95.05 |
87.50 |
92.68 |
|
|
100.00 |
100.00 |
u_prim_buf_state_err_check |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_buf_state_kmac_sel |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_buf_state_output_sel |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_buf_state_output_valid |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_errchk |
96.60 |
95.06 |
94.59 |
|
100.00 |
93.33 |
100.00 |
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_kmac_core |
95.80 |
98.88 |
92.86 |
100.00 |
100.00 |
91.38 |
91.67 |
gen_key_slicer[0].u_key_slicer |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_key_slicer[1].u_key_slicer |
100.00 |
100.00 |
|
|
|
|
100.00 |
u_key_index_count |
100.00 |
|
|
100.00 |
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_msgfifo |
97.32 |
100.00 |
95.16 |
94.52 |
100.00 |
94.23 |
100.00 |
u_msgfifo |
98.38 |
100.00 |
91.89 |
100.00 |
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
100.00 |
|
|
|
gen_secure_ptrs.u_rptr |
100.00 |
|
|
100.00 |
|
|
|
gen_secure_ptrs.u_wptr |
100.00 |
|
|
100.00 |
|
|
|
u_packer |
96.41 |
100.00 |
100.00 |
89.74 |
|
92.31 |
100.00 |
g_pos_dupcnt.u_pos |
89.74 |
|
|
89.74 |
|
|
|
u_prim_lc_sync |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[5].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[5].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[5].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[5].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_flops.u_prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_reg |
99.00 |
99.41 |
96.63 |
100.00 |
|
98.94 |
100.00 |
subtree... |
|
|
|
|
|
|
|
u_sha3 |
96.50 |
98.83 |
95.67 |
100.00 |
88.10 |
96.40 |
100.00 |
u_keccak |
94.72 |
98.81 |
98.84 |
100.00 |
73.33 |
97.36 |
100.00 |
u_keccak_p |
99.30 |
100.00 |
98.75 |
|
|
98.45 |
100.00 |
g_2share_chi.g_chi_w[0].u_dom |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_inner_domain_regs.u_prim_flop_tab01 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_flop_t01 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_xor_q01 |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_xor_t01 |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
g_2share_chi.g_chi_w[1].u_dom |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_inner_domain_regs.u_prim_flop_tab01 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_flop_t01 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_xor_q01 |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_xor_t01 |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
g_2share_chi.g_chi_w[2].u_dom |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_inner_domain_regs.u_prim_flop_tab01 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_flop_t01 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_xor_q01 |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_xor_t01 |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
g_2share_chi.g_chi_w[3].u_dom |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_inner_domain_regs.u_prim_flop_tab01 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_flop_t01 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_xor_q01 |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_xor_t01 |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
g_2share_chi.g_chi_w[4].u_dom |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_inner_domain_regs.u_prim_flop_tab01 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_flop_t01 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_xor_q01 |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_xor_t01 |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_sec_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_round_count |
100.00 |
|
|
100.00 |
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_pad |
96.34 |
99.45 |
88.37 |
100.00 |
94.44 |
95.79 |
100.00 |
u_prefix_slicer |
100.00 |
100.00 |
|
|
|
|
100.00 |
u_sentmsg_count |
100.00 |
|
|
100.00 |
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sha3_done_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_prim_buf.u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_staterd |
89.71 |
89.72 |
80.83 |
|
|
88.30 |
100.00 |
gen_slicer[0].u_state_slice |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_slicer[1].u_state_slice |
100.00 |
100.00 |
|
|
|
|
100.00 |
u_tlul_adapter |
89.48 |
89.12 |
81.30 |
|
|
87.50 |
100.00 |
u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_reqfifo |
87.85 |
95.00 |
73.08 |
|
|
83.33 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
81.94 |
88.89 |
|
|
|
75.00 |
|
u_rsp_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
u_rspfifo |
89.12 |
95.00 |
76.47 |
|
|
85.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
81.94 |
88.89 |
|
|
|
75.00 |
|
u_sram_byte |
100.00 |
100.00 |
|
|
|
|
|
u_sramreqfifo |
86.89 |
95.00 |
69.23 |
|
|
83.33 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
81.94 |
88.89 |
|
|
|
75.00 |
|
u_tlul_data_integ_enc_data |
0.00 |
0.00 |
|
|
|
|
|
u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
u_tlul_data_integ_enc_instr |
0.00 |
0.00 |
|
|
|
|
|
u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
u_tlul_adapter_msgfifo |
79.67 |
86.78 |
73.83 |
|
|
76.83 |
81.25 |
u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_reqfifo |
87.85 |
95.00 |
73.08 |
|
|
83.33 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
81.94 |
88.89 |
|
|
|
75.00 |
|
u_rsp_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
u_rspfifo |
68.01 |
91.43 |
51.85 |
|
|
68.75 |
60.00 |
gen_normal_fifo.u_fifo_cnt |
76.67 |
86.67 |
|
|
|
66.67 |
|
u_sram_byte |
100.00 |
100.00 |
|
|
|
|
|
u_sramreqfifo |
64.11 |
86.11 |
47.83 |
|
|
62.50 |
60.00 |
gen_normal_fifo.u_fifo_cnt |
76.67 |
86.67 |
|
|
|
66.67 |
|
u_tlul_data_integ_enc_data |
0.00 |
0.00 |
|
|
|
|
|
u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
u_tlul_data_integ_enc_instr |
0.00 |
0.00 |
|
|
|
|
|
u_data_gen |
0.00 |
0.00 |
|
|
|
|
|