Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1693098	0	0
entropy_period_rd_A	2147483647	3442	0	0
intr_enable_rd_A	2147483647	3950	0	0
prefix_0_rd_A	2147483647	3258	0	0
prefix_10_rd_A	2147483647	3194	0	0
prefix_1_rd_A	2147483647	3331	0	0
prefix_2_rd_A	2147483647	3213	0	0
prefix_3_rd_A	2147483647	3219	0	0
prefix_4_rd_A	2147483647	3037	0	0
prefix_5_rd_A	2147483647	3378	0	0
prefix_6_rd_A	2147483647	3309	0	0
prefix_7_rd_A	2147483647	3232	0	0
prefix_8_rd_A	2147483647	3155	0	0
prefix_9_rd_A	2147483647	3155	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1693098	0	0
T47	9841	2	0	0
T48	12517	0	0	0
T49	2606	0	0	0
T50	3537	279	0	0
T51	1179	0	0	0
T52	10438	0	0	0
T53	1642	0	0	0
T54	0	18	0	0
T55	847	0	0	0
T56	0	226	0	0
T57	0	214	0	0
T59	0	286	0	0
T60	0	20	0	0
T62	10795	0	0	0
T63	2214	0	0	0
T65	0	2	0	0
T108	0	3	0	0
T109	0	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3442	0	0
T48	12517	95	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	30	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	45	0	0
T63	2214	4	0	0
T64	734	0	0	0
T65	0	92	0	0
T80	0	9	0	0
T90	0	51	0	0
T92	0	8	0	0
T130	0	20	0	0
T131	0	115	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3950	0	0
T2	1260	13	0	0
T3	1331	0	0	0
T47	9841	0	0	0
T48	12517	109	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	30	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	0	43	0	0
T63	0	1	0	0
T65	0	147	0	0
T80	0	8	0	0
T92	0	8	0	0
T132	0	18	0	0
T133	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3258	0	0
T48	12517	51	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	11	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	19	0	0
T63	2214	1	0	0
T64	734	0	0	0
T65	0	85	0	0
T80	0	10	0	0
T90	0	31	0	0
T92	0	8	0	0
T130	0	94	0	0
T131	0	216	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3194	0	0
T48	12517	40	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	6	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	41	0	0
T63	2214	5	0	0
T64	734	0	0	0
T65	0	76	0	0
T80	0	15	0	0
T90	0	32	0	0
T92	0	4	0	0
T130	0	112	0	0
T131	0	235	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3331	0	0
T48	12517	35	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	14	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	23	0	0
T63	2214	5	0	0
T64	734	0	0	0
T65	0	99	0	0
T80	0	3	0	0
T90	0	38	0	0
T92	0	1	0	0
T130	0	44	0	0
T131	0	214	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3213	0	0
T48	12517	44	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	28	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	20	0	0
T63	2214	1	0	0
T64	734	0	0	0
T65	0	81	0	0
T80	0	9	0	0
T90	0	35	0	0
T92	0	9	0	0
T130	0	42	0	0
T131	0	215	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3219	0	0
T48	12517	50	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	19	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	16	0	0
T63	2214	7	0	0
T64	734	0	0	0
T65	0	77	0	0
T80	0	13	0	0
T90	0	28	0	0
T92	0	7	0	0
T130	0	16	0	0
T131	0	218	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3037	0	0
T48	12517	45	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	28	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	19	0	0
T63	2214	5	0	0
T64	734	0	0	0
T65	0	91	0	0
T80	0	7	0	0
T90	0	35	0	0
T92	0	9	0	0
T130	0	51	0	0
T131	0	209	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3378	0	0
T48	12517	52	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	51	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	25	0	0
T63	2214	9	0	0
T64	734	0	0	0
T65	0	83	0	0
T80	0	22	0	0
T90	0	55	0	0
T92	0	13	0	0
T130	0	1	0	0
T131	0	212	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3309	0	0
T48	12517	38	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	12	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	43	0	0
T63	2214	3	0	0
T64	734	0	0	0
T65	0	103	0	0
T80	0	7	0	0
T90	0	19	0	0
T92	0	9	0	0
T130	0	85	0	0
T131	0	200	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3232	0	0
T48	12517	51	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	40	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	35	0	0
T63	2214	10	0	0
T64	734	0	0	0
T65	0	93	0	0
T80	0	10	0	0
T90	0	26	0	0
T92	0	8	0	0
T130	0	5	0	0
T131	0	183	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3155	0	0
T48	12517	28	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	33	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	18	0	0
T63	2214	7	0	0
T64	734	0	0	0
T65	0	83	0	0
T80	0	6	0	0
T90	0	55	0	0
T92	0	6	0	0
T130	0	17	0	0
T131	0	211	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3155	0	0
T48	12517	30	0	0
T49	2606	0	0	0
T50	3537	0	0	0
T51	1179	0	0	0
T52	10438	17	0	0
T53	1642	0	0	0
T55	847	0	0	0
T62	10795	22	0	0
T63	2214	8	0	0
T64	734	0	0	0
T65	0	92	0	0
T80	0	6	0	0
T90	0	25	0	0
T92	0	5	0	0
T130	0	59	0	0
T131	0	221	0	0