Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	118402885	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1266	1266	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118402885	0	0
T50	3537	325	0	0
T51	1179	0	0	0
T52	10438	0	0	0
T53	1642	0	0	0
T54	1611	515	0	0
T55	847	0	0	0
T56	0	395	0	0
T57	0	385	0	0
T58	0	153	0	0
T59	0	455	0	0
T60	0	536	0	0
T62	10795	0	0	0
T63	2214	149	0	0
T64	734	0	0	0
T65	26376	0	0	0
T66	0	280	0	0
T67	0	162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1266	1266	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	219586230	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1266	1266	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	219586230	0	0
T50	3537	279	0	0
T51	1179	0	0	0
T52	10438	0	0	0
T53	1642	0	0	0
T54	1611	281	0	0
T55	847	0	0	0
T56	0	332	0	0
T57	0	327	0	0
T58	0	141	0	0
T59	0	361	0	0
T60	0	287	0	0
T62	10795	0	0	0
T63	2214	315	0	0
T64	734	0	0	0
T65	26376	0	0	0
T66	0	256	0	0
T67	0	149	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1266	1266	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	333227114	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1266	1266	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333227114	0	0
T1	44506	7558	0	0
T2	1260	22	0	0
T3	1331	40	0	0
T47	9841	1442	0	0
T48	12517	3819	0	0
T49	2606	278	0	0
T50	3537	1007	0	0
T51	1179	40	0	0
T52	10438	2138	0	0
T53	1642	266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1266	1266	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	625820906	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1266	1266	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	625820906	0	0
T1	44506	6965	0	0
T2	1260	87	0	0
T3	1331	40	0	0
T47	9841	1340	0	0
T48	12517	7100	0	0
T49	2606	263	0	0
T50	3537	676	0	0
T51	1179	40	0	0
T52	10438	3957	0	0
T53	1642	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44506	44416	0	0
T2	1260	1166	0	0
T3	1331	1277	0	0
T47	9841	9112	0	0
T48	12517	11646	0	0
T49	2606	2539	0	0
T50	3537	3441	0	0
T51	1179	1110	0	0
T52	10438	10366	0	0
T53	1642	1254	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1266	1266	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0