Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	263774920	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

188462164

1

T1

11

T2

198

T3

128

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	234415929	1			T1	11		T2	120		T3	123
values[0x0]	104496962	1			T1	5		T2	51		T3	122
values[0x1]	113324193	1			T1	6		T2	69		T3	203

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	204740740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

247496344

1

T1

12

T2

207

T3

249

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1274556	1			T3	4		T58	4		T60	22
valid_sources[0x01]	2079506	1			T57	1		T58	2		T61	2
valid_sources[0x02]	1735843	1			T2	2		T58	6		T59	23
valid_sources[0x03]	3249798	1			T3	4		T58	6		T70	7
valid_sources[0x04]	1285206	1			T2	2		T3	1		T58	4
valid_sources[0x05]	3244872	1			T3	4		T58	9		T61	3
valid_sources[0x06]	1268474	1			T3	2		T58	10		T61	1
valid_sources[0x07]	1943423	1			T3	1		T58	6		T61	1
valid_sources[0x08]	1274090	1			T2	2		T3	1		T58	4
valid_sources[0x09]	1266769	1			T2	2		T3	2		T57	1
valid_sources[0x0a]	3594352	1			T2	1		T3	2		T58	3
valid_sources[0x0b]	1323035	1			T57	1		T58	8		T61	2
valid_sources[0x0c]	2390230	1			T3	1		T58	6		T61	1
valid_sources[0x0d]	1726414	1			T3	4		T56	22		T58	2
valid_sources[0x0e]	1275232	1			T3	1		T57	2		T58	5
valid_sources[0x0f]	1271976	1			T3	2		T58	7		T61	2
valid_sources[0x10]	1275406	1			T3	2		T58	4		T61	2
valid_sources[0x11]	1438916	1			T3	1		T58	4		T70	2
valid_sources[0x12]	2198412	1			T2	2		T3	5		T58	7
valid_sources[0x13]	1930603	1			T3	2		T58	4		T61	4
valid_sources[0x14]	2107018	1			T58	5		T73	28		T90	4
valid_sources[0x15]	1275903	1			T2	2		T3	1		T58	4
valid_sources[0x16]	1447462	1			T2	1		T58	4		T64	28
valid_sources[0x17]	1298558	1			T1	2		T3	3		T58	6
valid_sources[0x18]	5212369	1			T3	1		T57	1		T58	10
valid_sources[0x19]	1285846	1			T3	1		T58	7		T61	1
valid_sources[0x1a]	1272171	1			T3	1		T57	2		T58	2
valid_sources[0x1b]	1732430	1			T3	3		T58	4		T61	1
valid_sources[0x1c]	3236988	1			T58	5		T61	1		T72	6
valid_sources[0x1d]	1270636	1			T3	2		T58	4		T61	1
valid_sources[0x1e]	2168818	1			T3	2		T58	4		T60	6
valid_sources[0x1f]	1267509	1			T3	2		T58	4		T59	35
valid_sources[0x20]	1264802	1			T3	2		T58	3		T61	1
valid_sources[0x21]	2779469	1			T3	1		T58	7		T61	5
valid_sources[0x22]	2639006	1			T3	5		T58	7		T61	2
valid_sources[0x23]	1391515	1			T3	2		T58	10		T61	2
valid_sources[0x24]	1273624	1			T3	1		T58	2		T70	1
valid_sources[0x25]	1556597	1			T3	2		T58	6		T61	3
valid_sources[0x26]	1277006	1			T3	2		T58	4		T70	1
valid_sources[0x27]	3615756	1			T2	1		T3	1		T58	2
valid_sources[0x28]	1269778	1			T3	2		T58	9		T60	6
valid_sources[0x29]	1277506	1			T3	1		T58	5		T59	11
valid_sources[0x2a]	2181255	1			T2	16		T3	4		T58	5
valid_sources[0x2b]	1302908	1			T3	2		T58	5		T70	4
valid_sources[0x2c]	3455117	1			T2	1		T3	3		T58	2
valid_sources[0x2d]	1449241	1			T2	1		T3	1		T58	3
valid_sources[0x2e]	1275603	1			T3	2		T58	2		T72	3
valid_sources[0x2f]	1300097	1			T2	1		T3	1		T58	3
valid_sources[0x30]	1284625	1			T3	1		T58	9		T61	1
valid_sources[0x31]	3266504	1			T2	3		T3	1		T58	6
valid_sources[0x32]	1270299	1			T58	4		T59	51		T70	1
valid_sources[0x33]	1928416	1			T3	4		T58	3		T59	58
valid_sources[0x34]	1276744	1			T3	2		T57	4		T58	7
valid_sources[0x35]	1273781	1			T3	1		T58	5		T60	6
valid_sources[0x36]	1271509	1			T3	2		T58	4		T61	2
valid_sources[0x37]	3634957	1			T2	3		T3	2		T58	4
valid_sources[0x38]	2390353	1			T3	2		T58	7		T70	1
valid_sources[0x39]	1348124	1			T2	7		T3	3		T58	4
valid_sources[0x3a]	2705273	1			T2	7		T3	3		T57	2
valid_sources[0x3b]	1276323	1			T1	1		T3	2		T58	10
valid_sources[0x3c]	1465637	1			T2	6		T58	5		T61	1
valid_sources[0x3d]	3215936	1			T3	2		T58	6		T59	8
valid_sources[0x3e]	1327442	1			T3	2		T57	1		T58	9
valid_sources[0x3f]	3712702	1			T1	3		T58	11		T60	20
valid_sources[0x40]	1921430	1			T58	4		T60	3		T61	2
valid_sources[0x41]	1829368	1			T3	1		T58	5		T61	2
valid_sources[0x42]	1312433	1			T3	1		T58	8		T61	1
valid_sources[0x43]	1275200	1			T1	1		T2	1		T3	2
valid_sources[0x44]	3621601	1			T3	1		T58	7		T61	5
valid_sources[0x45]	1610869	1			T3	3		T58	5		T70	1
valid_sources[0x46]	2189705	1			T3	2		T58	5		T61	1
valid_sources[0x47]	1272579	1			T2	1		T3	2		T58	7
valid_sources[0x48]	1278561	1			T2	1		T3	3		T58	9
valid_sources[0x49]	1272766	1			T2	3		T3	1		T58	4
valid_sources[0x4a]	1930087	1			T2	1		T3	2		T58	5
valid_sources[0x4b]	1279511	1			T3	3		T58	6		T70	2
valid_sources[0x4c]	4466990	1			T3	3		T57	2		T58	3
valid_sources[0x4d]	1274113	1			T2	6		T3	1		T58	4
valid_sources[0x4e]	1278761	1			T2	4		T3	1		T58	6
valid_sources[0x4f]	1270538	1			T3	1		T58	5		T70	2
valid_sources[0x50]	1271137	1			T3	1		T58	5		T61	1
valid_sources[0x51]	1323269	1			T3	1		T58	4		T61	4
valid_sources[0x52]	1269539	1			T3	1		T58	4		T61	1
valid_sources[0x53]	1266704	1			T3	4		T58	3		T59	23
valid_sources[0x54]	2122104	1			T3	3		T58	2		T70	1
valid_sources[0x55]	1274156	1			T3	4		T58	4		T61	1
valid_sources[0x56]	1282217	1			T1	1		T58	2		T61	1
valid_sources[0x57]	1273279	1			T3	1		T58	4		T59	53
valid_sources[0x58]	1274226	1			T3	2		T58	3		T61	1
valid_sources[0x59]	1281643	1			T2	1		T58	6		T61	4
valid_sources[0x5a]	3329401	1			T2	6		T3	3		T57	1
valid_sources[0x5b]	3632103	1			T3	2		T57	1		T58	3
valid_sources[0x5c]	1270158	1			T3	2		T58	5		T60	44
valid_sources[0x5d]	3632666	1			T1	1		T2	4		T3	3
valid_sources[0x5e]	3694226	1			T2	8		T3	3		T58	9
valid_sources[0x5f]	2123242	1			T3	2		T58	6		T61	1
valid_sources[0x60]	1423337	1			T3	2		T58	3		T61	2
valid_sources[0x61]	3586296	1			T3	2		T58	5		T69	3
valid_sources[0x62]	1267810	1			T2	5		T3	1		T58	3
valid_sources[0x63]	1271226	1			T3	1		T58	5		T60	9
valid_sources[0x64]	1348669	1			T58	4		T61	3		T73	46
valid_sources[0x65]	1940649	1			T3	5		T58	8		T61	1
valid_sources[0x66]	1270185	1			T1	1		T3	4		T58	6
valid_sources[0x67]	1274695	1			T3	1		T58	5		T61	2
valid_sources[0x68]	1274583	1			T2	4		T3	3		T58	4
valid_sources[0x69]	2225285	1			T3	1		T58	4		T60	2
valid_sources[0x6a]	2348822	1			T3	1		T58	4		T70	1
valid_sources[0x6b]	1273316	1			T2	1		T57	4		T58	8
valid_sources[0x6c]	1273153	1			T3	2		T58	4		T71	4
valid_sources[0x6d]	3604443	1			T3	3		T58	8		T59	13
valid_sources[0x6e]	1486436	1			T1	1		T57	2		T58	3
valid_sources[0x6f]	1268041	1			T2	2		T3	1		T58	4
valid_sources[0x70]	1270847	1			T3	5		T58	1		T59	10
valid_sources[0x71]	4061733	1			T3	2		T58	7		T60	3
valid_sources[0x72]	1504538	1			T2	1		T58	6		T61	2
valid_sources[0x73]	2086574	1			T3	2		T58	6		T61	2
valid_sources[0x74]	1275645	1			T2	3		T58	6		T60	9
valid_sources[0x75]	1346165	1			T3	2		T58	9		T61	1
valid_sources[0x76]	1271681	1			T3	1		T58	7		T59	14
valid_sources[0x77]	1287251	1			T2	2		T3	1		T58	4
valid_sources[0x78]	1278065	1			T3	1		T58	8		T61	2
valid_sources[0x79]	1273794	1			T3	2		T58	5		T60	17
valid_sources[0x7a]	1735898	1			T3	1		T58	8		T59	20
valid_sources[0x7b]	1267487	1			T2	2		T3	2		T58	5
valid_sources[0x7c]	1268796	1			T3	1		T58	7		T61	2
valid_sources[0x7d]	2178694	1			T3	4		T58	5		T61	4
valid_sources[0x7e]	1274731	1			T1	1		T2	1		T3	1
valid_sources[0x7f]	1643438	1			T2	4		T58	5		T61	2
valid_sources[0x80]	2665805	1			T3	3		T58	2		T61	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73222941

1

T1

5

T2

85

T3

69

values[0x0]

all_enables

biggest_size

61891666

1

T1

2

T2

50

T3

29

values[0x1]

all_enables

biggest_size

53347557

1

T1

4

T2

63

T3

30