Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

270842663

1

T1

11

T2

42

T3

320

full_word

188899562

1

T1

11

T2

198

T3

128

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	459741965	1			T1	22		T2	240		T3	448
auto[TlIntgErrCmd]	84	1			T59	2		T116	2		T117	3
auto[TlIntgErrData]	93	1			T59	3		T116	5		T117	6
auto[TlIntgErrBoth]	83	1			T59	5		T116	3		T117	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235760414

1

T1

11

T2

120

T3

123

auto[1]

223981811

1

T1

11

T2

120

T3

325

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	162428219	1			T1	6		T2	35		T3	54
auto[TlIntgErrNone]	partial	auto[1]	108414201	1			T1	5		T2	7		T3	266
auto[TlIntgErrNone]	full_word	auto[0]	73332068	1			T1	5		T2	85		T3	69
auto[TlIntgErrNone]	full_word	auto[1]	115567477	1			T1	6		T2	113		T3	59
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T59	1		T116	1		T117	2
auto[TlIntgErrCmd]	partial	auto[1]	36	1			T59	1		T117	1		T119	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T153	1		T155	1		T156	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T116	1		T118	1		T157	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T59	1		T116	4		T117	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T59	2		T116	1		T117	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T157	1		T156	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T158	1		T159	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T59	1		T116	2		T117	1
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T59	4		T116	1		T119	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T153	1		T160	1		T158	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T118	1		T155	1		T152	1