Unified Coverage Report :: Module :: sha3pad

Module : sha3pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.89	99.41	88.37		80.95	95.70	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_pad	95.59	99.41	88.37		94.44	95.70	100.00

---

Module Instance : tb.dut.u_sha3.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	99.41	88.37		94.44	95.70	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.34	99.45	88.37	100.00	94.44	95.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.09	97.30	81.25		100.00	91.89	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prefix_slicer	100.00	100.00					100.00
u_sentmsg_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
ALWAYS	157	6	6	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
ALWAYS	266	6	6	100.00
ALWAYS	278	3	3	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	292	3	3	100.00
ALWAYS	297	76	75	98.68
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
ALWAYS	557	4	4	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
ALWAYS	590	5	5	100.00
ALWAYS	602	5	5	100.00
ALWAYS	614	5	5	100.00
ALWAYS	663	10	10	100.00
ALWAYS	679	17	17	100.00
ALWAYS	778	6	6	100.00
ALWAYS	787	6	6	100.00
ALWAYS	797	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
208	1	1
212	1	1
235	1	1
241	1	1
246	1	1
256	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
			MISSING_ELSE
278	3	3
285	1	1
292	2	2
293	1	1
297	1	1
300	1	1
301	1	1
303	1	1
305	1	1
306	1	1
308	1	1
309	1	1
311	1	1
313	1	1
315	1	1
324	1	1
326	1	1
327	1	1
329	1	1
332	1	1
344	1	1
346	1	1
347	1	1
349	1	1
350	1	1
351	1	1
353	1	1
355	1	1
360	1	1
362	1	1
363	1	1
365	1	1
374	1	1
376	1	1
377	1	1
379	1	1
380	1	1
382	1	1
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
391	1	1
393	1	1
399	1	1
401	1	1
402	1	1
404	1	1
413	1	1
415	1	1
417	1	1
420	1	1
423	1	1
424	1	1
425	1	1
426	1	1
427	1	1
429	0	1
434	1	1
436	1	1
437	1	1
446	1	1
450	1	1
451	1	1
453	1	1
454	1	1
455	1	1
457	1	1
459	1	1
465	1	1
466	1	1
468	1	1
469	1	1
471	1	1
473	1	1
479	1	1
480	1	1
493	1	1
494	1	1
			MISSING_ELSE
508	1	1
519	1	1
537	1	1
557	1	1
558	1	1
559	1	1
560	1	1
577	1	1
587	1	1
590	1	1
591	1	1
592	1	1
593	1	1
594	1	1
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
614	1	1
615	1	1
616	1	1
617	1	1
618	1	1
663	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
670	1	1
671	1	1
672	1	1
673	1	1
			MISSING_ELSE
679	1	1
681	1	1
682	1	1
685	1	1
686	1	1
689	1	1
690	1	1
693	1	1
694	1	1
697	1	1
698	1	1
701	1	1
702	1	1
705	1	1
706	1	1
709	1	1
710	1	1
778	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
787	1	1
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
			MISSING_ELSE
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       212
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       235
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       235
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       241
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       241
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       246
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       256
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       285
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       285
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       376
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       387
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T23,T10

 LINE       417
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T23,T10

 LINE       587
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       603
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T48,T49
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       615
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Not Covered

 LINE       615
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

FSM Coverage for Module : sha3pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	21	17	80.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	329	Covered	T1
StMessageWait	382	Covered	T1
StPad	388	Covered	T1
StPad01	426	Covered	T1
StPadFlush	434	Covered	T1
StPadIdle	332	Covered	T1
StPadRun	420	Covered	T1
StPrefix	327	Covered	T1
StPrefixWait	347	Covered	T1
StTerminalError	494	Covered	T1

transitions	Line No.	Covered	Tests
StMessage->StMessageWait	382	Covered	T1
StMessage->StPad	388	Covered	T1
StMessage->StTerminalError	494	Covered	T1
StMessageWait->StMessage	402	Covered	T1
StMessageWait->StTerminalError	494	Covered	T1
StPad->StPad01	426	Covered	T1
StPad->StPadRun	420	Covered	T1
StPad->StTerminalError	494	Not Covered
StPad01->StPadFlush	451	Covered	T1
StPad01->StTerminalError	494	Not Covered
StPadFlush->StPadIdle	469	Covered	T1
StPadFlush->StTerminalError	494	Not Covered
StPadIdle->StMessage	329	Covered	T1
StPadIdle->StPrefix	327	Covered	T1
StPadIdle->StTerminalError	494	Covered	T1
StPadRun->StPadFlush	434	Covered	T1
StPadRun->StTerminalError	494	Not Covered
StPrefix->StPrefixWait	347	Covered	T1
StPrefix->StTerminalError	494	Covered	T1
StPrefixWait->StMessage	363	Covered	T1
StPrefixWait->StTerminalError	494	Covered	T1

---

Branch Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	212	2	2	100.00
TERNARY	235	2	2	100.00
TERNARY	241	2	2	100.00
TERNARY	285	2	2	100.00
TERNARY	587	2	2	100.00
CASE	157	6	5	83.33
IF	266	4	4	100.00
IF	278	2	2	100.00
IF	292	2	2	100.00
CASE	315	23	22	95.65
IF	493	2	2	100.00
CASE	557	4	3	75.00
CASE	590	5	5	100.00
CASE	602	5	5	100.00
CASE	614	5	5	100.00
IF	663	4	4	100.00
IF	778	4	4	100.00
IF	787	4	4	100.00
IF	797	4	4	100.00
CASE	679	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	235	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	241	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	285	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	587	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T4,T23,T11
L256	Covered	T4,T5,T6
L384	Covered	T4,T11,T25
L512	Covered	T4,T25,T28
default	Not Covered

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if (process_i)
-3-:	270	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	case (st)
-2-:	324	if (start_i)
-3-:	326	if (mode_eq_cshake)
-4-:	346	if (sent_blocksize)
-5-:	362	if (keccak_complete_i)
-6-:	376	if ((msg_valid_i && msg_partial))
-7-:	380	if (sent_blocksize)
-8-:	387	if ((process_latched || process_i))
-9-:	401	if (keccak_complete_i)
-10-:	417	if ((keccak_ack && end_of_block))
-11-:	425	if (keccak_ack)
-12-:	450	if (sent_blocksize)
-13-:	468	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T23,T10
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T4,T5,T6
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T5,T6
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T5,T6
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T4,T23,T10
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T4,T5,T6
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T23,T10
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T5,T6
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T5,T6
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	493	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	557	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T4,T5,T6
Shake	Covered	T4,T10,T11
CShake	Covered	T4,T5,T6
default	Not Covered

	LineNo.	Expression
-1-:	590	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T5,T6
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	602	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T5,T6
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	614	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T5,T6
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	663	if ((!rst_ni))
-2-:	666	if (en_msgbuf)
-3-:	671	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	778	if ((!rst_ni))
-2-:	780	if (start_i)
-3-:	782	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	787	if ((!rst_ni))
-2-:	789	if (start_i)
-3-:	791	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	797	if ((!rst_ni))
-2-:	799	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	801	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	679	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T4,T5,T6
7'b0000001	Covered	T4,T23,T10
7'b0000011	Covered	T4,T5,T23
7'b0000111	Covered	T4,T6,T23
7'b0001111	Covered	T4,T23,T10
7'b0011111	Covered	T4,T23,T10
7'b0111111	Covered	T4,T5,T23
7'b1111111	Covered	T4,T6,T23
default	Not Covered

---

Assert Coverage for Module : sha3pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	347258	0	0
AlwaysPartialMsgBuf_M	2147483647	199293	0	0
CompleteBlockWhenProcess_A	2147483647	335083	0	0
DoneCondition_M	2147483647	347236	0	0
DonePulse_A	2147483647	347236	0	0
KeccakAddrInRange_A	2147483647	53217237	0	0
KeccakRunPulse_A	2147483647	3084169	0	0
MessageCondition_M	2147483647	48451002	0	0
ModeStableDuringOp_M	2147483647	36271	0	0
MsgReadyCondition_A	2147483647	2147483647	0	0
MsgWidthidth_A	1041	1041	0	0
NoPartialMsgFifo_M	2147483647	48251709	0	0
Pad01NotAttheEndOfBlock_A	2147483647	336557	0	0
PartialEndOfMsg_M	2147483647	199293	0	0
PrefixLessThanBlock_A	1041	1041	0	0
ProcessCondition_M	2147483647	347259	0	0
ProcessPulse_A	2147483647	347259	0	0
StartCondition_M	2147483647	347372	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	347372	0	0
StrengthStableDuringOp_M	2147483647	43024	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347258	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	332	0	0
T38	0	9	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	199293	0	0
T4	705263	426	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	890	0	0
T11	312238	164	0	0
T23	981011	340	0	0
T24	1389	0	0	0
T25	658187	71	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	292	0	0
T38	0	9	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335083	0	0
T4	705263	476	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2211	0	0
T11	312238	190	0	0
T23	981011	372	0	0
T24	1389	0	0	0
T25	658187	76	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	325	0	0
T38	0	9	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347236	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	331	0	0
T38	0	9	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347236	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	331	0	0
T38	0	9	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	53217237	0	0
T4	705263	94150	0	0
T5	21269	607	0	0
T6	24271	607	0	0
T10	150036	220643	0	0
T11	312238	58220	0	0
T23	981011	99756	0	0
T24	1389	0	0	0
T25	658187	7739	0	0
T26	11107	607	0	0
T27	1400	0	0	0
T28	0	39828	0	0
T38	0	607	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3084169	0	0
T4	705263	5051	0	0
T5	21269	31	0	0
T6	24271	31	0	0
T10	150036	12979	0	0
T11	312238	3096	0	0
T23	981011	5542	0	0
T24	1389	0	0	0
T25	658187	431	0	0
T26	11107	31	0	0
T27	1400	0	0	0
T28	0	2057	0	0
T38	0	31	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48451002	0	0
T4	705263	81771	0	0
T5	21269	286	0	0
T6	24271	286	0	0
T10	150036	195716	0	0
T11	312238	53133	0	0
T23	981011	96112	0	0
T24	1389	0	0	0
T25	658187	6077	0	0
T26	11107	286	0	0
T27	1400	0	0	0
T28	0	30445	0	0
T38	0	286	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36271	0	0
T4	705263	286	0	0
T5	21269	1	0	0
T6	24271	1	0	0
T10	150036	1	0	0
T11	312238	81	0	0
T23	981011	0	0	0
T24	1389	0	0	0
T25	658187	84	0	0
T26	11107	1	0	0
T27	1400	0	0	0
T28	0	157	0	0
T29	0	1	0	0
T38	0	1	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	705263	475413	0	0
T5	21269	7569	0	0
T6	24271	8517	0	0
T10	150036	117081	0	0
T11	312238	708486	0	0
T23	981011	898348	0	0
T24	1389	0	0	0
T25	658187	417843	0	0
T26	11107	997	0	0
T27	1400	0	0	0
T28	0	486816	0	0
T38	0	1146	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48251709	0	0
T4	705263	81345	0	0
T5	21269	277	0	0
T6	24271	277	0	0
T10	150036	194826	0	0
T11	312238	52969	0	0
T23	981011	95772	0	0
T24	1389	0	0	0
T25	658187	6006	0	0
T26	11107	277	0	0
T27	1400	0	0	0
T28	0	30153	0	0
T38	0	277	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	336557	0	0
T4	705263	480	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2217	0	0
T11	312238	190	0	0
T23	981011	374	0	0
T24	1389	0	0	0
T25	658187	78	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	326	0	0
T38	0	9	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	199293	0	0
T4	705263	426	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	890	0	0
T11	312238	164	0	0
T23	981011	340	0	0
T24	1389	0	0	0
T25	658187	71	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	292	0	0
T38	0	9	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347259	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	332	0	0
T38	0	9	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347259	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	332	0	0
T38	0	9	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347372	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	195	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	333	0	0
T38	0	9	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	705263	705170	0	0
T5	21269	21171	0	0
T6	24271	24190	0	0
T10	150036	150035	0	0
T11	312238	312230	0	0
T23	981011	981001	0	0
T24	1389	1327	0	0
T25	658187	658092	0	0
T26	11107	11015	0	0
T27	1400	1347	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347372	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	195	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	333	0	0
T38	0	9	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43024	0	0
T4	705263	381	0	0
T5	21269	2	0	0
T6	24271	2	0	0
T10	150036	2	0	0
T11	312238	113	0	0
T23	981011	2	0	0
T24	1389	1	0	0
T25	658187	90	0	0
T26	11107	2	0	0
T27	1400	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	705263	705170	0	0
T5	21269	21171	0	0
T6	24271	24190	0	0
T10	150036	150035	0	0
T11	312238	312230	0	0
T23	981011	981001	0	0
T24	1389	1327	0	0
T25	658187	658092	0	0
T26	11107	11015	0	0
T27	1400	1347	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	33723197	0
StMessageFeed_C	2147483647	2147483647	0
StPadSendMsg_C	2147483647	3859408	0
StPad_C	2147483647	336557	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	33723197	0
T4	705263	48209	0
T5	21269	873	0
T6	24271	873	0
T10	150036	219713	0
T11	312238	18818	0
T23	981011	37830	0
T24	1389	0	0
T25	658187	8051	0
T26	11107	873	0
T27	1400	0	0
T28	0	32204	0
T38	0	873	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2147483647	0
T4	705263	475882	0
T5	21269	7591	0
T6	24271	8539	0
T10	150036	117211	0
T11	312238	711430	0
T23	981011	898903	0
T24	1389	0	0
T25	658187	418225	0
T26	11107	1019	0
T27	1400	0	0
T28	0	488607	0
T38	0	1168	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3859408	0
T4	705263	5378	0
T5	21269	144	0
T6	24271	144	0
T10	150036	23552	0
T11	312238	2181	0
T23	981011	3594	0
T24	1389	0	0
T25	658187	745	0
T26	11107	144	0
T27	1400	0	0
T28	0	4189	0
T38	0	144	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	336557	0
T4	705263	480	0
T5	21269	9	0
T6	24271	9	0
T10	150036	2217	0
T11	312238	190	0
T23	981011	374	0
T24	1389	0	0
T25	658187	78	0
T26	11107	9	0
T27	1400	0	0
T28	0	326	0
T38	0	9	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
ALWAYS	157	6	6	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
ALWAYS	266	6	6	100.00
ALWAYS	278	3	3	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	292	3	3	100.00
ALWAYS	297	76	75	98.68
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
ALWAYS	557	4	4	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
ALWAYS	590	5	5	100.00
ALWAYS	602	5	5	100.00
ALWAYS	614	5	5	100.00
ALWAYS	663	10	10	100.00
ALWAYS	679	17	17	100.00
ALWAYS	778	6	6	100.00
ALWAYS	787	6	6	100.00
ALWAYS	797	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
208	1	1
212	1	1
235	1	1
241	1	1
246	1	1
256	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
			MISSING_ELSE
278	3	3
285	1	1
292	2	2
293	1	1
297	1	1
300	1	1
301	1	1
303	1	1
305	1	1
306	1	1
308	1	1
309	1	1
311	1	1
313	1	1
315	1	1
324	1	1
326	1	1
327	1	1
329	1	1
332	1	1
344	1	1
346	1	1
347	1	1
349	1	1
350	1	1
351	1	1
353	1	1
355	1	1
360	1	1
362	1	1
363	1	1
365	1	1
374	1	1
376	1	1
377	1	1
379	1	1
380	1	1
382	1	1
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
391	1	1
393	1	1
399	1	1
401	1	1
402	1	1
404	1	1
413	1	1
415	1	1
417	1	1
420	1	1
423	1	1
424	1	1
425	1	1
426	1	1
427	1	1
429	0	1
434	1	1
436	1	1
437	1	1
446	1	1
450	1	1
451	1	1
453	1	1
454	1	1
455	1	1
457	1	1
459	1	1
465	1	1
466	1	1
468	1	1
469	1	1
471	1	1
473	1	1
479	1	1
480	1	1
493	1	1
494	1	1
			MISSING_ELSE
508	1	1
519	1	1
537	1	1
557	1	1
558	1	1
559	1	1
560	1	1
577	1	1
587	1	1
590	1	1
591	1	1
592	1	1
593	1	1
594	1	1
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
614	1	1
615	1	1
616	1	1
617	1	1
618	1	1
663	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
670	1	1
671	1	1
672	1	1
673	1	1
			MISSING_ELSE
679	1	1
681	1	1
682	1	1
685	1	1
686	1	1
689	1	1
690	1	1
693	1	1
694	1	1
697	1	1
698	1	1
701	1	1
702	1	1
705	1	1
706	1	1
709	1	1
710	1	1
778	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
787	1	1
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
			MISSING_ELSE
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       212
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       235
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       235
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       241
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       241
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       246
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       256
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       285
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       285
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       376
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       387
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T23,T10

 LINE       417
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T23,T10

 LINE       587
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       603
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T48,T49
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       615
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Not Covered

 LINE       615
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.u_sha3.u_pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	18	17	94.44
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	329	Covered	T1
StMessageWait	382	Covered	T1
StPad	388	Covered	T1
StPad01	426	Covered	T1
StPadFlush	434	Covered	T1
StPadIdle	332	Covered	T1
StPadRun	420	Covered	T1
StPrefix	327	Covered	T1
StPrefixWait	347	Covered	T1
StTerminalError	494	Covered	T1

transitions	Line No.	Covered	Tests	Exclude Annotation
StMessage->StMessageWait	382	Covered	T1
StMessage->StPad	388	Covered	T1
StMessage->StTerminalError	494	Covered	T1
StMessageWait->StMessage	402	Covered	T1
StMessageWait->StTerminalError	494	Covered	T1
StPad->StPad01	426	Covered	T1
StPad->StPadRun	420	Covered	T1
StPad->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPad01->StPadFlush	451	Covered	T1
StPad01->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPadFlush->StPadIdle	469	Covered	T1
StPadFlush->StTerminalError	494	Not Covered
StPadIdle->StMessage	329	Covered	T1
StPadIdle->StPrefix	327	Covered	T1
StPadIdle->StTerminalError	494	Covered	T1
StPadRun->StPadFlush	434	Covered	T1
StPadRun->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefix->StPrefixWait	347	Covered	T1
StPrefix->StTerminalError	494	Covered	T1
StPrefixWait->StMessage	363	Covered	T1
StPrefixWait->StTerminalError	494	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	212	2	2	100.00
TERNARY	235	2	2	100.00
TERNARY	241	2	2	100.00
TERNARY	285	2	2	100.00
TERNARY	587	2	2	100.00
CASE	157	6	5	83.33
IF	266	4	4	100.00
IF	278	2	2	100.00
IF	292	2	2	100.00
CASE	315	23	22	95.65
IF	493	2	2	100.00
CASE	557	4	3	75.00
CASE	590	5	5	100.00
CASE	602	5	5	100.00
CASE	614	5	5	100.00
IF	663	4	4	100.00
IF	778	4	4	100.00
IF	787	4	4	100.00
IF	797	4	4	100.00
CASE	679	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	235	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	241	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	285	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	587	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T4,T23,T11
L256	Covered	T4,T5,T6
L384	Covered	T4,T11,T25
L512	Covered	T4,T25,T28
default	Not Covered

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if (process_i)
-3-:	270	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	case (st)
-2-:	324	if (start_i)
-3-:	326	if (mode_eq_cshake)
-4-:	346	if (sent_blocksize)
-5-:	362	if (keccak_complete_i)
-6-:	376	if ((msg_valid_i && msg_partial))
-7-:	380	if (sent_blocksize)
-8-:	387	if ((process_latched || process_i))
-9-:	401	if (keccak_complete_i)
-10-:	417	if ((keccak_ack && end_of_block))
-11-:	425	if (keccak_ack)
-12-:	450	if (sent_blocksize)
-13-:	468	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T23,T10
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T4,T5,T6
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T5,T6
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T5,T6
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T4,T23,T10
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T4,T5,T6
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T23,T10
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T5,T6
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T5,T6
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	493	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	557	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T4,T5,T6
Shake	Covered	T4,T10,T11
CShake	Covered	T4,T5,T6
default	Not Covered

	LineNo.	Expression
-1-:	590	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T5,T6
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	602	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T5,T6
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	614	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T5,T6
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	663	if ((!rst_ni))
-2-:	666	if (en_msgbuf)
-3-:	671	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	778	if ((!rst_ni))
-2-:	780	if (start_i)
-3-:	782	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	787	if ((!rst_ni))
-2-:	789	if (start_i)
-3-:	791	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	797	if ((!rst_ni))
-2-:	799	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	801	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	679	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T4,T5,T6
7'b0000001	Covered	T4,T23,T10
7'b0000011	Covered	T4,T5,T23
7'b0000111	Covered	T4,T6,T23
7'b0001111	Covered	T4,T23,T10
7'b0011111	Covered	T4,T23,T10
7'b0111111	Covered	T4,T5,T23
7'b1111111	Covered	T4,T6,T23
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	347258	0	0
AlwaysPartialMsgBuf_M	2147483647	199293	0	0
CompleteBlockWhenProcess_A	2147483647	335083	0	0
DoneCondition_M	2147483647	347236	0	0
DonePulse_A	2147483647	347236	0	0
KeccakAddrInRange_A	2147483647	53217237	0	0
KeccakRunPulse_A	2147483647	3084169	0	0
MessageCondition_M	2147483647	48451002	0	0
ModeStableDuringOp_M	2147483647	36271	0	0
MsgReadyCondition_A	2147483647	2147483647	0	0
MsgWidthidth_A	1041	1041	0	0
NoPartialMsgFifo_M	2147483647	48251709	0	0
Pad01NotAttheEndOfBlock_A	2147483647	336557	0	0
PartialEndOfMsg_M	2147483647	199293	0	0
PrefixLessThanBlock_A	1041	1041	0	0
ProcessCondition_M	2147483647	347259	0	0
ProcessPulse_A	2147483647	347259	0	0
StartCondition_M	2147483647	347372	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	347372	0	0
StrengthStableDuringOp_M	2147483647	43024	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347258	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	332	0	0
T38	0	9	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	199293	0	0
T4	705263	426	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	890	0	0
T11	312238	164	0	0
T23	981011	340	0	0
T24	1389	0	0	0
T25	658187	71	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	292	0	0
T38	0	9	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335083	0	0
T4	705263	476	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2211	0	0
T11	312238	190	0	0
T23	981011	372	0	0
T24	1389	0	0	0
T25	658187	76	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	325	0	0
T38	0	9	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347236	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	331	0	0
T38	0	9	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347236	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	331	0	0
T38	0	9	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	53217237	0	0
T4	705263	94150	0	0
T5	21269	607	0	0
T6	24271	607	0	0
T10	150036	220643	0	0
T11	312238	58220	0	0
T23	981011	99756	0	0
T24	1389	0	0	0
T25	658187	7739	0	0
T26	11107	607	0	0
T27	1400	0	0	0
T28	0	39828	0	0
T38	0	607	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3084169	0	0
T4	705263	5051	0	0
T5	21269	31	0	0
T6	24271	31	0	0
T10	150036	12979	0	0
T11	312238	3096	0	0
T23	981011	5542	0	0
T24	1389	0	0	0
T25	658187	431	0	0
T26	11107	31	0	0
T27	1400	0	0	0
T28	0	2057	0	0
T38	0	31	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48451002	0	0
T4	705263	81771	0	0
T5	21269	286	0	0
T6	24271	286	0	0
T10	150036	195716	0	0
T11	312238	53133	0	0
T23	981011	96112	0	0
T24	1389	0	0	0
T25	658187	6077	0	0
T26	11107	286	0	0
T27	1400	0	0	0
T28	0	30445	0	0
T38	0	286	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36271	0	0
T4	705263	286	0	0
T5	21269	1	0	0
T6	24271	1	0	0
T10	150036	1	0	0
T11	312238	81	0	0
T23	981011	0	0	0
T24	1389	0	0	0
T25	658187	84	0	0
T26	11107	1	0	0
T27	1400	0	0	0
T28	0	157	0	0
T29	0	1	0	0
T38	0	1	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	705263	475413	0	0
T5	21269	7569	0	0
T6	24271	8517	0	0
T10	150036	117081	0	0
T11	312238	708486	0	0
T23	981011	898348	0	0
T24	1389	0	0	0
T25	658187	417843	0	0
T26	11107	997	0	0
T27	1400	0	0	0
T28	0	486816	0	0
T38	0	1146	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48251709	0	0
T4	705263	81345	0	0
T5	21269	277	0	0
T6	24271	277	0	0
T10	150036	194826	0	0
T11	312238	52969	0	0
T23	981011	95772	0	0
T24	1389	0	0	0
T25	658187	6006	0	0
T26	11107	277	0	0
T27	1400	0	0	0
T28	0	30153	0	0
T38	0	277	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	336557	0	0
T4	705263	480	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2217	0	0
T11	312238	190	0	0
T23	981011	374	0	0
T24	1389	0	0	0
T25	658187	78	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	326	0	0
T38	0	9	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	199293	0	0
T4	705263	426	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	890	0	0
T11	312238	164	0	0
T23	981011	340	0	0
T24	1389	0	0	0
T25	658187	71	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	292	0	0
T38	0	9	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347259	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	332	0	0
T38	0	9	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347259	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	332	0	0
T38	0	9	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347372	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	195	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	333	0	0
T38	0	9	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	705263	705170	0	0
T5	21269	21171	0	0
T6	24271	24190	0	0
T10	150036	150035	0	0
T11	312238	312230	0	0
T23	981011	981001	0	0
T24	1389	1327	0	0
T25	658187	658092	0	0
T26	11107	11015	0	0
T27	1400	1347	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347372	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	195	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	333	0	0
T38	0	9	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43024	0	0
T4	705263	381	0	0
T5	21269	2	0	0
T6	24271	2	0	0
T10	150036	2	0	0
T11	312238	113	0	0
T23	981011	2	0	0
T24	1389	1	0	0
T25	658187	90	0	0
T26	11107	2	0	0
T27	1400	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	705263	705170	0	0
T5	21269	21171	0	0
T6	24271	24190	0	0
T10	150036	150035	0	0
T11	312238	312230	0	0
T23	981011	981001	0	0
T24	1389	1327	0	0
T25	658187	658092	0	0
T26	11107	11015	0	0
T27	1400	1347	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	33723197	0
StMessageFeed_C	2147483647	2147483647	0
StPadSendMsg_C	2147483647	3859408	0
StPad_C	2147483647	336557	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	33723197	0
T4	705263	48209	0
T5	21269	873	0
T6	24271	873	0
T10	150036	219713	0
T11	312238	18818	0
T23	981011	37830	0
T24	1389	0	0
T25	658187	8051	0
T26	11107	873	0
T27	1400	0	0
T28	0	32204	0
T38	0	873	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2147483647	0
T4	705263	475882	0
T5	21269	7591	0
T6	24271	8539	0
T10	150036	117211	0
T11	312238	711430	0
T23	981011	898903	0
T24	1389	0	0
T25	658187	418225	0
T26	11107	1019	0
T27	1400	0	0
T28	0	488607	0
T38	0	1168	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3859408	0
T4	705263	5378	0
T5	21269	144	0
T6	24271	144	0
T10	150036	23552	0
T11	312238	2181	0
T23	981011	3594	0
T24	1389	0	0
T25	658187	745	0
T26	11107	144	0
T27	1400	0	0
T28	0	4189	0
T38	0	144	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	336557	0
T4	705263	480	0
T5	21269	9	0
T6	24271	9	0
T10	150036	2217	0
T11	312238	190	0
T23	981011	374	0
T24	1389	0	0
T25	658187	78	0
T26	11107	9	0
T27	1400	0	0
T28	0	326	0
T38	0	9	0