Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	347259	0	0
RunThenComplete_M	2147483647	3084129	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347259	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	332	0	0
T38	0	9	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3084129	0	0
T4	705263	5051	0	0
T5	21269	31	0	0
T6	24271	31	0	0
T10	150036	12979	0	0
T11	312238	3096	0	0
T23	981011	5542	0	0
T24	1389	0	0	0
T25	658187	431	0	0
T26	11107	31	0	0
T27	1400	0	0	0
T28	0	2057	0	0
T38	0	31	0	0