Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo.u_packer	98.08	100.00	100.00			92.31	100.00

---

Module Instance : tb.dut.u_msgfifo.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.41	100.00	100.00	89.74		92.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.21	100.00			100.00	92.86	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_pos_dupcnt.u_pos	89.74			89.74

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
ALWAYS	120	3	3	100.00
ALWAYS	156	4	4	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	184	9	9	100.00
ALWAYS	213	8	8	100.00
ALWAYS	234	3	3	100.00
ALWAYS	242	14	14	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	290	0	0
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	298	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
110	1	1
111	1	1
112	1	1
115	1	1
120	1	1
122	1	1
124	1	1
			MISSING_ELSE
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
164	1	1
165	1	1
169	1	1
170	1	1
173	1	1
174	1	1
177	1	1
179	1	1
184	1	1
186	1	1
187	1	1
191	1	1
192	1	1
196	1	1
197	1	1
201	1	1
202	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
234	1	1
235	1	1
237	1	1
242	1	1
244	1	1
245	1	1
247	1	1
249	1	1
250	1	1
252	1	1
257	1	1
258	1	1
260	1	1
261	1	1
263	1	1
265	1	1
266	1	1
278	1	1
282	1	1
290		unreachable
293	1	1
294	1	1
295	1	1
298		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       110
 EXPRESSION (ack_in && ((!ack_out)))
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T11,T25
1	1	Covered	T4,T5,T6

 LINE       111
 EXPRESSION (((!ack_in)) && ack_out)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       112
 EXPRESSION (ack_in && ack_out)
             ---1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T11,T25

 LINE       115
 EXPRESSION (g_pos_dupcnt.cnt_incr_en ? (8'(inmask_ones)) : (8'(OutW)))
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       158
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       164
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable	T4,T11,T25
1	1	Covered	T4,T5,T6

 LINE       165
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T11,T28
1	1	Covered	T4,T5,T6

 LINE       169
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       170
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       257
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       282
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Unreachable	T4,T5,T6

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		26	24	92.31
TERNARY	169	2	2	100.00
TERNARY	170	2	2	100.00
TERNARY	282	1	1	100.00
TERNARY	115	2	2	100.00
IF	158	2	2	100.00
CASE	184	5	4	80.00
IF	213	3	3	100.00
IF	234	2	2	100.00
CASE	247	5	4	80.00
IF	122	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	169	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	282	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	(g_pos_dupcnt.cnt_incr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	158	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	184	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Covered	T4,T5,T6
2'b01	Covered	T4,T5,T6
2'b10	Covered	T4,T5,T6
2'b11	Covered	T4,T11,T25
default	Not Covered

	LineNo.	Expression
-1-:	213	if ((!rst_ni))
-2-:	216	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	234	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	247	case (flush_st)
-2-:	249	if (flush_i)
-3-:	257	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T4,T5,T6
FlushIdle	0	-	Covered	T4,T5,T6
FlushSend	-	1	Covered	T4,T5,T6
FlushSend	-	0	Covered	T4,T5,T6
default	-	-	Not Covered

	LineNo.	Expression
-1-:	122	if ((pos_with_input > 8'(OutW)))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	28	28	100.00	28	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	28	28	100.00	28	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	2147483647	648477	0	1041
DataOStableWhenPending_A	2147483647	910013	0	1041
ExFlushValid_M	2147483647	347261	0	0
ExcessiveDataStored_A	2147483647	64156	0	0
ExcessiveMaskStored_A	2147483647	64156	0	0
FlushFollowedByDone_A	2147483647	347261	0	1041
ValidIDeassertedOnFlush_M	2147483647	560992	0	0
ValidOAssertedForStoredDataGTEOutW_A	2147483647	48462856	0	0
ValidOPairedWidthReadyI_A	2147483647	910013	0	0
g_byte_assert.InputDividedBy8_A	1041	1041	0	0
g_byte_assert.OutputDividedBy8_A	1041	1041	0	0
g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A	2147483647	109647834	0	0
g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A	2147483647	109647834	0	0
g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A	2147483647	109647834	0	0
g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A	2147483647	109647834	0	0
g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A	2147483647	109647834	0	0
g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A	2147483647	109647834	0	0
g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A	2147483647	109647834	0	0
g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A	2147483647	109647834	0	0
g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A	2147483647	48667608	0	0
g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A	2147483647	48667608	0	0
g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A	2147483647	48667608	0	0
g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A	2147483647	48667608	0	0
g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A	2147483647	48667608	0	0
g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A	2147483647	48667608	0	0
g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A	2147483647	48667608	0	0
g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A	2147483647	48667608	0	0
gen_mask_assert.ContiguousOnesMask_M	2147483647	109647834	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	648477	0	1041
T4	705263	5412	0	1
T5	21269	0	0	1
T6	24271	0	0	1
T10	150036	0	0	1
T11	312238	1	0	1
T15	0	1	0	0
T23	981011	0	0	1
T24	1389	0	0	1
T25	658187	6	0	1
T26	11107	0	0	1
T27	1400	0	0	1
T28	0	4	0	0
T34	0	15813	0	0
T48	0	2394	0	0
T49	0	11378	0	0
T76	0	13662	0	0
T94	0	22	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	910013	0	1041
T4	705263	5197	0	1
T5	21269	0	0	1
T6	24271	0	0	1
T10	150036	0	0	1
T11	312238	1816	0	1
T23	981011	0	0	1
T24	1389	0	0	1
T25	658187	0	0	1
T26	11107	0	0	1
T27	1400	0	0	1
T28	0	913	0	0
T30	0	1220	0	0
T33	0	5522	0	0
T34	0	16027	0	0
T42	0	3834	0	0
T48	0	2377	0	0
T49	0	10491	0	0
T76	0	12328	0	0

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347261	0	0
T4	705263	497	0	0
T5	21269	9	0	0
T6	24271	9	0	0
T10	150036	2265	0	0
T11	312238	194	0	0
T23	981011	390	0	0
T24	1389	0	0	0
T25	658187	83	0	0
T26	11107	9	0	0
T27	1400	0	0	0
T28	0	332	0	0
T38	0	9	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	64156	0	0
T4	705263	639	0	0
T5	21269	0	0	0
T6	24271	0	0	0
T10	150036	0	0	0
T11	312238	0	0	0
T15	0	2	0	0
T23	981011	0	0	0
T24	1389	0	0	0
T25	658187	2	0	0
T26	11107	0	0	0
T27	1400	0	0	0
T34	0	3	0	0
T48	0	325	0	0
T49	0	540	0	0
T53	0	15	0	0
T76	0	590	0	0
T94	0	3	0	0
T95	0	12	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	64156	0	0
T4	705263	639	0	0
T5	21269	0	0	0
T6	24271	0	0	0
T10	150036	0	0	0
T11	312238	0	0	0
T15	0	2	0	0
T23	981011	0	0	0
T24	1389	0	0	0
T25	658187	2	0	0
T26	11107	0	0	0
T27	1400	0	0	0
T34	0	3	0	0
T48	0	325	0	0
T49	0	540	0	0
T53	0	15	0	0
T76	0	590	0	0
T94	0	3	0	0
T95	0	12	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347261	0	1041
T4	705263	497	0	1
T5	21269	9	0	1
T6	24271	9	0	1
T10	150036	2265	0	1
T11	312238	194	0	1
T23	981011	390	0	1
T24	1389	0	0	1
T25	658187	83	0	1
T26	11107	9	0	1
T27	1400	0	0	1
T28	0	332	0	0
T38	0	9	0	0

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	560992	0	0
T4	705263	1102	0	0
T5	21269	18	0	0
T6	24271	18	0	0
T10	150036	3155	0	0
T11	312238	358	0	0
T23	981011	730	0	0
T24	1389	0	0	0
T25	658187	154	0	0
T26	11107	18	0	0
T27	1400	0	0	0
T28	0	624	0	0
T38	0	18	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48462856	0	0
T4	705263	80287	0	0
T5	21269	100	0	0
T6	24271	100	0	0
T10	150036	194826	0	0
T11	312238	52040	0	0
T23	981011	95772	0	0
T24	1389	0	0	0
T25	658187	5308	0	0
T26	11107	100	0	0
T27	1400	0	0	0
T28	0	26144	0	0
T38	0	100	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	910013	0	0
T4	705263	5197	0	0
T5	21269	0	0	0
T6	24271	0	0	0
T10	150036	0	0	0
T11	312238	1816	0	0
T23	981011	0	0	0
T24	1389	0	0	0
T25	658187	0	0	0
T26	11107	0	0	0
T27	1400	0	0	0
T28	0	913	0	0
T30	0	1220	0	0
T33	0	5522	0	0
T34	0	16027	0	0
T42	0	3834	0	0
T48	0	2377	0	0
T49	0	10491	0	0
T76	0	12328	0	0

g_byte_assert.InputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

g_byte_assert.OutputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109647834	0	0
T4	705263	170817	0	0
T5	21269	258	0	0
T6	24271	234	0	0
T10	150036	452959	0	0
T11	312238	110433	0	0
T23	981011	225372	0	0
T24	1389	0	0	0
T25	658187	12620	0	0
T26	11107	249	0	0
T27	1400	0	0	0
T28	0	55688	0	0
T38	0	286	0	0

g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109647834	0	0
T4	705263	170817	0	0
T5	21269	258	0	0
T6	24271	234	0	0
T10	150036	452959	0	0
T11	312238	110433	0	0
T23	981011	225372	0	0
T24	1389	0	0	0
T25	658187	12620	0	0
T26	11107	249	0	0
T27	1400	0	0	0
T28	0	55688	0	0
T38	0	286	0	0

g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109647834	0	0
T4	705263	170817	0	0
T5	21269	258	0	0
T6	24271	234	0	0
T10	150036	452959	0	0
T11	312238	110433	0	0
T23	981011	225372	0	0
T24	1389	0	0	0
T25	658187	12620	0	0
T26	11107	249	0	0
T27	1400	0	0	0
T28	0	55688	0	0
T38	0	286	0	0

g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109647834	0	0
T4	705263	170817	0	0
T5	21269	258	0	0
T6	24271	234	0	0
T10	150036	452959	0	0
T11	312238	110433	0	0
T23	981011	225372	0	0
T24	1389	0	0	0
T25	658187	12620	0	0
T26	11107	249	0	0
T27	1400	0	0	0
T28	0	55688	0	0
T38	0	286	0	0

g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109647834	0	0
T4	705263	170817	0	0
T5	21269	258	0	0
T6	24271	234	0	0
T10	150036	452959	0	0
T11	312238	110433	0	0
T23	981011	225372	0	0
T24	1389	0	0	0
T25	658187	12620	0	0
T26	11107	249	0	0
T27	1400	0	0	0
T28	0	55688	0	0
T38	0	286	0	0

g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109647834	0	0
T4	705263	170817	0	0
T5	21269	258	0	0
T6	24271	234	0	0
T10	150036	452959	0	0
T11	312238	110433	0	0
T23	981011	225372	0	0
T24	1389	0	0	0
T25	658187	12620	0	0
T26	11107	249	0	0
T27	1400	0	0	0
T28	0	55688	0	0
T38	0	286	0	0

g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109647834	0	0
T4	705263	170817	0	0
T5	21269	258	0	0
T6	24271	234	0	0
T10	150036	452959	0	0
T11	312238	110433	0	0
T23	981011	225372	0	0
T24	1389	0	0	0
T25	658187	12620	0	0
T26	11107	249	0	0
T27	1400	0	0	0
T28	0	55688	0	0
T38	0	286	0	0

g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109647834	0	0
T4	705263	170817	0	0
T5	21269	258	0	0
T6	24271	234	0	0
T10	150036	452959	0	0
T11	312238	110433	0	0
T23	981011	225372	0	0
T24	1389	0	0	0
T25	658187	12620	0	0
T26	11107	249	0	0
T27	1400	0	0	0
T28	0	55688	0	0
T38	0	286	0	0

g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48667608	0	0
T4	705263	80713	0	0
T5	21269	109	0	0
T6	24271	109	0	0
T10	150036	195716	0	0
T11	312238	52204	0	0
T23	981011	96112	0	0
T24	1389	0	0	0
T25	658187	5379	0	0
T26	11107	109	0	0
T27	1400	0	0	0
T28	0	26436	0	0
T38	0	109	0	0

g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48667608	0	0
T4	705263	80713	0	0
T5	21269	109	0	0
T6	24271	109	0	0
T10	150036	195716	0	0
T11	312238	52204	0	0
T23	981011	96112	0	0
T24	1389	0	0	0
T25	658187	5379	0	0
T26	11107	109	0	0
T27	1400	0	0	0
T28	0	26436	0	0
T38	0	109	0	0

g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48667608	0	0
T4	705263	80713	0	0
T5	21269	109	0	0
T6	24271	109	0	0
T10	150036	195716	0	0
T11	312238	52204	0	0
T23	981011	96112	0	0
T24	1389	0	0	0
T25	658187	5379	0	0
T26	11107	109	0	0
T27	1400	0	0	0
T28	0	26436	0	0
T38	0	109	0	0

g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48667608	0	0
T4	705263	80713	0	0
T5	21269	109	0	0
T6	24271	109	0	0
T10	150036	195716	0	0
T11	312238	52204	0	0
T23	981011	96112	0	0
T24	1389	0	0	0
T25	658187	5379	0	0
T26	11107	109	0	0
T27	1400	0	0	0
T28	0	26436	0	0
T38	0	109	0	0

g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48667608	0	0
T4	705263	80713	0	0
T5	21269	109	0	0
T6	24271	109	0	0
T10	150036	195716	0	0
T11	312238	52204	0	0
T23	981011	96112	0	0
T24	1389	0	0	0
T25	658187	5379	0	0
T26	11107	109	0	0
T27	1400	0	0	0
T28	0	26436	0	0
T38	0	109	0	0

g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48667608	0	0
T4	705263	80713	0	0
T5	21269	109	0	0
T6	24271	109	0	0
T10	150036	195716	0	0
T11	312238	52204	0	0
T23	981011	96112	0	0
T24	1389	0	0	0
T25	658187	5379	0	0
T26	11107	109	0	0
T27	1400	0	0	0
T28	0	26436	0	0
T38	0	109	0	0

g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48667608	0	0
T4	705263	80713	0	0
T5	21269	109	0	0
T6	24271	109	0	0
T10	150036	195716	0	0
T11	312238	52204	0	0
T23	981011	96112	0	0
T24	1389	0	0	0
T25	658187	5379	0	0
T26	11107	109	0	0
T27	1400	0	0	0
T28	0	26436	0	0
T38	0	109	0	0

g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48667608	0	0
T4	705263	80713	0	0
T5	21269	109	0	0
T6	24271	109	0	0
T10	150036	195716	0	0
T11	312238	52204	0	0
T23	981011	96112	0	0
T24	1389	0	0	0
T25	658187	5379	0	0
T26	11107	109	0	0
T27	1400	0	0	0
T28	0	26436	0	0
T38	0	109	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109647834	0	0
T4	705263	170817	0	0
T5	21269	258	0	0
T6	24271	234	0	0
T10	150036	452959	0	0
T11	312238	110433	0	0
T23	981011	225372	0	0
T24	1389	0	0	0
T25	658187	12620	0	0
T26	11107	249	0	0
T27	1400	0	0	0
T28	0	55688	0	0
T38	0	286	0	0