Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	115115656	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1256	1256	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115115656	0	0
T3	2244	574	0	0
T56	641	0	0	0
T57	1416	0	0	0
T58	11996	0	0	0
T59	11555	0	0	0
T60	3565	479	0	0
T61	3721	411	0	0
T62	2260	0	0	0
T63	0	214	0	0
T64	1397	0	0	0
T65	0	305	0	0
T66	0	4	0	0
T67	0	158	0	0
T68	0	590	0	0
T69	1212	0	0	0
T70	0	210	0	0
T74	0	726	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256	1256	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	204869158	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1256	1256	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	204869158	0	0
T3	2244	297	0	0
T56	641	0	0	0
T57	1416	0	0	0
T58	11996	0	0	0
T59	11555	0	0	0
T60	3565	371	0	0
T61	3721	327	0	0
T62	2260	0	0	0
T63	0	682	0	0
T64	1397	0	0	0
T65	0	267	0	0
T66	0	4	0	0
T67	0	612	0	0
T68	0	340	0	0
T69	1212	0	0	0
T70	0	511	0	0
T74	0	363	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256	1256	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	327511772	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1256	1256	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	327511772	0	0
T1	1147	22	0	0
T2	1496	473	0	0
T3	2244	276	0	0
T56	641	22	0	0
T57	1416	40	0	0
T58	11996	1598	0	0
T59	11555	1492	0	0
T60	3565	978	0	0
T61	3721	1083	0	0
T62	2260	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256	1256	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	595787485	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1256	1256	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	595787485	0	0
T1	1147	117	0	0
T2	1496	240	0	0
T3	2244	151	0	0
T56	641	22	0	0
T57	1416	40	0	0
T58	11996	1378	0	0
T59	11555	1367	0	0
T60	3565	670	0	0
T61	3721	676	0	0
T62	2260	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1147	1093	0	0
T2	1496	1420	0	0
T3	2244	2171	0	0
T56	641	561	0	0
T57	1416	1332	0	0
T58	11996	11558	0	0
T59	11555	10718	0	0
T60	3565	3501	0	0
T61	3721	3669	0	0
T62	2260	2162	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256	1256	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0