Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1594212	0	0
entropy_period_rd_A	2147483647	3347	0	0
intr_enable_rd_A	2147483647	4430	0	0
prefix_0_rd_A	2147483647	3774	0	0
prefix_10_rd_A	2147483647	3678	0	0
prefix_1_rd_A	2147483647	3648	0	0
prefix_2_rd_A	2147483647	3610	0	0
prefix_3_rd_A	2147483647	3793	0	0
prefix_4_rd_A	2147483647	3676	0	0
prefix_5_rd_A	2147483647	3749	0	0
prefix_6_rd_A	2147483647	3718	0	0
prefix_7_rd_A	2147483647	3873	0	0
prefix_8_rd_A	2147483647	3786	0	0
prefix_9_rd_A	2147483647	3840	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1594212	0	0
T3	2244	1	0	0
T56	641	0	0	0
T57	1416	0	0	0
T58	11996	0	0	0
T59	11555	1	0	0
T60	3565	187	0	0
T61	3721	297	0	0
T62	2260	0	0	0
T63	0	77	0	0
T64	1397	0	0	0
T65	0	236	0	0
T67	0	18	0	0
T68	0	19	0	0
T69	1212	0	0	0
T116	0	2	0	0
T117	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3347	0	0
T20	0	242	0	0
T63	4520	0	0	0
T70	3488	5	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	482	0	0
T74	1583	0	0	0
T83	16434	64	0	0
T84	0	25	0	0
T90	2752	0	0	0
T116	5727	0	0	0
T131	0	211	0	0
T135	1400	0	0	0
T138	0	58	0	0
T139	0	249	0	0
T140	0	74	0	0
T141	0	38	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4430	0	0
T1	1147	8	0	0
T2	1496	0	0	0
T3	2244	0	0	0
T56	641	0	0	0
T57	1416	0	0	0
T58	11996	0	0	0
T59	11555	0	0	0
T60	3565	0	0	0
T61	3721	0	0	0
T62	2260	16	0	0
T70	0	4	0	0
T73	0	492	0	0
T83	0	107	0	0
T84	0	58	0	0
T93	0	2	0	0
T131	0	490	0	0
T134	0	22	0	0
T138	0	108	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3774	0	0
T20	0	179	0	0
T63	4520	0	0	0
T70	3488	14	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	495	0	0
T74	1583	0	0	0
T83	16434	60	0	0
T84	0	23	0	0
T90	2752	0	0	0
T93	0	4	0	0
T116	5727	0	0	0
T131	0	443	0	0
T135	1400	0	0	0
T138	0	62	0	0
T139	0	159	0	0
T140	0	60	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3678	0	0
T20	0	188	0	0
T63	4520	0	0	0
T70	3488	7	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	496	0	0
T74	1583	0	0	0
T83	16434	70	0	0
T84	0	44	0	0
T90	2752	0	0	0
T93	0	17	0	0
T116	5727	0	0	0
T131	0	390	0	0
T135	1400	0	0	0
T138	0	47	0	0
T139	0	139	0	0
T140	0	79	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3648	0	0
T20	0	268	0	0
T63	4520	0	0	0
T70	3488	9	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	468	0	0
T74	1583	0	0	0
T83	16434	55	0	0
T84	0	17	0	0
T90	2752	0	0	0
T93	0	9	0	0
T116	5727	0	0	0
T131	0	444	0	0
T135	1400	0	0	0
T138	0	52	0	0
T139	0	85	0	0
T140	0	82	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3610	0	0
T20	0	170	0	0
T63	4520	0	0	0
T70	3488	11	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	506	0	0
T74	1583	0	0	0
T83	16434	56	0	0
T84	0	31	0	0
T90	2752	0	0	0
T93	0	16	0	0
T116	5727	0	0	0
T131	0	370	0	0
T135	1400	0	0	0
T138	0	52	0	0
T139	0	141	0	0
T140	0	52	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3793	0	0
T20	0	187	0	0
T63	4520	0	0	0
T70	3488	9	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	502	0	0
T74	1583	0	0	0
T83	16434	57	0	0
T84	0	21	0	0
T90	2752	0	0	0
T93	0	6	0	0
T116	5727	0	0	0
T131	0	474	0	0
T135	1400	0	0	0
T138	0	75	0	0
T139	0	181	0	0
T140	0	47	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3676	0	0
T20	0	169	0	0
T63	4520	0	0	0
T70	3488	4	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	450	0	0
T74	1583	0	0	0
T83	16434	45	0	0
T84	0	17	0	0
T90	2752	0	0	0
T93	0	5	0	0
T116	5727	0	0	0
T131	0	430	0	0
T135	1400	0	0	0
T138	0	42	0	0
T139	0	144	0	0
T140	0	65	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3749	0	0
T20	0	231	0	0
T63	4520	0	0	0
T70	3488	5	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	435	0	0
T74	1583	0	0	0
T83	16434	58	0	0
T84	0	25	0	0
T90	2752	0	0	0
T93	0	8	0	0
T116	5727	0	0	0
T131	0	434	0	0
T135	1400	0	0	0
T138	0	46	0	0
T139	0	139	0	0
T140	0	65	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3718	0	0
T20	0	216	0	0
T63	4520	0	0	0
T70	3488	7	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	433	0	0
T74	1583	0	0	0
T83	16434	64	0	0
T84	0	33	0	0
T90	2752	0	0	0
T93	0	11	0	0
T116	5727	0	0	0
T131	0	474	0	0
T135	1400	0	0	0
T138	0	67	0	0
T139	0	102	0	0
T140	0	65	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3873	0	0
T20	0	216	0	0
T63	4520	0	0	0
T70	3488	7	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	507	0	0
T74	1583	0	0	0
T83	16434	70	0	0
T84	0	16	0	0
T90	2752	0	0	0
T93	0	5	0	0
T116	5727	0	0	0
T131	0	503	0	0
T135	1400	0	0	0
T138	0	43	0	0
T139	0	137	0	0
T140	0	74	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3786	0	0
T20	0	215	0	0
T63	4520	0	0	0
T70	3488	16	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	496	0	0
T74	1583	0	0	0
T83	16434	38	0	0
T84	0	23	0	0
T90	2752	0	0	0
T93	0	12	0	0
T116	5727	0	0	0
T131	0	479	0	0
T135	1400	0	0	0
T138	0	66	0	0
T139	0	159	0	0
T140	0	61	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3840	0	0
T20	0	231	0	0
T63	4520	0	0	0
T70	3488	7	0	0
T71	2295	0	0	0
T72	5532	0	0	0
T73	55567	492	0	0
T74	1583	0	0	0
T83	16434	58	0	0
T84	0	27	0	0
T90	2752	0	0	0
T93	0	8	0	0
T116	5727	0	0	0
T131	0	421	0	0
T135	1400	0	0	0
T138	0	37	0	0
T139	0	189	0	0
T140	0	67	0	0