Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99389957	1			T1	5		T54	8		T55	8
all_values[1]	99389957	1			T1	5		T54	8		T55	8
all_values[2]	99389957	1			T1	5		T54	8		T55	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

601672

1

T1

7

T54

9

T55

12

auto[1]

297568199

1

T1

8

T54

15

T55

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296638986

1

T1

9

T54

9

T55

9

auto[1]

1530885

1

T1

6

T54

15

T55

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	166010	1			T1	2		T57	3		T58	1
all_values[0]	auto[0]	auto[1]	2207	1			T1	2		T54	2		T55	1
all_values[0]	auto[1]	auto[0]	98713652	1			T1	1		T54	3		T55	3
all_values[0]	auto[1]	auto[1]	508088	1			T54	3		T55	4		T57	2
all_values[1]	auto[0]	auto[0]	195837	1			T54	2		T55	2		T57	4
all_values[1]	auto[0]	auto[1]	1700	1			T54	3		T55	3		T57	2
all_values[1]	auto[1]	auto[0]	98683825	1			T1	3		T54	1		T55	1
all_values[1]	auto[1]	auto[1]	508595	1			T1	2		T54	2		T55	2
all_values[2]	auto[0]	auto[0]	234209	1			T1	1		T55	2		T57	3
all_values[2]	auto[0]	auto[1]	1709	1			T1	2		T54	2		T55	4
all_values[2]	auto[1]	auto[0]	98645453	1			T1	2		T54	3		T55	1
all_values[2]	auto[1]	auto[1]	508586	1			T54	3		T55	1		T57	2