Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total618510
Category 0618510

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total618510
Severity 0618510

Summary for Assertions
NUMBERPERCENT
Total Number618100.00
Uncovered71.13
Success61198.87
Failure00.00
Incomplete40.65
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00

Summary for Cover Properties
NUMBERPERCENT
Total Number5100.00
Uncovered00.00
Matches5100.00

Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_kmac_core.ProcessLatchedCleared_A 002147483647000
tb.dut.u_tlul_adapter_msgfifo.rvalidHighReqFifoEmpty 002147483647000
tb.dut.u_tlul_adapter_msgfifo.rvalidHighWhenRspFifoFull 002147483647000
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.DataKnown_A 002147483647000
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 002147483647000
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.DataKnown_A 002147483647000
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 002147483647000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertKnownO_A 002147483647214748364700
tb.dut.CmdSparse_M 002147483647128059200
tb.dut.EnMaskingKnown_A 002147483647214748364700
tb.dut.EntropyReadyLatched_A 00214748364733708200
tb.dut.EntrySizeRegSameToEntrySizePkg_A 001048104800
tb.dut.ErrProcessedLatched_A 00214748364789200
tb.dut.FifoEmpty_A 002147483647214748364700
tb.dut.FpvSecCmErrorCheckFsmCheck_A 0021474836477000
tb.dut.FpvSecCmKeccackFsmCheck_A 0021474836477000
tb.dut.FpvSecCmKeyIndexCountCheck_A 0021474836477000
tb.dut.FpvSecCmKmacAppFsmCheck_A 0021474836477000
tb.dut.FpvSecCmKmacCoreFsmCheck_A 0021474836477000
tb.dut.FpvSecCmKmacFsmCheck_A 0021474836477000
tb.dut.FpvSecCmRegWeOnehotCheck_A 0021474836477000
tb.dut.FpvSecCmRoundCountCheck_A 0021474836477000
tb.dut.FpvSecCmSHA3FsmCheck_A 0021474836477000
tb.dut.FpvSecCmSHA3padFsmCheck_A 0021474836477000
tb.dut.FpvSecCmSentMsgCountCheck_A 0021474836477000
tb.dut.KmacCmd_A 002147483647214748364700
tb.dut.KmacDone_A 002147483647214748364700
tb.dut.KmacErr_A 002147483647214748364700
tb.dut.KmacStKnown_A 002147483647214748364700
tb.dut.NumAlerts2_A 001048104800
tb.dut.NumEntriesRegSameToNumEntriesPkg_A 001048104800
tb.dut.PrefixRegSameToPrefixPkg_A 001048104800
tb.dut.SecretKeyDivideBy32_A 001048104800
tb.dut.Sha3AbsorbedPulse_A 00214748364734569600
tb.dut.TlOAReadyKnown_A 002147483647214748364700
tb.dut.TlODValidKnown_A 002147483647214748364700
tb.dut.g_testassertion.FpvSecCmEntropyFsmCheck_A 0021474836477000
tb.dut.g_testassertion.FpvSecCmHashCountCheck_A 0021474836477000
tb.dut.g_testassertion.FpvSecCmMsgFifoRptrCheck_A 0021474836477000
tb.dut.g_testassertion.FpvSecCmMsgFifoWptrCheck_A 0021474836477000
tb.dut.g_testassertion.FpvSecCmPackerCountCheck_A 0021474836477000
tb.dut.g_testassertion.FpvSecCmSeedIdxCountCheck_A 0021474836477000
tb.dut.gen_entropy.u_entropy.ChunkSizeEntropyLfsrMatchesEdn 001048104800
tb.dut.gen_entropy.u_entropy.ChunkSizeEntropyLfsrMatchesSw 001048104800
tb.dut.gen_entropy.u_entropy.ConsumeNotAssertWhenNotValid_M 00214748364715495430000
tb.dut.gen_entropy.u_entropy.EntropyLfsrWDivisble 001048104800
tb.dut.gen_entropy.u_entropy.ModeKnown_A 002147483647214748364700
tb.dut.gen_entropy.u_entropy.RandStKnown_A 002147483647214748364700
tb.dut.gen_entropy.u_entropy.p_perm_check.PermutationCheck_A 001048104800
tb.dut.gen_entropy.u_entropy.p_perm_fwd_check.PermutationCheck_A 001048104800
tb.dut.gen_entropy.u_entropy.u_entropy_configured.OutputsKnown_A 002147483647214748364700
tb.dut.gen_entropy.u_entropy.u_state_regs.AssertConnected_A 001048104800
tb.dut.gen_entropy.u_entropy.u_state_regs_A 002147483647214748364700
tb.dut.gen_entropy.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 002147483647560300
tb.dut.gen_entropy.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 002147483647560300
tb.dut.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq 002147483647547500
tb.dut.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq 002147483647121800
tb.dut.intr_fifo_empty.IntrTKind_A 001048104800
tb.dut.intr_kmac_done.IntrTKind_A 001048104800
tb.dut.intr_kmac_err.IntrTKind_A 001048104800
tb.dut.kmac_csr_assert.TlulOOBAddrErr_A 002147483647152956600
tb.dut.kmac_csr_assert.entropy_period_rd_A 002147483647236100
tb.dut.kmac_csr_assert.intr_enable_rd_A 002147483647287700
tb.dut.kmac_csr_assert.prefix_0_rd_A 002147483647214600
tb.dut.kmac_csr_assert.prefix_10_rd_A 002147483647219200
tb.dut.kmac_csr_assert.prefix_1_rd_A 002147483647220600
tb.dut.kmac_csr_assert.prefix_2_rd_A 002147483647248200
tb.dut.kmac_csr_assert.prefix_3_rd_A 002147483647239600
tb.dut.kmac_csr_assert.prefix_4_rd_A 002147483647220000
tb.dut.kmac_csr_assert.prefix_5_rd_A 002147483647227100
tb.dut.kmac_csr_assert.prefix_6_rd_A 002147483647213800
tb.dut.kmac_csr_assert.prefix_7_rd_A 002147483647228700
tb.dut.kmac_csr_assert.prefix_8_rd_A 002147483647230400
tb.dut.kmac_csr_assert.prefix_9_rd_A 002147483647227800
tb.dut.sha3pad_assert_cov_if.ProcessToRun_A 00214748364734569700
tb.dut.sha3pad_assert_cov_if.RunThenComplete_M 002147483647307308000
tb.dut.tlul_assert_device.aKnown_A 00214748364747773579900
tb.dut.tlul_assert_device.aKnown_AKnownEnable 002147483647214748364700
tb.dut.tlul_assert_device.aReadyKnown_A 002147483647214748364700
tb.dut.tlul_assert_device.dKnown_A 00214748364782025550900
tb.dut.tlul_assert_device.dKnown_AKnownEnable 002147483647214748364700
tb.dut.tlul_assert_device.dReadyKnown_A 002147483647214748364700
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A 001263126300
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tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 001263126300
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tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 001263126300
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 00214748364724329529000
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 002147483647268352200
tb.dut.tlul_assert_device.gen_device.contigMask_M 00214748364733266698900
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00214748364740614700600
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 002147483647228819700
tb.dut.tlul_assert_device.gen_device.legalAParam_M 00214748364747773584000
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00214748364782025554300
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 00214748364747773584000
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00214748364782025554300
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00214748364782025554300
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00214748364782025554300
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 002147483647186923000
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 002147483647166619500
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 001263126300
tb.dut.u_app_intf.AppIntfInRange_A 001048104800
tb.dut.u_app_intf.SideloadKeySameToDigest_A 001048104800
tb.dut.u_app_intf.u_appid_arb.CheckHotOne_A 002147483647214748364700
tb.dut.u_app_intf.u_appid_arb.CheckNGreaterZero_A 001048104800
tb.dut.u_app_intf.u_appid_arb.GntImpliesReady_A 002147483647723800
tb.dut.u_app_intf.u_appid_arb.GntImpliesValid_A 002147483647723800
tb.dut.u_app_intf.u_appid_arb.GrantKnown_A 002147483647214748364700
tb.dut.u_app_intf.u_appid_arb.IdxKnown_A 002147483647214748364700
tb.dut.u_app_intf.u_appid_arb.IndexIsCorrect_A 002147483647723800
tb.dut.u_app_intf.u_appid_arb.NoReadyValidNoGrant_A 002147483647214748364700
tb.dut.u_app_intf.u_appid_arb.Priority_A 002147483647395946600
tb.dut.u_app_intf.u_appid_arb.ReadyAndValidImplyGrant_A 002147483647723800
tb.dut.u_app_intf.u_appid_arb.ReqAndReadyImplyGrant_A 002147483647723800
tb.dut.u_app_intf.u_appid_arb.ReqImpliesValid_A 002147483647395946600
tb.dut.u_app_intf.u_appid_arb.ValidKnown_A 002147483647214748364700
tb.dut.u_app_intf.u_state_regs.AssertConnected_A 001048104800
tb.dut.u_app_intf.u_state_regs_A 002147483647214748364700
tb.dut.u_errchk.ExpectedModeStrengthBits_A 001048104800
tb.dut.u_errchk.ExpectedStSwCmdBits_A 001048104800
tb.dut.u_errchk.StKnown_A 002147483647214748364700
tb.dut.u_errchk.u_state_regs.AssertConnected_A 001048104800
tb.dut.u_errchk.u_state_regs_A 002147483647214748364700
tb.dut.u_kmac_core.AckOnlyInMessageState_A 002147483647803676000
tb.dut.u_kmac_core.KeyDataStable_M 002147483647103575100
tb.dut.u_kmac_core.KeyLengthStable_M 00214748364728125000
tb.dut.u_kmac_core.KmacEnStable_M 0021474836472358300
tb.dut.u_kmac_core.MaxKeyLenMatchToKey512_A 001048104800
tb.dut.u_kmac_core.ModeStable_M 0021474836473540100
tb.dut.u_kmac_core.StrengthStable_M 0021474836474234500
tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer.ValidWidth_A 001048104800
tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer.ValidWidth_A 001048104800
tb.dut.u_kmac_core.u_state_regs.AssertConnected_A 001048104800
tb.dut.u_kmac_core.u_state_regs_A 002147483647214748364700
tb.dut.u_msgfifo.FlushStInValid_A 002147483647214748364700
tb.dut.u_msgfifo.MessageValid_a 00214748364710884283000
tb.dut.u_msgfifo.PackerDoneDelay_A 002147483647214748364700
tb.dut.u_msgfifo.PackerDoneValid_a 00214748364734569800
tb.dut.u_msgfifo.u_msgfifo.DataKnown_A 00214748364719084942300
tb.dut.u_msgfifo.u_msgfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_msgfifo.u_msgfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_msgfifo.u_msgfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00214748364719084942300
tb.dut.u_msgfifo.u_packer.DataIStable_M 00214748364745517101048
tb.dut.u_msgfifo.u_packer.DataOStableWhenPending_A 00214748364767154801048
tb.dut.u_msgfifo.u_packer.ExFlushValid_M 00214748364734569800
tb.dut.u_msgfifo.u_packer.ExcessiveDataStored_A 0021474836474972500
tb.dut.u_msgfifo.u_packer.ExcessiveMaskStored_A 0021474836474972500
tb.dut.u_msgfifo.u_packer.FlushFollowedByDone_A 00214748364734569801048
tb.dut.u_msgfifo.u_packer.ValidIDeassertedOnFlush_M 00214748364755471600
tb.dut.u_msgfifo.u_packer.ValidOAssertedForStoredDataGTEOutW_A 0021474836474806921800
tb.dut.u_msgfifo.u_packer.ValidOPairedWidthReadyI_A 00214748364767154800
tb.dut.u_msgfifo.u_packer.g_byte_assert.InputDividedBy8_A 001048104800
tb.dut.u_msgfifo.u_packer.g_byte_assert.OutputDividedBy8_A 001048104800
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A 00214748364710884283000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A 00214748364710884283000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A 00214748364710884283000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A 00214748364710884283000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A 00214748364710884283000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A 00214748364710884283000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A 00214748364710884283000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A 00214748364710884283000
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A 0021474836474827131500
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A 0021474836474827131500
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A 0021474836474827131500
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A 0021474836474827131500
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A 0021474836474827131500
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A 0021474836474827131500
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A 0021474836474827131500
tb.dut.u_msgfifo.u_packer.g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A 0021474836474827131500
tb.dut.u_msgfifo.u_packer.gen_mask_assert.ContiguousOnesMask_M 00214748364710884283000
tb.dut.u_prim_lc_sync.NumCopiesMustBeGreaterZero_A 001048104800
tb.dut.u_prim_lc_sync.OutputsKnown_A 002147483647214748364700
tb.dut.u_prim_lc_sync.gen_flops.OutputDelay_A 002147483647214748364703144
tb.dut.u_reg.en2addrHit 00214748364731381416000
tb.dut.u_reg.reAfterRv 00214748364731381414100
tb.dut.u_reg.rePulse 00214748364720776188800
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_err_processed.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_err_processed.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_kmac_en.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_kmac_en.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_kstrength.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_kstrength.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_mode.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_mode.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_msg_mask.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_msg_mask.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_sideload.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_sideload.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_cfg_shadowed_state_endianness.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_cfg_shadowed_state_endianness.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_chk.PayLoadWidthCheck 001263126300
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.MubiIsNotYetSupported_A 002147483647214748364700
tb.dut.u_reg.u_reg_if.AllowedLatency_A 001263126300
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 001263126300
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 001263126300
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001263126300
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001263126300
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 001263126300
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 001263126300
tb.dut.u_reg.u_socket.NotOverflowed_A 0045297560045297560000
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A 00214748364747773579900
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A 00214748364782025550900
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 0021474836472465648800
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 0021474836474493833200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 00214748364711510658600
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 00214748364720345866500
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A 00214748364732120320100
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A 00214748364757185851200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A 001263126300
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck 001263126300
tb.dut.u_reg.u_socket.maxN 001263126300
tb.dut.u_reg.wePulse 00214748364710605225300
tb.dut.u_sha3.ErrDetection_A 002147483647741707100
tb.dut.u_sha3.FsmKnown_A 002147483647214748364700
tb.dut.u_sha3.MuxSelKnown_A 002147483647214748364700
tb.dut.u_sha3.SwRunInSqueezing_a 00214748364715511400
tb.dut.u_sha3.gen_chk_digest_masked.StateZeroInvalid_A 002147483647214748364700
tb.dut.u_sha3.u_keccak.ClearAssertStIdle_A 00214748364734567900
tb.dut.u_sha3.u_keccak.OneHot0ValidAndRun_A 002147483647214748364700
tb.dut.u_sha3.u_keccak.ValidRunAssertStIdle_A 0021474836475623886400
tb.dut.u_sha3.u_keccak.WidthDivisableByDInWidth_A 001048104800
tb.dut.u_sha3.u_keccak.gen_mask_st_chk.EnMaskingValidStates_A 002147483647214748364700
tb.dut.u_sha3.u_keccak.u_keccak_p.ValidL_A 001048104800
tb.dut.u_sha3.u_keccak.u_keccak_p.ValidRound_A 001048104800
tb.dut.u_sha3.u_keccak.u_keccak_p.ValidW_A 001048104800
tb.dut.u_sha3.u_keccak.u_keccak_p.ValidWidth_A 001048104800
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom.UnmaskedAndMatched_A 00214748364715496515900
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom.UnmaskedAndMatched_A 00214748364715496515900
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom.UnmaskedAndMatched_A 00214748364715496515900
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom.UnmaskedAndMatched_A 00214748364715496515900
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom.UnmaskedAndMatched_A 00214748364715496515900
tb.dut.u_sha3.u_keccak.u_keccak_p.gen_selperiod_chk.SelStayTwoCycleIfTrue_A 0021474836477747713200
tb.dut.u_sha3.u_keccak.u_state_regs.AssertConnected_A 001048104800
tb.dut.u_sha3.u_keccak.u_state_regs_A 002147483647214748364700
tb.dut.u_sha3.u_pad.AbsorbedPulse_A 00214748364734569600
tb.dut.u_sha3.u_pad.AlwaysPartialMsgBuf_M 00214748364719776400
tb.dut.u_sha3.u_pad.CompleteBlockWhenProcess_A 00214748364733357100
tb.dut.u_sha3.u_pad.DoneCondition_M 00214748364734567900
tb.dut.u_sha3.u_pad.DonePulse_A 00214748364734567900
tb.dut.u_sha3.u_pad.KeccakAddrInRange_A 0021474836475301062400
tb.dut.u_sha3.u_pad.KeccakRunPulse_A 002147483647307312600
tb.dut.u_sha3.u_pad.MessageCondition_M 0021474836474827782200
tb.dut.u_sha3.u_pad.ModeStableDuringOp_M 0021474836473540100
tb.dut.u_sha3.u_pad.MsgReadyCondition_A 002147483647213238804300
tb.dut.u_sha3.u_pad.MsgWidthidth_A 001048104800
tb.dut.u_sha3.u_pad.NoPartialMsgFifo_M 0021474836474808005800
tb.dut.u_sha3.u_pad.Pad01NotAttheEndOfBlock_A 00214748364733502200
tb.dut.u_sha3.u_pad.PartialEndOfMsg_M 00214748364719776400
tb.dut.u_sha3.u_pad.PrefixLessThanBlock_A 001048104800
tb.dut.u_sha3.u_pad.ProcessCondition_M 00214748364734569800
tb.dut.u_sha3.u_pad.ProcessPulse_A 00214748364734569800
tb.dut.u_sha3.u_pad.StartCondition_M 00214748364734581600
tb.dut.u_sha3.u_pad.StartProcessDoneMutex_a 002147483647214748364700
tb.dut.u_sha3.u_pad.StartPulse_A 00214748364734581600
tb.dut.u_sha3.u_pad.StrengthStableDuringOp_M 0021474836474234500
tb.dut.u_sha3.u_pad.u_prefix_slicer.ValidWidth_A 001048104800
tb.dut.u_sha3.u_pad.u_state_regs.AssertConnected_A 001048104800
tb.dut.u_sha3.u_pad.u_state_regs_A 002147483647214748364700
tb.dut.u_sha3.u_state_regs.AssertConnected_A 001048104800
tb.dut.u_sha3.u_state_regs_A 002147483647214748364700
tb.dut.u_sha3_done_sender.OutputsKnown_A 002147483647214748364700
tb.dut.u_state_regs.AssertConnected_A 001048104800
tb.dut.u_state_regs_A 002147483647214748364700
tb.dut.u_staterd.gen_slicer[0].u_state_slice.ValidWidth_A 001048104800
tb.dut.u_staterd.gen_slicer[1].u_state_slice.ValidWidth_A 001048104800
tb.dut.u_staterd.u_tlul_adapter.AddrOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.DataIntgOptions_A 001048104800
tb.dut.u_staterd.u_tlul_adapter.ReqOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.SramDwHasByteGranularity_A 001048104800
tb.dut.u_staterd.u_tlul_adapter.SramDwIsMultipleOfTlulWidth_A 001048104800
tb.dut.u_staterd.u_tlul_adapter.TlOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.TlOutPayloadKnown_A 0021474836474493096200
tb.dut.u_staterd.u_tlul_adapter.TlOutPayloadKnown_AKnownEnable 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.WdataOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.WeOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.WmaskOutKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.adapterNoReadOrWrite 001048104800
tb.dut.u_staterd.u_tlul_adapter.rvalidHighReqFifoEmpty 0021474836472202271900
tb.dut.u_staterd.u_tlul_adapter.rvalidHighWhenRspFifoFull 0021474836472202271900
tb.dut.u_staterd.u_tlul_adapter.u_err.dataWidthOnly32_A 001048104800
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.DataKnown_A 0021474836474493096200
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0021474836474493096200
tb.dut.u_staterd.u_tlul_adapter.u_rsp_gen.DataWidthCheck_A 001048104800
tb.dut.u_staterd.u_tlul_adapter.u_rsp_gen.PayLoadWidthCheck 001048104800
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.DataKnown_A 0021474836474137405400
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0021474836474137405400
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.DataKnown_A 0021474836472202271900
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0021474836472202271900
tb.dut.u_tlul_adapter_msgfifo.AddrOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.DataIntgOptions_A 001048104800
tb.dut.u_tlul_adapter_msgfifo.ReqOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.SramDwHasByteGranularity_A 001048104800
tb.dut.u_tlul_adapter_msgfifo.SramDwIsMultipleOfTlulWidth_A 001048104800
tb.dut.u_tlul_adapter_msgfifo.TlOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.TlOutPayloadKnown_A 00214748364720344314700
tb.dut.u_tlul_adapter_msgfifo.TlOutPayloadKnown_AKnownEnable 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.WdataOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.WeOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.WmaskOutKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.adapterNoReadOrWrite 001048104800
tb.dut.u_tlul_adapter_msgfifo.u_err.dataWidthOnly32_A 001048104800
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.DataKnown_A 00214748364720344314700
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00214748364720344314700
tb.dut.u_tlul_adapter_msgfifo.u_rsp_gen.DataWidthCheck_A 001048104800
tb.dut.u_tlul_adapter_msgfifo.u_rsp_gen.PayLoadWidthCheck 001048104800
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.WreadyKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.DepthKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.RvalidKnown_A 002147483647214748364700
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.WreadyKnown_A 002147483647214748364700

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_msgfifo.u_packer.DataIStable_M 00214748364745517101048
tb.dut.u_msgfifo.u_packer.DataOStableWhenPending_A 00214748364767154801048
tb.dut.u_msgfifo.u_packer.FlushFollowedByDone_A 00214748364734569801048
tb.dut.u_prim_lc_sync.gen_flops.OutputDelay_A 002147483647214748364703144

Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021474836476960206960200
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00214748364750500
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00214748364750500
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00214748364743430
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00214748364723230
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00214748364730300
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 002147483647440
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002147483647922092200
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 002147483647719670771967070
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0021474836472312721272312721271211

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021474836476960206960200
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00214748364750500
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00214748364750500
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00214748364743430
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00214748364723230
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00214748364730300
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 002147483647440
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002147483647922092200
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 002147483647719670771967070
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0021474836472312721272312721271211

Detail Report for Cover Properties

Cover Properties Matches:
COVER PROPERTIESCATEGORYSEVERITYATTEMPTSMATCHESINCOMPLETESRC
tb.dut.u_app_intf.AppIntfUseDifferentSizeKey_C 00214748364728590
tb.dut.u_sha3.u_pad.StComplete_C 002147483647335669000
tb.dut.u_sha3.u_pad.StMessageFeed_C 00214748364721354218300
tb.dut.u_sha3.u_pad.StPadSendMsg_C 00214748364738434170
tb.dut.u_sha3.u_pad.StPad_C 0021474836473350210

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