Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329858 |
1 |
|
|
T4 |
2 |
|
T5 |
620 |
|
T11 |
2 |
auto[1] |
363218 |
1 |
|
|
T4 |
192 |
|
T9 |
92 |
|
T10 |
352 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173871 |
1 |
|
|
T4 |
60 |
|
T5 |
146 |
|
T11 |
1 |
lower_val |
171479 |
1 |
|
|
T4 |
41 |
|
T5 |
163 |
|
T9 |
27 |
zero_val |
2023 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
255636 |
1 |
|
|
T4 |
48 |
|
T5 |
294 |
|
T11 |
2 |
lower_val |
255480 |
1 |
|
|
T4 |
40 |
|
T5 |
326 |
|
T9 |
36 |
zero_val |
181960 |
1 |
|
|
T4 |
106 |
|
T9 |
32 |
|
T10 |
174 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41249 |
1 |
|
|
T5 |
73 |
|
T11 |
1 |
|
T31 |
78 |
higher_val |
higher_val |
auto[1] |
22757 |
1 |
|
|
T4 |
16 |
|
T9 |
8 |
|
T10 |
28 |
higher_val |
lower_val |
auto[0] |
41275 |
1 |
|
|
T5 |
73 |
|
T29 |
1 |
|
T31 |
80 |
higher_val |
lower_val |
auto[1] |
22842 |
1 |
|
|
T4 |
12 |
|
T9 |
10 |
|
T10 |
19 |
higher_val |
zero_val |
auto[0] |
102 |
1 |
|
|
T9 |
1 |
|
T10 |
1 |
|
T13 |
2 |
higher_val |
zero_val |
auto[1] |
45646 |
1 |
|
|
T4 |
32 |
|
T9 |
9 |
|
T10 |
34 |
lower_val |
higher_val |
auto[0] |
40545 |
1 |
|
|
T5 |
72 |
|
T31 |
80 |
|
T38 |
560 |
lower_val |
higher_val |
auto[1] |
22666 |
1 |
|
|
T4 |
8 |
|
T9 |
7 |
|
T10 |
13 |
lower_val |
lower_val |
auto[0] |
40723 |
1 |
|
|
T5 |
91 |
|
T30 |
1 |
|
T31 |
64 |
lower_val |
lower_val |
auto[1] |
22636 |
1 |
|
|
T4 |
8 |
|
T9 |
13 |
|
T10 |
18 |
lower_val |
zero_val |
auto[0] |
102 |
1 |
|
|
T13 |
4 |
|
T15 |
1 |
|
T26 |
1 |
lower_val |
zero_val |
auto[1] |
44807 |
1 |
|
|
T4 |
25 |
|
T9 |
7 |
|
T10 |
43 |
zero_val |
higher_val |
auto[0] |
583 |
1 |
|
|
T11 |
1 |
|
T31 |
1 |
|
T38 |
3 |
zero_val |
higher_val |
auto[1] |
163 |
1 |
|
|
T9 |
2 |
|
T13 |
4 |
|
T15 |
1 |
zero_val |
lower_val |
auto[0] |
592 |
1 |
|
|
T5 |
1 |
|
T9 |
1 |
|
T29 |
1 |
zero_val |
lower_val |
auto[1] |
174 |
1 |
|
|
T9 |
1 |
|
T14 |
3 |
|
T15 |
1 |
zero_val |
zero_val |
auto[0] |
278 |
1 |
|
|
T4 |
1 |
|
T9 |
1 |
|
T10 |
1 |
zero_val |
zero_val |
auto[1] |
233 |
1 |
|
|
T10 |
2 |
|
T13 |
1 |
|
T14 |
1 |