Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10208	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8999	1			T4	16		T5	24		T9	1
len_5001_7500	14606	1			T4	48		T5	24		T9	3
len_2501_5000	9229	1			T4	14		T5	24		T10	18
len_1025_2500	5400	1			T4	6		T5	14		T10	19
len_769_1024	6516	1			T4	1		T5	2		T9	6
len_513_768	6928	1			T4	1		T5	3		T9	8
len_257_512	21074	1			T4	2		T5	2		T9	10
len_0_256	256545	1			T4	9		T5	211		T9	13
len_keccak_block_sizes[72]	723	1			T5	2		T31	2		T38	3
len_keccak_block_sizes[104]	618	1			T5	2		T31	2		T38	3
len_keccak_block_sizes[136]	513	1			T38	3		T157	2		T34	2
len_keccak_block_sizes[144]	420	1			T38	3		T158	3		T159	3
len_keccak_block_sizes[168]	314	1			T38	3		T158	3		T159	3
len_1	758	1			T5	2		T29	1		T31	2
len_0	1211	1			T4	2		T5	2		T10	2