Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99389957	1			T1	5		T54	8		T55	8
all_pins[1]	99389957	1			T1	5		T54	8		T55	8
all_pins[2]	99389957	1			T1	5		T54	8		T55	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	247853804	1			T1	12		T54	15		T55	19
values[0x1]	50316067	1			T1	3		T54	9		T55	5
transitions[0x0=>0x1]	49935493	1			T1	3		T54	5		T55	4
transitions[0x1=>0x0]	49935513	1			T1	3		T54	6		T55	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98881869	1			T1	5		T54	5		T55	4
all_pins[0]	values[0x1]	508088	1			T54	3		T55	4		T57	2
all_pins[0]	transitions[0x0=>0x1]	215226	1			T54	3		T55	3		T57	2
all_pins[0]	transitions[0x1=>0x0]	49280829	1			T1	2		T54	1		T57	1
all_pins[1]	values[0x0]	49816266	1			T1	3		T54	7		T55	7
all_pins[1]	values[0x1]	49573691	1			T1	2		T54	1		T55	1
all_pins[1]	transitions[0x0=>0x1]	49487308	1			T1	2		T55	1		T60	1
all_pins[1]	transitions[0x1=>0x0]	147905	1			T1	1		T54	4		T60	1
all_pins[2]	values[0x0]	99155669	1			T1	4		T54	3		T55	8
all_pins[2]	values[0x1]	234288	1			T1	1		T54	5		T57	1
all_pins[2]	transitions[0x0=>0x1]	232959	1			T1	1		T54	2		T57	1
all_pins[2]	transitions[0x1=>0x0]	506779	1			T54	1		T55	4		T57	2