Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10947935 |
1 |
|
|
T4 |
16130 |
|
T5 |
3720 |
|
T9 |
5569 |
auto[1] |
10947820 |
1 |
|
|
T4 |
16130 |
|
T5 |
3720 |
|
T9 |
5569 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21656451 |
1 |
|
|
T4 |
32108 |
|
T5 |
7440 |
|
T9 |
11096 |
triple_byte_access |
78930 |
1 |
|
|
T4 |
44 |
|
T9 |
4 |
|
T10 |
88 |
halfword_access |
80436 |
1 |
|
|
T4 |
46 |
|
T9 |
24 |
|
T10 |
82 |
byte_access |
79938 |
1 |
|
|
T4 |
62 |
|
T9 |
14 |
|
T10 |
94 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10828283 |
1 |
|
|
T4 |
16054 |
|
T5 |
3720 |
|
T9 |
5548 |
auto[0] |
triple_byte_access |
39465 |
1 |
|
|
T4 |
22 |
|
T9 |
2 |
|
T10 |
44 |
auto[0] |
halfword_access |
40218 |
1 |
|
|
T4 |
23 |
|
T9 |
12 |
|
T10 |
41 |
auto[0] |
byte_access |
39969 |
1 |
|
|
T4 |
31 |
|
T9 |
7 |
|
T10 |
47 |
auto[1] |
word_access |
10828168 |
1 |
|
|
T4 |
16054 |
|
T5 |
3720 |
|
T9 |
5548 |
auto[1] |
triple_byte_access |
39465 |
1 |
|
|
T4 |
22 |
|
T9 |
2 |
|
T10 |
44 |
auto[1] |
halfword_access |
40218 |
1 |
|
|
T4 |
23 |
|
T9 |
12 |
|
T10 |
41 |
auto[1] |
byte_access |
39969 |
1 |
|
|
T4 |
31 |
|
T9 |
7 |
|
T10 |
47 |