Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 257 1 T1 4 T54 7 T55 7
all_values[1] 257 1 T1 4 T54 7 T55 7
all_values[2] 257 1 T1 4 T54 7 T55 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 394 1 T1 3 T54 6 T55 6
auto[1] 377 1 T1 9 T54 15 T55 15


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 321 1 T1 5 T54 6 T55 11
auto[1] 450 1 T1 7 T54 15 T55 10


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 469 1 T1 8 T54 13 T55 13
auto[1] 302 1 T1 4 T54 8 T55 8


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 44 1 T1 1 T57 3 T145 1
all_values[0] auto[0] auto[0] auto[1] 25 1 T1 1 T54 1 T115 1
all_values[0] auto[0] auto[1] auto[0] 57 1 T1 1 T54 1 T55 1
all_values[0] auto[0] auto[1] auto[1] 29 1 T54 2 T55 1 T57 1
all_values[0] auto[1] auto[0] auto[1] 54 1 T54 1 T57 3 T60 2
all_values[0] auto[1] auto[1] auto[1] 48 1 T1 1 T54 2 T55 5
all_values[1] auto[0] auto[0] auto[0] 59 1 T54 3 T57 2 T60 2
all_values[1] auto[0] auto[0] auto[1] 24 1 T55 1 T146 1 T147 1
all_values[1] auto[0] auto[1] auto[0] 45 1 T1 2 T54 2 T55 3
all_values[1] auto[0] auto[1] auto[1] 22 1 T1 1 T134 1 T148 1
all_values[1] auto[1] auto[0] auto[1] 55 1 T55 1 T57 3 T146 1
all_values[1] auto[1] auto[1] auto[1] 52 1 T1 1 T54 2 T55 2
all_values[2] auto[0] auto[0] auto[0] 60 1 T55 4 T57 2 T134 1
all_values[2] auto[0] auto[0] auto[1] 22 1 T1 1 T54 1 T60 2
all_values[2] auto[0] auto[1] auto[0] 56 1 T1 1 T55 3 T57 3
all_values[2] auto[0] auto[1] auto[1] 26 1 T54 3 T146 1 T134 1
all_values[2] auto[1] auto[0] auto[1] 51 1 T57 2 T60 2 T145 1
all_values[2] auto[1] auto[1] auto[1] 42 1 T1 2 T54 3 T145 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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