Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164332 |
1 |
|
|
T12 |
430 |
|
T32 |
116 |
|
T14 |
3 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
83504 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61061 |
1 |
|
|
T12 |
16 |
|
T32 |
114 |
|
T14 |
3 |
seven_bytes |
2784 |
1 |
|
|
T12 |
9 |
|
T37 |
23 |
|
T53 |
85 |
six_bytes |
2843 |
1 |
|
|
T12 |
24 |
|
T37 |
17 |
|
T53 |
114 |
five_bytes |
2910 |
1 |
|
|
T12 |
9 |
|
T37 |
18 |
|
T53 |
85 |
four_bytes |
2755 |
1 |
|
|
T12 |
9 |
|
T37 |
19 |
|
T53 |
97 |
three_bytes |
2872 |
1 |
|
|
T12 |
10 |
|
T37 |
17 |
|
T53 |
98 |
two_bytes |
2841 |
1 |
|
|
T12 |
11 |
|
T37 |
14 |
|
T53 |
74 |
one_byte |
2762 |
1 |
|
|
T12 |
12 |
|
T37 |
15 |
|
T53 |
73 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
161193 |
1 |
|
|
T12 |
426 |
|
T32 |
112 |
|
T14 |
3 |
auto[1] |
3139 |
1 |
|
|
T12 |
4 |
|
T32 |
4 |
|
T34 |
30 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164332 |
1 |
|
|
T12 |
430 |
|
T32 |
116 |
|
T14 |
3 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164326 |
1 |
|
|
T12 |
430 |
|
T32 |
116 |
|
T14 |
3 |
auto[1] |
6 |
1 |
|
|
T47 |
1 |
|
T157 |
1 |
|
T158 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1121 |
1 |
|
|
T32 |
2 |
|
T34 |
15 |
|
T46 |
38 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3139 |
1 |
|
|
T12 |
4 |
|
T32 |
4 |
|
T34 |
30 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170554 |
1 |
|
|
T12 |
119 |
|
T32 |
58 |
|
T33 |
167 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
86911 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
63215 |
1 |
|
|
T12 |
5 |
|
T32 |
57 |
|
T33 |
164 |
seven_bytes |
2993 |
1 |
|
|
T12 |
1 |
|
T42 |
1 |
|
T37 |
1 |
six_bytes |
2848 |
1 |
|
|
T12 |
5 |
|
T42 |
1 |
|
T37 |
2 |
five_bytes |
2861 |
1 |
|
|
T12 |
3 |
|
T42 |
1 |
|
T37 |
2 |
four_bytes |
3036 |
1 |
|
|
T12 |
1 |
|
T37 |
1 |
|
T53 |
35 |
three_bytes |
2943 |
1 |
|
|
T12 |
1 |
|
T42 |
2 |
|
T37 |
2 |
two_bytes |
2834 |
1 |
|
|
T12 |
1 |
|
T42 |
3 |
|
T37 |
1 |
one_byte |
2913 |
1 |
|
|
T12 |
4 |
|
T37 |
2 |
|
T53 |
32 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167296 |
1 |
|
|
T12 |
117 |
|
T32 |
56 |
|
T33 |
161 |
auto[1] |
3258 |
1 |
|
|
T12 |
2 |
|
T32 |
2 |
|
T33 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170554 |
1 |
|
|
T12 |
119 |
|
T32 |
58 |
|
T33 |
167 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170547 |
1 |
|
|
T12 |
119 |
|
T32 |
58 |
|
T33 |
167 |
auto[1] |
7 |
1 |
|
|
T46 |
2 |
|
T47 |
1 |
|
T159 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1163 |
1 |
|
|
T32 |
1 |
|
T33 |
3 |
|
T34 |
11 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3258 |
1 |
|
|
T12 |
2 |
|
T32 |
2 |
|
T33 |
6 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
340731 |
1 |
|
|
T13 |
12 |
|
T12 |
617 |
|
T32 |
121 |
auto[1] |
506 |
1 |
|
|
T46 |
103 |
|
T47 |
95 |
|
T49 |
43 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
179126 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
119566 |
1 |
|
|
T13 |
12 |
|
T12 |
15 |
|
T32 |
119 |
seven_bytes |
6105 |
1 |
|
|
T12 |
15 |
|
T37 |
49 |
|
T53 |
102 |
six_bytes |
6034 |
1 |
|
|
T12 |
15 |
|
T37 |
41 |
|
T53 |
88 |
five_bytes |
6042 |
1 |
|
|
T12 |
19 |
|
T37 |
37 |
|
T53 |
78 |
four_bytes |
6224 |
1 |
|
|
T12 |
17 |
|
T37 |
27 |
|
T53 |
86 |
three_bytes |
6158 |
1 |
|
|
T12 |
13 |
|
T37 |
30 |
|
T53 |
106 |
two_bytes |
6000 |
1 |
|
|
T12 |
17 |
|
T37 |
34 |
|
T53 |
106 |
one_byte |
5982 |
1 |
|
|
T12 |
18 |
|
T37 |
26 |
|
T53 |
83 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334725 |
1 |
|
|
T13 |
12 |
|
T12 |
611 |
|
T32 |
117 |
auto[1] |
6512 |
1 |
|
|
T12 |
6 |
|
T32 |
4 |
|
T33 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
341237 |
1 |
|
|
T13 |
12 |
|
T12 |
617 |
|
T32 |
121 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
341215 |
1 |
|
|
T13 |
12 |
|
T12 |
617 |
|
T32 |
121 |
auto[1] |
22 |
1 |
|
|
T31 |
1 |
|
T160 |
1 |
|
T161 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2243 |
1 |
|
|
T12 |
1 |
|
T32 |
2 |
|
T33 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6512 |
1 |
|
|
T12 |
6 |
|
T32 |
4 |
|
T33 |
6 |