Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

268134208

1

T1

155

T2

818

T3

136

full_word

189158204

1

T1

132

T2

1914

T3

489

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	457292122	1			T1	287		T2	2712		T3	625
auto[TlIntgErrCmd]	103	1			T2	6		T63	8		T118	5
auto[TlIntgErrData]	88	1			T2	7		T63	6		T118	4
auto[TlIntgErrBoth]	99	1			T2	7		T63	6		T118	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233709670

1

T1

273

T2

1519

T3

352

auto[1]

223582742

1

T1

14

T2

1213

T3

273

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	160779584	1			T1	155		T2	736		T3	126
auto[TlIntgErrNone]	partial	auto[1]	107354359	1			T2	62		T3	10		T58	10
auto[TlIntgErrNone]	full_word	auto[0]	72929943	1			T1	118		T2	776		T3	226
auto[TlIntgErrNone]	full_word	auto[1]	116228236	1			T1	14		T2	1138		T3	263
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T2	2		T63	2		T118	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T2	4		T63	5		T118	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T63	1		T118	1		T121	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T165	1		T163	1		T166	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T2	2		T63	4		T118	2
auto[TlIntgErrData]	partial	auto[1]	32	1			T2	5		T63	2		T118	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T123	1		T165	1		T167	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T119	1		T164	1		T168	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T2	3		T63	5		T121	3
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T2	4		T63	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T164	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T119	1		T169	1		-	-