Unified Coverage Report :: Module :: keccak_round

Module : keccak_round

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.32	92.94	100.00		73.33	90.32	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak	91.32	92.94	100.00		73.33	90.32	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.32	92.94	100.00		73.33	90.32	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.72	98.81	98.84	100.00	73.33	97.36	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.87	97.30	81.25		88.89	91.89	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak_p	99.30	100.00	98.75			98.45	100.00
u_prim_sec_anchor_buf	100.00	100.00
u_round_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
TOTAL		85	79	92.94
CONT_ASSIGN	134	0	0
ALWAYS	137	3	3	100.00
ALWAYS	143	56	51	91.07
CONT_ASSIGN	309	1	1	100.00
ALWAYS	327	6	6	100.00
CONT_ASSIGN	336	1	1	100.00
ALWAYS	344	7	7	100.00
ALWAYS	366	4	3	75.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
ALWAYS	427	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
134		unreachable
137	3	3
143	1	1
145	1	1
146	1	1
147	1	1
149	1	1
150	1	1
152	1	1
154	1	1
155	1	1
157	1	1
159	1	1
161	1	1
163	1	1
165	1	1
167	1	1
168	1	1
169	1	1
174	1	1
176	1	1
177	1	1
179	1	1
180	1	1
182		unreachable
184	1	1
190	0	1
192	0	1
193		unreachable
195		unreachable
196		unreachable
198	0	1
200	0	1
206	1	1
207	1	1
216	1	1
217	1	1
218	1	1
220	1	1
226	1	1
227	1	1
230	1	1
233	1	1
239	1	1
246	1	1
247	1	1
250	1	1
253	1	1
255	1	1
257	1	1
258	1	1
264	1	1
265	1	1
268	1	1
270	1	1
271		unreachable
273		unreachable
274		unreachable
276	1	1
278	1	1
283	0	1
288	1	1
289	1	1
301	1	1
302	1	1
			MISSING_ELSE
309	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
			MISSING_ELSE
336	1	1
344	1	1
345	1	1
346	1	1
347	1	1
351	1	1
352	1	1
355	1	1
			MISSING_ELSE
366	1	1
368	1	1
370	1	1
372	0	1
			MISSING_ELSE
			MISSING_ELSE
377	1	1
401	1	1
403	1	1
404	1	1
427	1	1
428	1	1
430	1	1

---

Cond Coverage for Module : keccak_round

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (int'(round) == (MaxRound - 1))
            ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Unreachable	T5,T6,T13

 LINE       177
 EXPRESSION (EnMasking && run_i)
             ----1----    --2--

-1-	-2-	Status	Tests
-	0	Covered	T4,T5,T6
-	1	Covered	T5,T6,T13

 LINE       216
 EXPRESSION (rand_early_i || rand_valid_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T34,T35
0	1	Covered	T5,T6,T13
1	0	Covered	T6,T34,T35

 LINE       309
 EXPRESSION ((keccak_st == KeccakStIdle) ? 1'b1 : 1'b0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T5,T6,T10
1	Covered	T4,T5,T6

 LINE       309
 SUB-EXPRESSION (keccak_st == KeccakStIdle)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       351
 EXPRESSION (addr_i == i[(DInAddr - 1):0])
            ---------------1--------------

-1-	Status	Tests
0	Covered	T5,T6,T13
1	Covered	T5,T6,T13

---

FSM Coverage for Module : keccak_round

Summary for FSM :: keccak_st

	Total	Covered	Percent
States	8	6	75.00	(Not included in score)
Transitions	15	11	73.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: keccak_st

---

states	Line No.	Covered	Tests
KeccakStActive	182	Not Covered
KeccakStError	283	Not Covered
KeccakStIdle	165	Covered	T1
KeccakStPhase1	179	Covered	T1
KeccakStPhase2Cycle1	217	Covered	T1
KeccakStPhase2Cycle2	233	Covered	T1
KeccakStPhase2Cycle3	255	Covered	T1
KeccakStTerminalError	302	Covered	T1

transitions	Line No.	Covered	Tests
KeccakStActive->KeccakStIdle	193	Not Covered
KeccakStActive->KeccakStTerminalError	302	Not Covered
KeccakStError->KeccakStTerminalError	302	Not Covered
KeccakStIdle->KeccakStActive	182	Not Covered
KeccakStIdle->KeccakStPhase1	179	Covered	T1
KeccakStIdle->KeccakStTerminalError	302	Covered	T1
KeccakStPhase1->KeccakStPhase2Cycle1	217	Covered	T1
KeccakStPhase1->KeccakStTerminalError	302	Covered	T1
KeccakStPhase2Cycle1->KeccakStPhase2Cycle2	233	Covered	T1
KeccakStPhase2Cycle1->KeccakStTerminalError	302	Covered	T1
KeccakStPhase2Cycle2->KeccakStPhase2Cycle3	255	Covered	T1
KeccakStPhase2Cycle2->KeccakStTerminalError	302	Covered	T1
KeccakStPhase2Cycle3->KeccakStIdle	271	Covered	T1
KeccakStPhase2Cycle3->KeccakStPhase1	276	Covered	T1
KeccakStPhase2Cycle3->KeccakStTerminalError	302	Covered	T1

---

Branch Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
Branches		31	28	90.32
TERNARY	309	2	2	100.00
IF	137	2	2	100.00
CASE	161	14	12	85.71
IF	301	2	2	100.00
IF	327	4	4	100.00
IF	345	2	2	100.00
IF	368	3	2	66.67
IF	427	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	309	((keccak_st == KeccakStIdle)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T5,T6,T10

	LineNo.	Expression
-1-:	137	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	161	case (keccak_st)
-2-:	163	if (valid_i)
-3-:	169	if (prim_mubi_pkg::mubi4_test_true_strict(clear_i))
-4-:	177	if ((EnMasking && run_i))
-5-:	180	if (((!EnMasking) && run_i))
-6-:	192	if (rnd_eq_end)
-7-:	216	if ((rand_early_i || rand_valid_i))
-8-:	246	if (rand_valid_i)
-9-:	270	if (rnd_eq_end)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KeccakStIdle	1	-	-	-	-	-	-	-	Covered	T5,T6,T13
KeccakStIdle	0	1	-	-	-	-	-	-	Covered	T5,T6,T11
KeccakStIdle	0	0	1	-	-	-	-	-	Covered	T5,T6,T13
KeccakStIdle	0	0	0	1	-	-	-	-	Unreachable
KeccakStIdle	0	0	0	0	-	-	-	-	Covered	T4,T5,T6
KeccakStActive	-	-	-	-	1	-	-	-	Unreachable
KeccakStActive	-	-	-	-	0	-	-	-	Not Covered
KeccakStPhase1	-	-	-	-	-	1	-	-	Covered	T5,T6,T13
KeccakStPhase1	-	-	-	-	-	0	-	-	Covered	T6,T34,T35
KeccakStPhase2Cycle1	-	-	-	-	-	-	-	-	Covered	T5,T6,T13
KeccakStPhase2Cycle2	-	-	-	-	-	-	1	-	Covered	T5,T6,T13
KeccakStPhase2Cycle2	-	-	-	-	-	-	0	-	Covered	T39,T40,T41
KeccakStPhase2Cycle3	-	-	-	-	-	-	-	1	Unreachable	T5,T6,T13
KeccakStPhase2Cycle3	-	-	-	-	-	-	-	0	Covered	T5,T6,T13
KeccakStError	-	-	-	-	-	-	-	-	Not Covered
KeccakStTerminalError	-	-	-	-	-	-	-	-	Covered	T10,T13,T14
default	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	301	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T10,T13,T14
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	327	if ((!rst_n))
-2-:	329	if (rst_storage)
-3-:	331	if (update_storage)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T6,T11
0	0	1	Covered	T5,T6,T13
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	345	if (xor_message)

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	368	if (rst_storage)
-2-:	370	if (((keccak_st != KeccakStIdle) || prim_mubi_pkg::mubi4_test_false_loose(clear_i)))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T5,T6,T11
0	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	427	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : keccak_round

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClearAssertStIdle_A	2147483647	345225	0	0
OneHot0ValidAndRun_A	2147483647	2147483647	0	0
ValidRunAssertStIdle_A	2147483647	56929703	0	0
WidthDivisableByDInWidth_A	1053	1053	0	0
gen_mask_st_chk.EnMaskingValidStates_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ClearAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345225	0	0
T5	550670	194	0	0
T6	147141	310	0	0
T10	6077	0	0	0
T11	202867	147	0	0
T12	228444	184	0	0
T13	2186	0	0	0
T14	5351	0	0	0
T32	365082	123	0	0
T33	546213	169	0	0
T34	671278	86	0	0
T35	0	18	0	0
T42	0	1	0	0
T43	0	246	0	0

OneHot0ValidAndRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

ValidRunAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	56929703	0	0
T5	550670	20753	0	0
T6	147141	76468	0	0
T10	6077	0	0	0
T11	202867	106294	0	0
T12	228444	33680	0	0
T13	2186	24	0	0
T14	5351	25	0	0
T32	365082	13643	0	0
T33	546213	18796	0	0
T34	671278	8874	0	0
T35	0	1827	0	0

WidthDivisableByDInWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

gen_mask_st_chk.EnMaskingValidStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0