Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	116414966	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1258	1258	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	116414966	0	0
T61	6100	474	0	0
T62	2518	160	0	0
T63	19877	0	0	0
T64	1781	0	0	0
T65	3060	386	0	0
T66	12197	0	0	0
T67	0	527	0	0
T68	0	552	0	0
T69	0	494	0	0
T73	3017	401	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T77	0	876	0	0
T78	0	167	0	0
T79	0	765	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258	1258	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	212151570	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1258	1258	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	212151570	0	0
T61	6100	1015	0	0
T62	2518	148	0	0
T63	19877	0	0	0
T64	1781	0	0	0
T65	3060	300	0	0
T66	12197	0	0	0
T67	0	426	0	0
T68	0	300	0	0
T69	0	394	0	0
T73	3017	215	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T77	0	460	0	0
T78	0	152	0	0
T79	0	383	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258	1258	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	323731013	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1258	1258	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	323731013	0	0
T1	2812	524	0	0
T2	24774	2974	0	0
T3	2503	1218	0	0
T58	946	22	0	0
T59	15541	13813	0	0
T60	1034	1	0	0
T61	6100	465	0	0
T62	2518	71	0	0
T63	19877	2981	0	0
T64	1781	514	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258	1258	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	597625916	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1258	1258	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	597625916	0	0
T1	2812	287	0	0
T2	24774	2732	0	0
T3	2503	625	0	0
T58	946	22	0	0
T59	15541	6965	0	0
T60	1034	1	0	0
T61	6100	1008	0	0
T62	2518	65	0	0
T63	19877	2721	0	0
T64	1781	268	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258	1258	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0