Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1473658	0	0
entropy_period_rd_A	2147483647	2082	0	0
intr_enable_rd_A	2147483647	2508	0	0
prefix_0_rd_A	2147483647	2033	0	0
prefix_10_rd_A	2147483647	2034	0	0
prefix_1_rd_A	2147483647	2111	0	0
prefix_2_rd_A	2147483647	1936	0	0
prefix_3_rd_A	2147483647	2143	0	0
prefix_4_rd_A	2147483647	1883	0	0
prefix_5_rd_A	2147483647	1996	0	0
prefix_6_rd_A	2147483647	2067	0	0
prefix_7_rd_A	2147483647	2061	0	0
prefix_8_rd_A	2147483647	1927	0	0
prefix_9_rd_A	2147483647	2064	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1473658	0	0
T2	24774	2	0	0
T3	2503	0	0	0
T58	946	0	0	0
T59	15541	0	0	0
T60	1034	0	0	0
T61	6100	165	0	0
T62	2518	0	0	0
T63	19877	3	0	0
T64	1781	0	0	0
T65	0	149	0	0
T66	12197	0	0	0
T67	0	311	0	0
T68	0	7	0	0
T69	0	269	0	0
T77	0	1	0	0
T121	0	2	0	0
T122	0	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2082	0	0
T24	0	162	0	0
T65	3060	0	0	0
T66	12197	67	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	40	0	0
T95	0	77	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	44	0	0
T119	0	88	0	0
T146	0	3	0	0
T148	0	13	0	0
T149	0	84	0	0
T150	0	118	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2508	0	0
T65	3060	0	0	0
T66	12197	64	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	36	0	0
T95	0	88	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T119	0	135	0	0
T146	0	19	0	0
T148	0	24	0	0
T151	0	19	0	0
T152	0	26	0	0
T153	0	10	0	0
T154	0	25	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2033	0	0
T24	0	95	0	0
T65	3060	0	0	0
T66	12197	20	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	27	0	0
T95	0	66	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	60	0	0
T119	0	56	0	0
T148	0	13	0	0
T149	0	122	0	0
T150	0	111	0	0
T155	0	34	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2034	0	0
T24	0	97	0	0
T65	3060	0	0	0
T66	12197	54	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	11	0	0
T95	0	38	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	49	0	0
T119	0	78	0	0
T146	0	3	0	0
T148	0	2	0	0
T149	0	53	0	0
T150	0	167	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2111	0	0
T24	0	121	0	0
T65	3060	0	0	0
T66	12197	52	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	42	0	0
T95	0	37	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	30	0	0
T119	0	85	0	0
T146	0	5	0	0
T148	0	5	0	0
T149	0	58	0	0
T150	0	134	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1936	0	0
T24	0	109	0	0
T65	3060	0	0	0
T66	12197	28	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	20	0	0
T95	0	51	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	54	0	0
T119	0	68	0	0
T148	0	9	0	0
T149	0	105	0	0
T150	0	99	0	0
T155	0	28	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2143	0	0
T24	0	96	0	0
T65	3060	0	0	0
T66	12197	25	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	12	0	0
T95	0	39	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	26	0	0
T119	0	107	0	0
T146	0	3	0	0
T148	0	11	0	0
T149	0	82	0	0
T150	0	173	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1883	0	0
T24	0	95	0	0
T65	3060	0	0	0
T66	12197	29	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	30	0	0
T95	0	50	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	57	0	0
T119	0	64	0	0
T148	0	4	0	0
T149	0	100	0	0
T150	0	69	0	0
T155	0	37	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1996	0	0
T24	0	106	0	0
T65	3060	0	0	0
T66	12197	10	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	31	0	0
T95	0	53	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	25	0	0
T119	0	74	0	0
T146	0	1	0	0
T149	0	119	0	0
T150	0	110	0	0
T155	0	40	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2067	0	0
T24	0	91	0	0
T65	3060	0	0	0
T66	12197	79	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	18	0	0
T95	0	58	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	36	0	0
T119	0	71	0	0
T146	0	5	0	0
T148	0	3	0	0
T149	0	104	0	0
T150	0	160	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2061	0	0
T24	0	106	0	0
T65	3060	0	0	0
T66	12197	58	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	28	0	0
T95	0	56	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	41	0	0
T119	0	112	0	0
T146	0	8	0	0
T148	0	6	0	0
T149	0	80	0	0
T150	0	95	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1927	0	0
T24	0	74	0	0
T65	3060	0	0	0
T66	12197	52	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	29	0	0
T95	0	56	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	25	0	0
T119	0	65	0	0
T146	0	3	0	0
T148	0	7	0	0
T149	0	106	0	0
T150	0	117	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2064	0	0
T24	0	163	0	0
T65	3060	0	0	0
T66	12197	47	0	0
T67	4065	0	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0
T89	0	30	0	0
T95	0	52	0	0
T104	659	0	0	0
T105	844	0	0	0
T106	817	0	0	0
T114	0	46	0	0
T119	0	69	0	0
T146	0	4	0	0
T148	0	6	0	0
T149	0	80	0	0
T150	0	108	0	0