Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183250 |
1 |
|
|
T4 |
918 |
|
T5 |
1021 |
|
T6 |
528 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
101248 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
58073 |
1 |
|
|
T4 |
280 |
|
T5 |
31 |
|
T6 |
519 |
seven_bytes |
3505 |
1 |
|
|
T4 |
18 |
|
T5 |
38 |
|
T23 |
21 |
six_bytes |
3410 |
1 |
|
|
T4 |
19 |
|
T5 |
28 |
|
T23 |
22 |
five_bytes |
3455 |
1 |
|
|
T4 |
12 |
|
T5 |
31 |
|
T23 |
22 |
four_bytes |
3368 |
1 |
|
|
T4 |
19 |
|
T5 |
30 |
|
T23 |
31 |
three_bytes |
3416 |
1 |
|
|
T4 |
13 |
|
T5 |
24 |
|
T23 |
25 |
two_bytes |
3337 |
1 |
|
|
T4 |
14 |
|
T5 |
25 |
|
T23 |
18 |
one_byte |
3438 |
1 |
|
|
T4 |
19 |
|
T5 |
27 |
|
T23 |
21 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179808 |
1 |
|
|
T4 |
902 |
|
T5 |
1009 |
|
T6 |
510 |
auto[1] |
3442 |
1 |
|
|
T4 |
16 |
|
T5 |
12 |
|
T6 |
18 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183250 |
1 |
|
|
T4 |
918 |
|
T5 |
1021 |
|
T6 |
528 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183233 |
1 |
|
|
T4 |
918 |
|
T5 |
1021 |
|
T6 |
528 |
auto[1] |
17 |
1 |
|
|
T40 |
1 |
|
T96 |
1 |
|
T104 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1144 |
1 |
|
|
T4 |
4 |
|
T5 |
3 |
|
T6 |
9 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3442 |
1 |
|
|
T4 |
16 |
|
T5 |
12 |
|
T6 |
18 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175607 |
1 |
|
|
T4 |
1011 |
|
T5 |
1179 |
|
T6 |
576 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
94955 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
58015 |
1 |
|
|
T4 |
108 |
|
T5 |
23 |
|
T6 |
566 |
seven_bytes |
3300 |
1 |
|
|
T4 |
20 |
|
T5 |
41 |
|
T23 |
10 |
six_bytes |
3174 |
1 |
|
|
T4 |
30 |
|
T5 |
31 |
|
T23 |
13 |
five_bytes |
3225 |
1 |
|
|
T4 |
22 |
|
T5 |
40 |
|
T23 |
15 |
four_bytes |
3246 |
1 |
|
|
T4 |
23 |
|
T5 |
36 |
|
T23 |
15 |
three_bytes |
3158 |
1 |
|
|
T4 |
20 |
|
T5 |
42 |
|
T23 |
14 |
two_bytes |
3189 |
1 |
|
|
T4 |
20 |
|
T5 |
36 |
|
T23 |
21 |
one_byte |
3345 |
1 |
|
|
T4 |
33 |
|
T5 |
35 |
|
T23 |
15 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172277 |
1 |
|
|
T4 |
997 |
|
T5 |
1161 |
|
T6 |
556 |
auto[1] |
3330 |
1 |
|
|
T4 |
14 |
|
T5 |
18 |
|
T6 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175607 |
1 |
|
|
T4 |
1011 |
|
T5 |
1179 |
|
T6 |
576 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175600 |
1 |
|
|
T4 |
1011 |
|
T5 |
1179 |
|
T6 |
576 |
auto[1] |
7 |
1 |
|
|
T23 |
1 |
|
T40 |
1 |
|
T147 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1115 |
1 |
|
|
T4 |
4 |
|
T5 |
6 |
|
T6 |
10 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3330 |
1 |
|
|
T4 |
14 |
|
T5 |
18 |
|
T6 |
20 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
368021 |
1 |
|
|
T4 |
927 |
|
T5 |
6357 |
|
T6 |
912 |
auto[1] |
369 |
1 |
|
|
T39 |
6 |
|
T40 |
29 |
|
T41 |
3 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
204166 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
115568 |
1 |
|
|
T4 |
245 |
|
T5 |
188 |
|
T6 |
899 |
seven_bytes |
7091 |
1 |
|
|
T4 |
12 |
|
T5 |
181 |
|
T23 |
52 |
six_bytes |
7077 |
1 |
|
|
T4 |
25 |
|
T5 |
171 |
|
T23 |
36 |
five_bytes |
6857 |
1 |
|
|
T4 |
24 |
|
T5 |
171 |
|
T23 |
31 |
four_bytes |
6846 |
1 |
|
|
T4 |
29 |
|
T5 |
191 |
|
T23 |
36 |
three_bytes |
6902 |
1 |
|
|
T4 |
24 |
|
T5 |
171 |
|
T23 |
42 |
two_bytes |
6979 |
1 |
|
|
T4 |
11 |
|
T5 |
170 |
|
T23 |
37 |
one_byte |
6904 |
1 |
|
|
T4 |
19 |
|
T5 |
178 |
|
T23 |
45 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
361702 |
1 |
|
|
T4 |
907 |
|
T5 |
6289 |
|
T6 |
886 |
auto[1] |
6688 |
1 |
|
|
T4 |
20 |
|
T5 |
68 |
|
T6 |
26 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
368390 |
1 |
|
|
T4 |
927 |
|
T5 |
6357 |
|
T6 |
912 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
368369 |
1 |
|
|
T4 |
927 |
|
T5 |
6357 |
|
T6 |
912 |
auto[1] |
21 |
1 |
|
|
T28 |
1 |
|
T148 |
1 |
|
T149 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2209 |
1 |
|
|
T4 |
8 |
|
T5 |
8 |
|
T6 |
13 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6688 |
1 |
|
|
T4 |
20 |
|
T5 |
68 |
|
T6 |
26 |