Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	265112347	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

192042002

1

T1

3554

T2

172

T3

54

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	236355995	1			T1	6845		T2	121		T3	138
values[0x0]	106022593	1			T1	63		T2	66		T3	3
values[0x1]	114775761	1			T1	57		T2	56		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	205886308	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

251268041

1

T1

4238

T2

187

T3

82

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1495709	1			T1	25		T53	3		T56	6
valid_sources[0x01]	2018595	1			T1	31		T2	3		T53	4
valid_sources[0x02]	2155613	1			T1	21		T2	1		T53	6
valid_sources[0x03]	1362469	1			T1	25		T56	9		T57	1
valid_sources[0x04]	2079424	1			T1	31		T53	4		T56	7
valid_sources[0x05]	1353994	1			T1	23		T2	1		T53	6
valid_sources[0x06]	1366329	1			T1	34		T2	2		T53	6
valid_sources[0x07]	1356763	1			T1	10		T2	1		T53	5
valid_sources[0x08]	1354847	1			T1	17		T53	4		T55	41
valid_sources[0x09]	1360228	1			T1	19		T2	1		T53	4
valid_sources[0x0a]	2053284	1			T1	23		T53	8		T56	2
valid_sources[0x0b]	1355457	1			T1	16		T53	4		T57	2
valid_sources[0x0c]	2646080	1			T1	27		T2	1		T53	12
valid_sources[0x0d]	1354797	1			T1	28		T53	11		T56	3
valid_sources[0x0e]	1615014	1			T1	32		T53	4		T56	2
valid_sources[0x0f]	1992954	1			T1	35		T53	4		T56	6
valid_sources[0x10]	2018262	1			T1	11		T53	1		T57	18
valid_sources[0x11]	1395492	1			T1	21		T53	5		T57	1
valid_sources[0x12]	1358702	1			T1	30		T53	7		T56	15
valid_sources[0x13]	1356283	1			T1	35		T2	3		T53	9
valid_sources[0x14]	1352785	1			T1	39		T2	3		T53	5
valid_sources[0x15]	1512792	1			T1	27		T2	2		T53	3
valid_sources[0x16]	2202848	1			T1	35		T2	3		T53	6
valid_sources[0x17]	1360036	1			T1	21		T2	4		T53	9
valid_sources[0x18]	1366377	1			T1	34		T53	3		T54	2
valid_sources[0x19]	2286790	1			T1	27		T2	1		T53	9
valid_sources[0x1a]	1355466	1			T1	18		T53	7		T56	35
valid_sources[0x1b]	1359565	1			T1	37		T53	7		T56	38
valid_sources[0x1c]	1354494	1			T1	38		T53	11		T56	24
valid_sources[0x1d]	1817926	1			T1	40		T53	7		T56	19
valid_sources[0x1e]	2229585	1			T1	22		T53	4		T56	4
valid_sources[0x1f]	1356485	1			T1	20		T52	31		T53	6
valid_sources[0x20]	3350233	1			T1	22		T2	1		T53	7
valid_sources[0x21]	1353909	1			T1	17		T3	8		T53	2
valid_sources[0x22]	1473898	1			T1	48		T2	2		T53	7
valid_sources[0x23]	1423181	1			T1	34		T2	1		T53	4
valid_sources[0x24]	1402992	1			T1	24		T52	29		T53	5
valid_sources[0x25]	3359895	1			T1	16		T2	1		T53	7
valid_sources[0x26]	3717225	1			T1	48		T2	1		T53	6
valid_sources[0x27]	1350982	1			T1	32		T2	2		T53	5
valid_sources[0x28]	3305077	1			T1	21		T2	1		T53	5
valid_sources[0x29]	3729729	1			T1	37		T2	1		T52	27
valid_sources[0x2a]	1476125	1			T1	12		T2	2		T53	5
valid_sources[0x2b]	1421518	1			T1	23		T2	3		T53	6
valid_sources[0x2c]	1355765	1			T1	24		T2	1		T53	2
valid_sources[0x2d]	1353562	1			T1	30		T53	6		T56	5
valid_sources[0x2e]	1359290	1			T1	27		T2	2		T53	3
valid_sources[0x2f]	1364067	1			T1	32		T2	2		T53	6
valid_sources[0x30]	1366438	1			T1	12		T2	6		T53	6
valid_sources[0x31]	1375603	1			T1	31		T53	9		T56	14
valid_sources[0x32]	1355730	1			T1	33		T2	3		T53	2
valid_sources[0x33]	2772835	1			T1	34		T53	8		T57	19
valid_sources[0x34]	2193751	1			T1	28		T2	2		T53	4
valid_sources[0x35]	1483125	1			T1	28		T53	4		T56	14
valid_sources[0x36]	1364510	1			T1	40		T2	1		T53	3
valid_sources[0x37]	1364375	1			T1	24		T53	7		T56	8
valid_sources[0x38]	1352137	1			T1	21		T2	2		T53	6
valid_sources[0x39]	1365827	1			T1	26		T2	2		T53	3
valid_sources[0x3a]	1361750	1			T1	34		T2	1		T53	6
valid_sources[0x3b]	1352197	1			T1	23		T2	1		T53	6
valid_sources[0x3c]	3364693	1			T1	18		T53	6		T54	1
valid_sources[0x3d]	1364185	1			T1	30		T2	1		T53	3
valid_sources[0x3e]	4610786	1			T1	42		T2	2		T53	9
valid_sources[0x3f]	2230705	1			T1	35		T53	3		T54	1
valid_sources[0x40]	1353021	1			T1	6		T53	4		T56	3
valid_sources[0x41]	1363622	1			T1	20		T53	7		T56	17
valid_sources[0x42]	1355369	1			T1	29		T53	3		T56	9
valid_sources[0x43]	2030820	1			T1	34		T53	2		T56	4
valid_sources[0x44]	2418918	1			T1	26		T2	1		T53	7
valid_sources[0x45]	1359883	1			T1	20		T2	1		T53	4
valid_sources[0x46]	2007424	1			T1	39		T53	3		T56	12
valid_sources[0x47]	2443807	1			T1	38		T2	1		T53	4
valid_sources[0x48]	1368732	1			T1	33		T53	5		T56	21
valid_sources[0x49]	2467410	1			T1	24		T2	1		T53	4
valid_sources[0x4a]	1362084	1			T1	17		T2	2		T53	5
valid_sources[0x4b]	3716986	1			T1	29		T53	7		T56	3
valid_sources[0x4c]	1360148	1			T1	38		T2	1		T53	5
valid_sources[0x4d]	1357074	1			T1	39		T53	3		T56	8
valid_sources[0x4e]	3691319	1			T1	26		T2	2		T53	2
valid_sources[0x4f]	1351834	1			T1	35		T2	3		T53	2
valid_sources[0x50]	1398512	1			T1	25		T2	3		T53	6
valid_sources[0x51]	1527925	1			T1	27		T2	2		T53	4
valid_sources[0x52]	1923821	1			T1	20		T2	1		T52	9
valid_sources[0x53]	1350093	1			T1	25		T2	3		T53	6
valid_sources[0x54]	1567264	1			T1	28		T53	5		T54	1
valid_sources[0x55]	2004805	1			T1	21		T2	1		T53	5
valid_sources[0x56]	1380097	1			T1	15		T53	6		T56	18
valid_sources[0x57]	1374063	1			T1	21		T2	1		T53	1
valid_sources[0x58]	1361759	1			T1	25		T2	2		T53	1
valid_sources[0x59]	2253524	1			T1	15		T52	7		T53	3
valid_sources[0x5a]	1359505	1			T1	16		T53	4		T56	8
valid_sources[0x5b]	1361588	1			T1	22		T2	1		T53	9
valid_sources[0x5c]	3359532	1			T1	37		T2	1		T53	4
valid_sources[0x5d]	1356885	1			T1	15		T53	5		T56	16
valid_sources[0x5e]	1363756	1			T1	24		T52	15		T53	3
valid_sources[0x5f]	1360168	1			T1	40		T2	3		T53	7
valid_sources[0x60]	1381595	1			T1	31		T2	1		T53	5
valid_sources[0x61]	1352520	1			T1	32		T52	30		T53	2
valid_sources[0x62]	1412336	1			T1	37		T2	1		T53	4
valid_sources[0x63]	3364934	1			T1	26		T2	1		T53	3
valid_sources[0x64]	1809293	1			T1	19		T53	7		T55	10
valid_sources[0x65]	2293329	1			T1	29		T2	1		T53	4
valid_sources[0x66]	1357051	1			T1	24		T2	1		T53	1
valid_sources[0x67]	1353235	1			T1	20		T2	1		T53	7
valid_sources[0x68]	1354390	1			T1	20		T2	1		T53	7
valid_sources[0x69]	2306069	1			T1	27		T2	1		T53	4
valid_sources[0x6a]	1365862	1			T1	17		T53	10		T56	15
valid_sources[0x6b]	1361414	1			T1	24		T2	1		T53	3
valid_sources[0x6c]	1490245	1			T1	28		T53	7		T4	1598
valid_sources[0x6d]	3201798	1			T1	22		T53	8		T54	1
valid_sources[0x6e]	3672598	1			T1	21		T53	6		T56	2
valid_sources[0x6f]	1357836	1			T1	29		T53	3		T57	9
valid_sources[0x70]	1458152	1			T1	33		T53	2		T57	2
valid_sources[0x71]	1347528	1			T1	19		T2	4		T53	8
valid_sources[0x72]	3998232	1			T1	13		T53	6		T56	9
valid_sources[0x73]	1362959	1			T1	28		T53	6		T56	3
valid_sources[0x74]	1371724	1			T1	10		T2	1		T53	3
valid_sources[0x75]	1816393	1			T1	35		T2	1		T53	2
valid_sources[0x76]	1814617	1			T1	19		T2	1		T53	6
valid_sources[0x77]	1358671	1			T1	14		T53	5		T56	9
valid_sources[0x78]	2027907	1			T1	39		T53	3		T56	14
valid_sources[0x79]	1442009	1			T1	44		T53	7		T56	49
valid_sources[0x7a]	1365726	1			T1	26		T53	3		T54	1
valid_sources[0x7b]	2292180	1			T1	22		T53	6		T56	6
valid_sources[0x7c]	1355536	1			T1	33		T52	9		T53	9
valid_sources[0x7d]	1357047	1			T1	43		T2	1		T53	4
valid_sources[0x7e]	2024091	1			T1	41		T2	1		T53	4
valid_sources[0x7f]	2208683	1			T1	21		T53	5		T56	14
valid_sources[0x80]	1349155	1			T1	34		T53	1		T56	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74224296

1

T1

3446

T2

60

T3

52

values[0x0]

all_enables

biggest_size

63206919

1

T1

59

T2

60

T3

1

values[0x1]

all_enables

biggest_size

54610787

1

T1

49

T2

52

T3

1