Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

271090388

1

T1

3411

T2

71

T3

92

full_word

192413574

1

T1

3554

T2

172

T3

54

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	463503692	1			T1	6965		T2	243		T3	146
auto[TlIntgErrCmd]	91	1			T53	6		T56	9		T57	3
auto[TlIntgErrData]	84	1			T53	1		T56	4		T57	8
auto[TlIntgErrBoth]	95	1			T53	3		T56	7		T57	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237498075

1

T1

6845

T2

121

T3

138

auto[1]

226005887

1

T1

120

T2

122

T3

8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	163180030	1			T1	3399		T2	61		T3	86
auto[TlIntgErrNone]	partial	auto[1]	107910112	1			T1	12		T2	10		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	74317931	1			T1	3446		T2	60		T3	52
auto[TlIntgErrNone]	full_word	auto[1]	118095619	1			T1	108		T2	112		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T53	3		T56	4		T57	3
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T53	3		T56	4		T150	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T56	1		T151	1		T152	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T150	1		T153	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T53	1		T56	3		T57	4
auto[TlIntgErrData]	partial	auto[1]	37	1			T56	1		T57	3		T150	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T57	1		T154	1		T151	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T151	1		T155	1		T156	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T53	2		T57	3		T150	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T56	5		T57	5		T150	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T53	1		T56	2		T57	1