Unified Coverage Report :: Module :: sha3

Module : sha3

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.45	97.30	81.25		81.82	91.89	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3	94.09	97.30	81.25		100.00	91.89	100.00

---

Module Instance : tb.dut.u_sha3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.09	97.30	81.25		100.00	91.89	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.50	98.83	95.67	100.00	88.10	96.40	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak	94.72	98.81	98.84	100.00	73.33	97.36	100.00
u_pad	96.34	99.45	88.37	100.00	94.44	95.79	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3

	Line No.	Total	Covered	Percent
TOTAL		74	72	97.30
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
ALWAYS	166	3	3	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	175	6	6	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
ALWAYS	195	3	3	100.00
ALWAYS	205	38	38	100.00
ALWAYS	300	3	3	100.00
ALWAYS	317	12	10	83.33

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
131	1	1
137	1	1
141	1	1
159	1	1
166	2	2
167	1	1
171	1	1
175	2	2
176	2	2
177	1	1
178	1	1
			MISSING_ELSE
182	1	1
185	1	1
186	1	1
188	1	1
195	3	3
205	1	1
208	1	1
209	1	1
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
220	1	1
222	1	1
223	1	1
225	1	1
227	1	1
232	1	1
233	1	1
235	1	1
236	1	1
237	1	1
239	1	1
244	1	1
245	1	1
247	1	1
249	1	1
250	1	1
252	1	1
253	1	1
254	1	1
256	1	1
258	1	1
263	1	1
264	1	1
266	1	1
271	1	1
276	1	1
277	1	1
289	1	1
290	1	1
			MISSING_ELSE
300	1	1
301	1	1
302	1	1
317	1	1
319	1	1
321	1	1
323	1	1
			MISSING_ELSE
332	1	1
334	1	1
			MISSING_ELSE
343	1	1
344	0	1
			MISSING_ELSE
353	1	1
355	1	1
			MISSING_ELSE
364	1	1
366	0	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       131
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       137
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T7,T8,T9
0	1	0	Covered	T7,T8,T9
1	0	0	Covered	T7,T8,T9

 LINE       159
 EXPRESSION (sha3pad_keccak_run | sw_keccak_run)
             ---------1--------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       232
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       343
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Module : sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	11	9	81.82
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	223	Covered	T1
StFlush_sparse	254	Covered	T1
StIdle_sparse	227	Covered	T1
StManualRun_sparse	250	Covered	T1
StSqueeze_sparse	237	Covered	T1
StTerminalError_sparse	276	Covered	T1

transitions	Line No.	Covered	Tests
StAbsorb_sparse->StSqueeze_sparse	237	Covered	T1
StAbsorb_sparse->StTerminalError_sparse	290	Covered	T1
StFlush_sparse->StIdle_sparse	271	Covered	T1
StFlush_sparse->StTerminalError_sparse	290	Not Covered
StIdle_sparse->StAbsorb_sparse	223	Covered	T1
StIdle_sparse->StTerminalError_sparse	290	Covered	T1
StManualRun_sparse->StSqueeze_sparse	264	Covered	T1
StManualRun_sparse->StTerminalError_sparse	290	Not Covered
StSqueeze_sparse->StFlush_sparse	254	Covered	T1
StSqueeze_sparse->StManualRun_sparse	250	Covered	T1
StSqueeze_sparse->StTerminalError_sparse	290	Covered	T1

---

Branch Coverage for Module : sha3

	Line No.	Total	Covered	Percent
Branches		37	34	91.89
IF	166	2	2	100.00
IF	175	4	4	100.00
IF	195	2	2	100.00
CASE	220	13	13	100.00
IF	289	2	2	100.00
CASE	300	3	2	66.67
CASE	319	11	9	81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	166	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	175	if ((!rst_ni))
-2-:	176	if (process_i)
-3-:	177	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	195	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	220	case (st)
-2-:	222	if (start_i)
-3-:	232	if ((process_i && (!processing)))
-4-:	236	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))
-5-:	249	if (run_i)
-6-:	253	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
-7-:	263	if (keccak_complete)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Covered	T4,T5,T6
StIdle_sparse	0	-	-	-	-	-	Covered	T4,T5,T6
StAbsorb_sparse	-	1	-	-	-	-	Covered	T4,T5,T6
StAbsorb_sparse	-	0	1	-	-	-	Covered	T4,T5,T6
StAbsorb_sparse	-	0	0	-	-	-	Covered	T4,T5,T6
StSqueeze_sparse	-	-	-	1	-	-	Covered	T4,T5,T6
StSqueeze_sparse	-	-	-	0	1	-	Covered	T4,T5,T6
StSqueeze_sparse	-	-	-	0	0	-	Covered	T4,T5,T6
StManualRun_sparse	-	-	-	-	-	1	Covered	T4,T5,T6
StManualRun_sparse	-	-	-	-	-	0	Covered	T4,T5,T6
StFlush_sparse	-	-	-	-	-	-	Covered	T4,T5,T6
StTerminalError_sparse	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	289	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	300	case (mux_sel)

Branches:

-1-	Status	Tests
MuxGuard	Covered	T4,T5,T6
MuxRelease	Covered	T4,T5,T6
default	Not Covered

	LineNo.	Expression
-1-:	319	case (st)
-2-:	321	if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-3-:	332	if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing)))
-4-:	343	if ((start_i || process_i))
-5-:	353	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-6-:	364	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Covered	T4,T13,T14
StIdle_sparse	0	-	-	-	-	Covered	T4,T5,T6
StAbsorb_sparse	-	1	-	-	-	Covered	T4,T13,T14
StAbsorb_sparse	-	0	-	-	-	Covered	T4,T5,T6
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Covered	T4,T5,T6
StManualRun_sparse	-	-	-	1	-	Covered	T4,T13,T14
StManualRun_sparse	-	-	-	0	-	Covered	T4,T5,T6
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Covered	T4,T5,T6
default	-	-	-	-	-	Covered	T10,T11,T12

---

Assert Coverage for Module : sha3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrDetection_A	2147483647	8972797	0	0
FsmKnown_A	2147483647	2147483647	0	0
MuxSelKnown_A	2147483647	2147483647	0	0
SwRunInSqueezing_a	2147483647	163248	0	0
gen_chk_digest_masked.StateZeroInvalid_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ErrDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8972797	0	0
T4	630381	56210	0	0
T5	145678	0	0	0
T6	205661	0	0	0
T10	3735	0	0	0
T13	0	291746	0	0
T14	0	118635	0	0
T15	0	360891	0	0
T16	0	52837	0	0
T17	0	53638	0	0
T18	0	41915	0	0
T19	0	456060	0	0
T20	0	84633	0	0
T21	0	67166	0	0
T22	542998	0	0	0
T23	285453	0	0	0
T24	191102	0	0	0
T25	610750	0	0	0
T26	37315	0	0	0
T27	993181	0	0	0

FsmKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	630381	630366	0	0
T5	145678	145671	0	0
T6	205661	205573	0	0
T10	3735	3582	0	0
T22	542998	542989	0	0
T23	285453	285400	0	0
T24	191102	191036	0	0
T25	610750	610743	0	0
T26	37315	37253	0	0
T27	993181	993176	0	0

MuxSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	630381	630366	0	0
T5	145678	145671	0	0
T6	205661	205573	0	0
T10	3735	3582	0	0
T22	542998	542989	0	0
T23	285453	285400	0	0
T24	191102	191036	0	0
T25	610750	610743	0	0
T26	37315	37253	0	0
T27	993181	993176	0	0

SwRunInSqueezing_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	163248	0	0
T4	630381	551	0	0
T5	145678	455	0	0
T6	205661	148	0	0
T10	3735	0	0	0
T13	0	1158	0	0
T14	0	295	0	0
T22	542998	389	0	0
T23	285453	153	0	0
T24	191102	63	0	0
T25	610750	0	0	0
T26	37315	0	0	0
T27	993181	0	0	0
T28	0	485	0	0
T29	0	101	0	0

gen_chk_digest_masked.StateZeroInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	630381	578995	0	0
T5	145678	111423	0	0
T6	205661	157452	0	0
T10	3735	3582	0	0
T22	542998	512413	0	0
T23	285453	235889	0	0
T24	191102	118916	0	0
T25	610750	588071	0	0
T26	37315	37253	0	0
T27	993181	968005	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	630381	630366	0	0
T5	145678	145671	0	0
T6	205661	205573	0	0
T10	3735	3582	0	0
T22	542998	542989	0	0
T23	285453	285400	0	0
T24	191102	191036	0	0
T25	610750	610743	0	0
T26	37315	37253	0	0
T27	993181	993176	0	0

Line Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
TOTAL		74	72	97.30
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
ALWAYS	166	3	3	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	175	6	6	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
ALWAYS	195	3	3	100.00
ALWAYS	205	38	38	100.00
ALWAYS	300	3	3	100.00
ALWAYS	317	12	10	83.33

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
131	1	1
137	1	1
141	1	1
159	1	1
166	2	2
167	1	1
171	1	1
175	2	2
176	2	2
177	1	1
178	1	1
			MISSING_ELSE
182	1	1
185	1	1
186	1	1
188	1	1
195	3	3
205	1	1
208	1	1
209	1	1
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
220	1	1
222	1	1
223	1	1
225	1	1
227	1	1
232	1	1
233	1	1
235	1	1
236	1	1
237	1	1
239	1	1
244	1	1
245	1	1
247	1	1
249	1	1
250	1	1
252	1	1
253	1	1
254	1	1
256	1	1
258	1	1
263	1	1
264	1	1
266	1	1
271	1	1
276	1	1
277	1	1
289	1	1
290	1	1
			MISSING_ELSE
300	1	1
301	1	1
302	1	1
317	1	1
319	1	1
321	1	1
323	1	1
			MISSING_ELSE
332	1	1
334	1	1
			MISSING_ELSE
343	1	1
344	0	1
			MISSING_ELSE
353	1	1
355	1	1
			MISSING_ELSE
364	1	1
366	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       131
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       137
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T7,T8,T9
0	1	0	Covered	T7,T8,T9
1	0	0	Covered	T7,T8,T9

 LINE       159
 EXPRESSION (sha3pad_keccak_run | sw_keccak_run)
             ---------1--------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       232
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       343
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	223	Covered	T1
StFlush_sparse	254	Covered	T1
StIdle_sparse	227	Covered	T1
StManualRun_sparse	250	Covered	T1
StSqueeze_sparse	237	Covered	T1
StTerminalError_sparse	276	Covered	T1

transitions	Line No.	Covered	Tests	Exclude Annotation
StAbsorb_sparse->StSqueeze_sparse	237	Covered	T1
StAbsorb_sparse->StTerminalError_sparse	290	Covered	T1
StFlush_sparse->StIdle_sparse	271	Covered	T1
StFlush_sparse->StTerminalError_sparse	290	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StIdle_sparse->StAbsorb_sparse	223	Covered	T1
StIdle_sparse->StTerminalError_sparse	290	Covered	T1
StManualRun_sparse->StSqueeze_sparse	264	Covered	T1
StManualRun_sparse->StTerminalError_sparse	290	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StSqueeze_sparse->StFlush_sparse	254	Covered	T1
StSqueeze_sparse->StManualRun_sparse	250	Covered	T1
StSqueeze_sparse->StTerminalError_sparse	290	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
Branches		37	34	91.89
IF	166	2	2	100.00
IF	175	4	4	100.00
IF	195	2	2	100.00
CASE	220	13	13	100.00
IF	289	2	2	100.00
CASE	300	3	2	66.67
CASE	319	11	9	81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	166	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	175	if ((!rst_ni))
-2-:	176	if (process_i)
-3-:	177	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	195	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	220	case (st)
-2-:	222	if (start_i)
-3-:	232	if ((process_i && (!processing)))
-4-:	236	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))
-5-:	249	if (run_i)
-6-:	253	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
-7-:	263	if (keccak_complete)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Covered	T4,T5,T6
StIdle_sparse	0	-	-	-	-	-	Covered	T4,T5,T6
StAbsorb_sparse	-	1	-	-	-	-	Covered	T4,T5,T6
StAbsorb_sparse	-	0	1	-	-	-	Covered	T4,T5,T6
StAbsorb_sparse	-	0	0	-	-	-	Covered	T4,T5,T6
StSqueeze_sparse	-	-	-	1	-	-	Covered	T4,T5,T6
StSqueeze_sparse	-	-	-	0	1	-	Covered	T4,T5,T6
StSqueeze_sparse	-	-	-	0	0	-	Covered	T4,T5,T6
StManualRun_sparse	-	-	-	-	-	1	Covered	T4,T5,T6
StManualRun_sparse	-	-	-	-	-	0	Covered	T4,T5,T6
StFlush_sparse	-	-	-	-	-	-	Covered	T4,T5,T6
StTerminalError_sparse	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	289	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	300	case (mux_sel)

Branches:

-1-	Status	Tests
MuxGuard	Covered	T4,T5,T6
MuxRelease	Covered	T4,T5,T6
default	Not Covered

	LineNo.	Expression
-1-:	319	case (st)
-2-:	321	if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-3-:	332	if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing)))
-4-:	343	if ((start_i || process_i))
-5-:	353	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-6-:	364	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Covered	T4,T13,T14
StIdle_sparse	0	-	-	-	-	Covered	T4,T5,T6
StAbsorb_sparse	-	1	-	-	-	Covered	T4,T13,T14
StAbsorb_sparse	-	0	-	-	-	Covered	T4,T5,T6
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Covered	T4,T5,T6
StManualRun_sparse	-	-	-	1	-	Covered	T4,T13,T14
StManualRun_sparse	-	-	-	0	-	Covered	T4,T5,T6
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Covered	T4,T5,T6
default	-	-	-	-	-	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_sha3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrDetection_A	2147483647	8972797	0	0
FsmKnown_A	2147483647	2147483647	0	0
MuxSelKnown_A	2147483647	2147483647	0	0
SwRunInSqueezing_a	2147483647	163248	0	0
gen_chk_digest_masked.StateZeroInvalid_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ErrDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8972797	0	0
T4	630381	56210	0	0
T5	145678	0	0	0
T6	205661	0	0	0
T10	3735	0	0	0
T13	0	291746	0	0
T14	0	118635	0	0
T15	0	360891	0	0
T16	0	52837	0	0
T17	0	53638	0	0
T18	0	41915	0	0
T19	0	456060	0	0
T20	0	84633	0	0
T21	0	67166	0	0
T22	542998	0	0	0
T23	285453	0	0	0
T24	191102	0	0	0
T25	610750	0	0	0
T26	37315	0	0	0
T27	993181	0	0	0

FsmKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	630381	630366	0	0
T5	145678	145671	0	0
T6	205661	205573	0	0
T10	3735	3582	0	0
T22	542998	542989	0	0
T23	285453	285400	0	0
T24	191102	191036	0	0
T25	610750	610743	0	0
T26	37315	37253	0	0
T27	993181	993176	0	0

MuxSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	630381	630366	0	0
T5	145678	145671	0	0
T6	205661	205573	0	0
T10	3735	3582	0	0
T22	542998	542989	0	0
T23	285453	285400	0	0
T24	191102	191036	0	0
T25	610750	610743	0	0
T26	37315	37253	0	0
T27	993181	993176	0	0

SwRunInSqueezing_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	163248	0	0
T4	630381	551	0	0
T5	145678	455	0	0
T6	205661	148	0	0
T10	3735	0	0	0
T13	0	1158	0	0
T14	0	295	0	0
T22	542998	389	0	0
T23	285453	153	0	0
T24	191102	63	0	0
T25	610750	0	0	0
T26	37315	0	0	0
T27	993181	0	0	0
T28	0	485	0	0
T29	0	101	0	0

gen_chk_digest_masked.StateZeroInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	630381	578995	0	0
T5	145678	111423	0	0
T6	205661	157452	0	0
T10	3735	3582	0	0
T22	542998	512413	0	0
T23	285453	235889	0	0
T24	191102	118916	0	0
T25	610750	588071	0	0
T26	37315	37253	0	0
T27	993181	968005	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	630381	630366	0	0
T5	145678	145671	0	0
T6	205661	205573	0	0
T10	3735	3582	0	0
T22	542998	542989	0	0
T23	285453	285400	0	0
T24	191102	191036	0	0
T25	610750	610743	0	0
T26	37315	37253	0	0
T27	993181	993176	0	0