Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	352675	0	0
RunThenComplete_M	2147483647	3163568	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352675	0	0
T4	630381	209	0	0
T5	145678	173	0	0
T6	205661	73	0	0
T10	3735	0	0	0
T22	542998	112	0	0
T23	285453	65	0	0
T24	191102	20	0	0
T25	610750	374	0	0
T26	37315	0	0	0
T27	993181	390	0	0
T35	0	374	0	0
T36	0	2337	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3163568	0	0
T4	630381	5499	0	0
T5	145678	952	0	0
T6	205661	348	0	0
T10	3735	0	0	0
T22	542998	4391	0	0
T23	285453	302	0	0
T24	191102	95	0	0
T25	610750	5526	0	0
T26	37315	0	0	0
T27	993181	5542	0	0
T35	0	5526	0	0
T36	0	13147	0	0