Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo.u_packer	98.08	100.00	100.00			92.31	100.00

---

Module Instance : tb.dut.u_msgfifo.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.41	100.00	100.00	89.74		92.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.21	100.00			100.00	92.86	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_pos_dupcnt.u_pos	89.74			89.74

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
ALWAYS	120	3	3	100.00
ALWAYS	156	4	4	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	184	9	9	100.00
ALWAYS	213	8	8	100.00
ALWAYS	234	3	3	100.00
ALWAYS	242	14	14	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	290	0	0
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	298	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
110	1	1
111	1	1
112	1	1
115	1	1
120	1	1
122	1	1
124	1	1
			MISSING_ELSE
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
164	1	1
165	1	1
169	1	1
170	1	1
173	1	1
174	1	1
177	1	1
179	1	1
184	1	1
186	1	1
187	1	1
191	1	1
192	1	1
196	1	1
197	1	1
201	1	1
202	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
234	1	1
235	1	1
237	1	1
242	1	1
244	1	1
245	1	1
247	1	1
249	1	1
250	1	1
252	1	1
257	1	1
258	1	1
260	1	1
261	1	1
263	1	1
265	1	1
266	1	1
278	1	1
282	1	1
290		unreachable
293	1	1
294	1	1
295	1	1
298		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       110
 EXPRESSION (ack_in && ((!ack_out)))
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       111
 EXPRESSION (((!ack_in)) && ack_out)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       112
 EXPRESSION (ack_in && ack_out)
             ---1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       115
 EXPRESSION (g_pos_dupcnt.cnt_incr_en ? (8'(inmask_ones)) : (8'(OutW)))
             ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       158
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       164
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       165
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T29,T13
1	1	Covered	T4,T5,T6

 LINE       169
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       170
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       257
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       282
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Unreachable	T4,T5,T6

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		26	24	92.31
TERNARY	169	2	2	100.00
TERNARY	170	2	2	100.00
TERNARY	282	1	1	100.00
TERNARY	115	2	2	100.00
IF	158	2	2	100.00
CASE	184	5	4	80.00
IF	213	3	3	100.00
IF	234	2	2	100.00
CASE	247	5	4	80.00
IF	122	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	169	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	282	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	(g_pos_dupcnt.cnt_incr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	158	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	184	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Covered	T4,T5,T6
2'b01	Covered	T4,T5,T6
2'b10	Covered	T4,T5,T6
2'b11	Covered	T4,T5,T6
default	Not Covered

	LineNo.	Expression
-1-:	213	if ((!rst_ni))
-2-:	216	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	234	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	247	case (flush_st)
-2-:	249	if (flush_i)
-3-:	257	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T4,T5,T6
FlushIdle	0	-	Covered	T4,T5,T6
FlushSend	-	1	Covered	T4,T5,T6
FlushSend	-	0	Covered	T4,T5,T6
default	-	-	Not Covered

	LineNo.	Expression
-1-:	122	if ((pos_with_input > 8'(OutW)))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	28	28	100.00	28	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	28	28	100.00	28	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	2147483647	332468	0	1050
DataOStableWhenPending_A	2147483647	570850	0	1050
ExFlushValid_M	2147483647	352675	0	0
ExcessiveDataStored_A	2147483647	33874	0	0
ExcessiveMaskStored_A	2147483647	33874	0	0
FlushFollowedByDone_A	2147483647	352675	0	1050
ValidIDeassertedOnFlush_M	2147483647	563717	0	0
ValidOAssertedForStoredDataGTEOutW_A	2147483647	49446714	0	0
ValidOPairedWidthReadyI_A	2147483647	570850	0	0
g_byte_assert.InputDividedBy8_A	1050	1050	0	0
g_byte_assert.OutputDividedBy8_A	1050	1050	0	0
g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A	2147483647	111984843	0	0
g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A	2147483647	111984843	0	0
g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A	2147483647	111984843	0	0
g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A	2147483647	111984843	0	0
g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A	2147483647	111984843	0	0
g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A	2147483647	111984843	0	0
g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A	2147483647	111984843	0	0
g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A	2147483647	111984843	0	0
g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A	2147483647	49653101	0	0
g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A	2147483647	49653101	0	0
g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A	2147483647	49653101	0	0
g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A	2147483647	49653101	0	0
g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A	2147483647	49653101	0	0
g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A	2147483647	49653101	0	0
g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A	2147483647	49653101	0	0
g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A	2147483647	49653101	0	0
gen_mask_assert.ContiguousOnesMask_M	2147483647	111984843	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	332468	0	1050
T4	630381	4	0	1
T5	145678	17	0	1
T6	205661	2440	0	1
T10	3735	0	0	1
T13	0	4052	0	0
T14	0	1075	0	0
T15	0	7270	0	0
T16	0	3899	0	0
T22	542998	0	0	1
T23	285453	6	0	1
T24	191102	0	0	1
T25	610750	0	0	1
T26	37315	0	0	1
T27	993181	0	0	1
T28	0	9	0	0
T29	0	1220	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	570850	0	1050
T6	205661	2549	0	1
T10	3735	0	0	1
T13	0	4248	0	0
T14	0	997	0	0
T15	0	7563	0	0
T16	0	4876	0	0
T22	542998	0	0	1
T23	285453	0	0	1
T24	191102	0	0	1
T25	610750	0	0	1
T26	37315	0	0	1
T27	993181	0	0	1
T29	0	1220	0	0
T35	196926	0	0	1
T50	0	1118	0	0
T60	0	2771	0	0
T83	0	13436	0	0
T84	0	9802	0	0
T85	1843	0	0	1

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352675	0	0
T4	630381	209	0	0
T5	145678	173	0	0
T6	205661	73	0	0
T10	3735	0	0	0
T22	542998	112	0	0
T23	285453	65	0	0
T24	191102	20	0	0
T25	610750	374	0	0
T26	37315	0	0	0
T27	993181	390	0	0
T35	0	374	0	0
T36	0	2337	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33874	0	0
T4	630381	6	0	0
T5	145678	4	0	0
T6	205661	499	0	0
T10	3735	0	0	0
T13	0	829	0	0
T14	0	48	0	0
T15	0	978	0	0
T16	0	216	0	0
T17	0	2	0	0
T22	542998	0	0	0
T23	285453	0	0	0
T24	191102	0	0	0
T25	610750	0	0	0
T26	37315	0	0	0
T27	993181	0	0	0
T28	0	4	0	0
T29	0	244	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33874	0	0
T4	630381	6	0	0
T5	145678	4	0	0
T6	205661	499	0	0
T10	3735	0	0	0
T13	0	829	0	0
T14	0	48	0	0
T15	0	978	0	0
T16	0	216	0	0
T17	0	2	0	0
T22	542998	0	0	0
T23	285453	0	0	0
T24	191102	0	0	0
T25	610750	0	0	0
T26	37315	0	0	0
T27	993181	0	0	0
T28	0	4	0	0
T29	0	244	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352675	0	1050
T4	630381	209	0	1
T5	145678	173	0	1
T6	205661	73	0	1
T10	3735	0	0	1
T22	542998	112	0	1
T23	285453	65	0	1
T24	191102	20	0	1
T25	610750	374	0	1
T26	37315	0	0	1
T27	993181	390	0	1
T35	0	374	0	0
T36	0	2337	0	0

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	563717	0	0
T4	630381	390	0	0
T5	145678	330	0	0
T6	205661	228	0	0
T10	3735	0	0	0
T22	542998	209	0	0
T23	285453	121	0	0
T24	191102	36	0	0
T25	610750	700	0	0
T26	37315	0	0	0
T27	993181	730	0	0
T35	0	700	0	0
T36	0	3395	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49446714	0	0
T4	630381	94364	0	0
T5	145678	11733	0	0
T6	205661	6760	0	0
T10	3735	0	0	0
T22	542998	78594	0	0
T23	285453	3778	0	0
T24	191102	1145	0	0
T25	610750	90348	0	0
T26	37315	0	0	0
T27	993181	95772	0	0
T35	0	90348	0	0
T36	0	240518	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	570850	0	0
T6	205661	2549	0	0
T10	3735	0	0	0
T13	0	4248	0	0
T14	0	997	0	0
T15	0	7563	0	0
T16	0	4876	0	0
T22	542998	0	0	0
T23	285453	0	0	0
T24	191102	0	0	0
T25	610750	0	0	0
T26	37315	0	0	0
T27	993181	0	0	0
T29	0	1220	0	0
T35	196926	0	0	0
T50	0	1118	0	0
T60	0	2771	0	0
T83	0	13436	0	0
T84	0	9802	0	0
T85	1843	0	0	0

g_byte_assert.InputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

g_byte_assert.OutputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111984843	0	0
T4	630381	189931	0	0
T5	145678	27527	0	0
T6	205661	9496	0	0
T10	3735	0	0	0
T22	542998	184238	0	0
T23	285453	8930	0	0
T24	191102	2472	0	0
T25	610750	207382	0	0
T26	37315	0	0	0
T27	993181	227709	0	0
T35	0	212830	0	0
T36	0	553948	0	0

g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111984843	0	0
T4	630381	189931	0	0
T5	145678	27527	0	0
T6	205661	9496	0	0
T10	3735	0	0	0
T22	542998	184238	0	0
T23	285453	8930	0	0
T24	191102	2472	0	0
T25	610750	207382	0	0
T26	37315	0	0	0
T27	993181	227709	0	0
T35	0	212830	0	0
T36	0	553948	0	0

g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111984843	0	0
T4	630381	189931	0	0
T5	145678	27527	0	0
T6	205661	9496	0	0
T10	3735	0	0	0
T22	542998	184238	0	0
T23	285453	8930	0	0
T24	191102	2472	0	0
T25	610750	207382	0	0
T26	37315	0	0	0
T27	993181	227709	0	0
T35	0	212830	0	0
T36	0	553948	0	0

g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111984843	0	0
T4	630381	189931	0	0
T5	145678	27527	0	0
T6	205661	9496	0	0
T10	3735	0	0	0
T22	542998	184238	0	0
T23	285453	8930	0	0
T24	191102	2472	0	0
T25	610750	207382	0	0
T26	37315	0	0	0
T27	993181	227709	0	0
T35	0	212830	0	0
T36	0	553948	0	0

g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111984843	0	0
T4	630381	189931	0	0
T5	145678	27527	0	0
T6	205661	9496	0	0
T10	3735	0	0	0
T22	542998	184238	0	0
T23	285453	8930	0	0
T24	191102	2472	0	0
T25	610750	207382	0	0
T26	37315	0	0	0
T27	993181	227709	0	0
T35	0	212830	0	0
T36	0	553948	0	0

g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111984843	0	0
T4	630381	189931	0	0
T5	145678	27527	0	0
T6	205661	9496	0	0
T10	3735	0	0	0
T22	542998	184238	0	0
T23	285453	8930	0	0
T24	191102	2472	0	0
T25	610750	207382	0	0
T26	37315	0	0	0
T27	993181	227709	0	0
T35	0	212830	0	0
T36	0	553948	0	0

g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111984843	0	0
T4	630381	189931	0	0
T5	145678	27527	0	0
T6	205661	9496	0	0
T10	3735	0	0	0
T22	542998	184238	0	0
T23	285453	8930	0	0
T24	191102	2472	0	0
T25	610750	207382	0	0
T26	37315	0	0	0
T27	993181	227709	0	0
T35	0	212830	0	0
T36	0	553948	0	0

g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111984843	0	0
T4	630381	189931	0	0
T5	145678	27527	0	0
T6	205661	9496	0	0
T10	3735	0	0	0
T22	542998	184238	0	0
T23	285453	8930	0	0
T24	191102	2472	0	0
T25	610750	207382	0	0
T26	37315	0	0	0
T27	993181	227709	0	0
T35	0	212830	0	0
T36	0	553948	0	0

g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49653101	0	0
T4	630381	94545	0	0
T5	145678	11890	0	0
T6	205661	6806	0	0
T10	3735	0	0	0
T22	542998	78691	0	0
T23	285453	3834	0	0
T24	191102	1161	0	0
T25	610750	90674	0	0
T26	37315	0	0	0
T27	993181	96112	0	0
T35	0	90674	0	0
T36	0	241576	0	0

g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49653101	0	0
T4	630381	94545	0	0
T5	145678	11890	0	0
T6	205661	6806	0	0
T10	3735	0	0	0
T22	542998	78691	0	0
T23	285453	3834	0	0
T24	191102	1161	0	0
T25	610750	90674	0	0
T26	37315	0	0	0
T27	993181	96112	0	0
T35	0	90674	0	0
T36	0	241576	0	0

g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49653101	0	0
T4	630381	94545	0	0
T5	145678	11890	0	0
T6	205661	6806	0	0
T10	3735	0	0	0
T22	542998	78691	0	0
T23	285453	3834	0	0
T24	191102	1161	0	0
T25	610750	90674	0	0
T26	37315	0	0	0
T27	993181	96112	0	0
T35	0	90674	0	0
T36	0	241576	0	0

g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49653101	0	0
T4	630381	94545	0	0
T5	145678	11890	0	0
T6	205661	6806	0	0
T10	3735	0	0	0
T22	542998	78691	0	0
T23	285453	3834	0	0
T24	191102	1161	0	0
T25	610750	90674	0	0
T26	37315	0	0	0
T27	993181	96112	0	0
T35	0	90674	0	0
T36	0	241576	0	0

g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49653101	0	0
T4	630381	94545	0	0
T5	145678	11890	0	0
T6	205661	6806	0	0
T10	3735	0	0	0
T22	542998	78691	0	0
T23	285453	3834	0	0
T24	191102	1161	0	0
T25	610750	90674	0	0
T26	37315	0	0	0
T27	993181	96112	0	0
T35	0	90674	0	0
T36	0	241576	0	0

g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49653101	0	0
T4	630381	94545	0	0
T5	145678	11890	0	0
T6	205661	6806	0	0
T10	3735	0	0	0
T22	542998	78691	0	0
T23	285453	3834	0	0
T24	191102	1161	0	0
T25	610750	90674	0	0
T26	37315	0	0	0
T27	993181	96112	0	0
T35	0	90674	0	0
T36	0	241576	0	0

g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49653101	0	0
T4	630381	94545	0	0
T5	145678	11890	0	0
T6	205661	6806	0	0
T10	3735	0	0	0
T22	542998	78691	0	0
T23	285453	3834	0	0
T24	191102	1161	0	0
T25	610750	90674	0	0
T26	37315	0	0	0
T27	993181	96112	0	0
T35	0	90674	0	0
T36	0	241576	0	0

g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49653101	0	0
T4	630381	94545	0	0
T5	145678	11890	0	0
T6	205661	6806	0	0
T10	3735	0	0	0
T22	542998	78691	0	0
T23	285453	3834	0	0
T24	191102	1161	0	0
T25	610750	90674	0	0
T26	37315	0	0	0
T27	993181	96112	0	0
T35	0	90674	0	0
T36	0	241576	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111984843	0	0
T4	630381	189931	0	0
T5	145678	27527	0	0
T6	205661	9496	0	0
T10	3735	0	0	0
T22	542998	184238	0	0
T23	285453	8930	0	0
T24	191102	2472	0	0
T25	610750	207382	0	0
T26	37315	0	0	0
T27	993181	227709	0	0
T35	0	212830	0	0
T36	0	553948	0	0