Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	117974439	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1211	1211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117974439	0	0
T4	630381	301988	0	0
T5	145678	18968	0	0
T6	0	5059	0	0
T10	0	20	0	0
T22	0	184238	0	0
T23	0	5910	0	0
T24	0	2418	0	0
T25	0	207382	0	0
T27	0	227709	0	0
T52	1758	447	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1211	1211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	212037395	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1211	1211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	212037395	0	0
T4	630381	289229	0	0
T5	145678	18968	0	0
T6	0	5059	0	0
T10	0	20	0	0
T22	0	184238	0	0
T23	0	5910	0	0
T24	0	11781	0	0
T25	0	207382	0	0
T27	0	102483	0	0
T52	1758	246	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1211	1211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	327928726	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1211	1211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	327928726	0	0
T1	43698	7577	0	0
T2	2684	263	0	0
T3	2544	286	0	0
T52	1758	316	0	0
T53	10960	1436	0	0
T54	999	40	0	0
T55	1230	485	0	0
T56	18955	2945	0	0
T57	19284	2928	0	0
T58	827	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1211	1211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	596886158	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1211	1211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	596886158	0	0
T1	43698	6965	0	0
T2	2684	243	0	0
T3	2544	691	0	0
T52	1758	183	0	0
T53	10960	1320	0	0
T54	999	40	0	0
T55	1230	246	0	0
T56	18955	2728	0	0
T57	19284	2686	0	0
T58	827	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	43698	43626	0	0
T2	2684	2432	0	0
T3	2544	2351	0	0
T52	1758	1675	0	0
T53	10960	10076	0	0
T54	999	917	0	0
T55	1230	1174	0	0
T56	18955	17324	0	0
T57	19284	17855	0	0
T58	827	766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1211	1211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0