Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1345921	0	0
entropy_period_rd_A	2147483647	2037	0	0
intr_enable_rd_A	2147483647	2608	0	0
prefix_0_rd_A	2147483647	2111	0	0
prefix_10_rd_A	2147483647	2141	0	0
prefix_1_rd_A	2147483647	2220	0	0
prefix_2_rd_A	2147483647	2089	0	0
prefix_3_rd_A	2147483647	2191	0	0
prefix_4_rd_A	2147483647	2173	0	0
prefix_5_rd_A	2147483647	2144	0	0
prefix_6_rd_A	2147483647	1982	0	0
prefix_7_rd_A	2147483647	2143	0	0
prefix_8_rd_A	2147483647	2157	0	0
prefix_9_rd_A	2147483647	2227	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1345921	0	0
T4	630381	58854	0	0
T5	145678	0	0	0
T14	0	24985	0	0
T17	0	27066	0	0
T21	0	29573	0	0
T52	1758	3	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	2	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T104	0	37178	0	0
T105	0	46191	0	0
T106	0	37790	0	0
T107	0	24234	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2037	0	0
T3	2544	10	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	56	0	0
T135	0	21	0	0
T136	0	185	0	0
T137	0	101	0	0
T138	0	56	0	0
T139	0	52	0	0
T140	0	40	0	0
T141	0	267	0	0
T142	0	26	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2608	0	0
T3	2544	10	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	41	0	0
T135	0	44	0	0
T136	0	219	0	0
T137	0	109	0	0
T138	0	37	0	0
T139	0	66	0	0
T140	0	58	0	0
T141	0	231	0	0
T142	0	42	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2111	0	0
T3	2544	5	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	37	0	0
T135	0	12	0	0
T136	0	206	0	0
T137	0	116	0	0
T138	0	59	0	0
T139	0	47	0	0
T140	0	72	0	0
T141	0	199	0	0
T142	0	13	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2141	0	0
T3	2544	11	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	41	0	0
T135	0	29	0	0
T136	0	203	0	0
T137	0	100	0	0
T138	0	39	0	0
T139	0	85	0	0
T140	0	60	0	0
T141	0	216	0	0
T142	0	11	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2220	0	0
T3	2544	4	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	50	0	0
T135	0	20	0	0
T136	0	208	0	0
T137	0	124	0	0
T138	0	64	0	0
T139	0	106	0	0
T140	0	95	0	0
T141	0	250	0	0
T142	0	18	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2089	0	0
T3	2544	3	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	30	0	0
T135	0	13	0	0
T136	0	187	0	0
T137	0	152	0	0
T138	0	49	0	0
T139	0	67	0	0
T140	0	66	0	0
T141	0	269	0	0
T142	0	15	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2191	0	0
T3	2544	9	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	42	0	0
T135	0	16	0	0
T136	0	218	0	0
T137	0	94	0	0
T138	0	75	0	0
T139	0	55	0	0
T140	0	75	0	0
T141	0	261	0	0
T142	0	20	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2173	0	0
T3	2544	8	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	52	0	0
T135	0	10	0	0
T136	0	218	0	0
T137	0	132	0	0
T138	0	59	0	0
T139	0	71	0	0
T140	0	73	0	0
T141	0	224	0	0
T142	0	23	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2144	0	0
T3	2544	6	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	64	0	0
T135	0	24	0	0
T136	0	206	0	0
T137	0	148	0	0
T138	0	70	0	0
T139	0	55	0	0
T140	0	39	0	0
T141	0	234	0	0
T142	0	17	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1982	0	0
T3	2544	4	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	18	0	0
T135	0	24	0	0
T136	0	102	0	0
T137	0	170	0	0
T138	0	50	0	0
T139	0	86	0	0
T140	0	52	0	0
T141	0	221	0	0
T142	0	32	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2143	0	0
T3	2544	1	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	75	0	0
T135	0	20	0	0
T136	0	188	0	0
T137	0	116	0	0
T138	0	51	0	0
T139	0	77	0	0
T140	0	90	0	0
T141	0	231	0	0
T142	0	40	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2157	0	0
T3	2544	15	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	35	0	0
T135	0	13	0	0
T136	0	245	0	0
T137	0	101	0	0
T138	0	73	0	0
T139	0	49	0	0
T140	0	57	0	0
T141	0	282	0	0
T142	0	41	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2227	0	0
T3	2544	9	0	0
T52	1758	0	0	0
T53	10960	0	0	0
T54	999	0	0	0
T55	1230	0	0	0
T56	18955	0	0	0
T57	19284	0	0	0
T58	827	0	0	0
T59	915	0	0	0
T134	208816	58	0	0
T135	0	35	0	0
T136	0	188	0	0
T137	0	89	0	0
T138	0	69	0	0
T139	0	78	0	0
T140	0	71	0	0
T141	0	266	0	0
T142	0	42	0	0